Obviousness

An analysis of US patent 7349448 under 35 U.S.C. § 103 for obviousness requires identifying combinations of prior art references that would render the claims obvious, along with a motivation for a person having ordinary skill in the art (POSITA) to combine them. The priority date for US7349448 is August 1, 2003.

The core inventive features of US7349448, as described in its abstract and detailed description, include:

1. Distributed/Staged Multiplexing: The multiplexing functionality is broken down into multiple cascaded stages (e.g., "first stage logic" and "second stage logic"), where each stage receives data from a previous stage and its own associated data connection (Claim 1, Description).
2. Per-Stage Data Selection: Each stage selects between the data received from a previous stage and its locally associated data word based on select signals (Claim 1, Description).
3. Tristate Drivers for Selection: The selection within each stage is implemented using tristate drivers, where outputs of different drivers are electrically coupled to a common connection (Claim 1).
4. Built-in Repeater Functionality: The tristate drivers, when passing data from a previous stage, also serve to increase the signal strength of the data word, acting as repeaters to enable longer distances between data connections (Claim 4, Description).
5. Clocked Latches for Control: Latch circuits are used to synchronize the data words and select signals with clock signals (Claim 7).
6. Out-of-Phase Clocking to Prevent Drive Fight: The system uses out-of-phase clock signals to control the timing of the tristate drivers, preventing "drive fight" where multiple drivers simultaneously attempt to drive a connection (Description).

The patent itself highlights the problem it aims to solve: conventional multiplexers are "prone to routing congestion" and "speed and noise degradation typically increases as the distances between the data connections increase" when using tristate multiplexors (Description, BACKGROUND).

Prior Art Combinations and Motivation for Combination:

Based on the titles of the cited prior art and common knowledge in digital circuit design prior to August 2003, the following combinations would render the claims of US7349448 obvious:

Combination 1: EP0492862A2 ("Daisy chain multiplexer") + US5677638A ("High speed tristate bus with multiplexers for selecting bus driver") + US6415353B1 ("Read/write buffers for complete hiding of the refresh of a semiconductor memory") + "Combinational Building Blocks" (Non-Patent Literature)

• EP0492862A2 (Daisy chain multiplexer): This reference strongly suggests a distributed or cascaded multiplexer architecture where multiple multiplexing elements are connected in series. This directly teaches the concept of distributed/staged multiplexing (Feature 1) and implicitly the idea of per-stage data selection (Feature 2) as data would be passed along the chain for selection at appropriate points.
• US5677638A (High speed tristate bus with multiplexers for selecting bus driver): This patent directly addresses the use of tristate drivers in a multiplexing context for selecting bus drivers (Feature 3). The title explicitly mentions "high speed tristate bus," indicating concerns about signal integrity and performance. A POSITA would understand that tristate drivers are commonly used to enable selective connection of one of several data sources to a shared bus.
• US6415353B1 (Read/write buffers for complete hiding of the refresh of a semiconductor memory): This reference teaches the use of buffers, which are a form of drivers or repeaters, to maintain signal integrity or improve performance in memory systems. A POSITA would recognize that such buffers, when implemented with tristate drivers operating in an enabled state, inherently provide signal amplification and repeater functionality (Feature 4). The motivation to use them is explicitly for performance or integrity over a data path.
• "Combinational Building Blocks" (e.g., from www.ece.msstate.edu/~reese/EE3714/combblocks/): This non-patent literature provides fundamental teachings of digital logic. It describes how to construct larger multiplexers from smaller ones, illustrating hierarchical or cascaded multiplexing. It also introduces "controlled switches", which can be understood as tristate buffers, and the concept of a "bus" as a collection of data lines. This document provides the foundational knowledge for understanding and implementing multiplexing and bus structures.

Motivation for Combination 1:
A POSITA, facing the known problems of routing congestion and signal degradation over long distances in conventional centralized multiplexers or simple tristate multiplexers (as acknowledged in US7349448's background), would be motivated to combine these elements. The motivation would be to:

• Reduce routing congestion and simplify layout: By distributing the multiplexer functionality into a daisy chain or cascaded stages as taught by EP0492862A2 and "Combinational Building Blocks."
• Implement flexible data selection: By using tristate drivers as taught by US5677638A for selecting which data source drives the bus at each stage.
• Overcome signal degradation over distance: By leveraging the inherent repeater capability of the tristate drivers (as informed by US6415353B1's teaching of buffers for signal integrity) that are already part of the multiplexing stages. This would be a natural engineering optimization to maintain signal strength and speed over longer interconnects on an IC. The understanding of basic MUX construction from "Combinational Building Blocks" would guide the integration of these concepts.

Combination 2: Combination 1 + Common knowledge of clocked latches and out-of-phase clocks.

• Building on Combination 1: The combined system from Combination 1 provides the distributed tristate multiplexer with repeater functionality.
• Clocked Latches (Feature 5): The use of latches for timing and holding control signals and data in synchronous digital circuits is a fundamental and widely known principle taught in any basic digital logic curriculum or textbook, including the general scope of "Combinational Building Blocks." Latches ensure that signals are stable when presented to the inputs of logic elements.
• Out-of-Phase Clocking (Feature 6) for Drive Fight Prevention: In high-speed bus designs utilizing multiple tristate drivers (as in US5677638A and US5936424A), the problem of "drive fight" or bus contention (where more than one driver attempts to drive the bus simultaneously) is a well-recognized issue. A standard solution in the art involves using precise timing mechanisms, such as phased or out-of-phase clock signals, to enable and disable drivers sequentially or to ensure only one driver is active at a time. This technique would be considered routine engineering practice for a POSITA designing a reliable synchronous bus system.

Motivation for Combination 2:
A POSITA designing the distributed tristate multiplexer (from Combination 1) for a high-speed integrated circuit application would be strongly motivated to incorporate synchronous control to ensure reliable operation.

• Reliable Data Transfer: Latches would be added to synchronize the select signals and data words with the system clock, guaranteeing stable inputs to the tristate drivers and preventing glitches (as taught by basic digital design principles).
• Preventing Bus Contention: To actively avoid "drive fight" on the shared connections between tristate drivers, the POSITA would be motivated to implement a robust timing scheme. The use of out-of-phase clocks for controlling the enable/disable signals of the tristate drivers is a well-known and conventional method to ensure non-overlapping driver activation, thereby preventing bus contention and improving signal integrity and system reliability in high-speed applications. This is a common design consideration for any bus system with multiple drivers.

In summary, the claims of US7349448 would be obvious to a POSITA by combining existing knowledge of distributed multiplexing (EP0492862A2, "Combinational Building Blocks"), the use of tristate drivers for bus selection (US5677638A), the signal boosting capability of buffers/drivers (US6415353B1), and standard synchronous circuit design practices, including latches and out-of-phase clocking to manage timing and prevent contention. The motivation for such combinations would be to address recognized challenges in high-speed data routing on integrated circuits, such as routing congestion, signal degradation over distance, and bus contention.