US 7320935

US 7,320,935 B2 — Patent Overview

Title: Semiconductor device using an interconnect
Patent number: US 7,320,935 B2 (application US 10/635,892, filed 2003-08-05)
Inventor(s): Jihperng Leu; Christopher D. Thomas
Assignee: Intel Corp (original and current assignee per listing)
Prior art date: 2001-12-19
Publication: US 2004/0026786 A1 published 2004-02-12; patent granted 2008-01-22
Status: Expired – Lifetime; anticipated expiration 2021-12-19

Purpose and plain-language scope (from the supplied excerpt):
The text indicates the patent concerns forming interconnects in a semiconductor device. Keywords given are forming, ILD layer (interlayer dielectric), recess, interconnect, and layer. The classification entries describe a fabrication process involving: forming openings or recesses in a dielectric region (including dual-damascene structures); forming conductive barrier/adhesion or liner layers within those openings; filling conductive material into holes, grooves, or trenches; treatments of the barrier/liner layers without adding elements (including thermal treatment); and dielectric parts comprising thin functional dielectric layers (etch-stop, barrier, capping, or liner layers), including multilayer versions.

Note on available text: The supplied source is largely bibliographic and classification data. The abstract and claims were not included in the excerpt shown. The excerpt therefore does not establish:

• The specific independent claim language or claim count
• The precise process sequence or materials claimed
• The named field of invention or explicit technical problem addressed
• Any embodiment details, examples, or figures
• Priority/continuation relationships beyond the listed dates
• Whether the claims are limited to dual-damascene or to a particular dielectric or metal

No litigation, ownership-transfer, validity, or prior-art analysis was performed, per scope. No facts beyond the source were assumed.

Source: https://patents.google.com/patent/US7320935/en