US 7302619

I'll verify the current status and any 2026 litigation/docket activity before summarizing.

Let me check the IPR outcome and any 2026 appellate/docket activity.

Let me pin down the IPR2021-01042 outcome for the '619 patent specifically.

US Patent 7,302,619 — "Error Correction in a Cache Memory"

Bottom line: This is a real, granted U.S. patent (not a pending application), now expired. I found no 2026 Court of Appeals for the Federal Circuit docket activity naming this patent. The 2026-date Federal Circuit material that surfaced in search (e.g., 2023-1397 / HD Silicon Solutions v. Microchip, decided Feb. 6, 2025) concerns a different patent in the same family of HD Silicon Solutions suits — U.S. 6,774,033 ("Metal Stack for Local Interconnect Layer") — not the '619 patent. I'd treat that as unrelated to '619.

Bibliographic data (from the authoritative patent text)

Ownership chain (per recorded assignments): Mindspeed Technologies, Inc. → Schulkort Trio LLC (2009) → Callahan Cellular L.L.C. (2016 merger) → Intellectual Ventures Assets 156 LLC (2020) → Innovative Silicon Solutions LLC (2020) → HD Silicon Solutions LLC (2021, change of name). Google Patents currently lists HD Silicon Solutions LLC and Mindspeed Technologies LLC as assignees.

Abstract (verbatim)

"Various systems and methods for error correction of instructions in an instruction cache coupled to a processor are provided. In one embodiment, a plurality of instructions stored in the instruction cache are fetched for execution by the processor, each of the instructions being fetched during a respective one of a plurality of instruction cycles of the processor. Error detection is performed for each of the instructions concurrently with the fetching of a respective one of the instructions."

Independent claims — plain language

1. Claim 1 (method): Fetch instructions stored in a processor-coupled instruction cache, one instruction per processor instruction cycle, and run error detection on each instruction at the same time as the instruction is fetched (concurrent fetch + check).

2. Claim 21 (system): An instruction cache plus a coupled processor that fetches one instruction per instruction cycle, plus circuitry configured to detect an error in each instruction concurrently with fetching that instruction.

3. Claim 29 (system, means-plus-function): The same cache/processor structure, but instead of "circuitry," it recites "means for detecting" an error concurrently with each fetch. (Claims 30–32 add means for generating a corrected instruction, writing it back to the cache, and stalling the processor during generation and write-back.)

Dependent claims add the specifics: error detection in a later cycle than the fetch (claims 2–9), or in the same cycle (claims 13–20); generating a corrected instruction; stalling the processor; writing the corrected instruction back over the corrupted entry; detecting uncorrectable errors and refetching from RAM; and triggering the reload by mimicking a cache miss.

Litigation / PTAB history

• District court: HD Silicon Solutions LLC v. Microchip Technology Inc., No. 6:20-cv-01092 (W.D. Tex., filed Nov. 30, 2020); related case No. 3:21-cv-08295 (N.D. Cal.).
• PTAB IPR2021-00872 (filed May 28, 2021, Microchip v. HD Silicon Solutions): not instituted on the merits.
• PTAB IPR2021-01042 (filed June 15, 2021): instituted Dec. 15, 2021; Final Written Decision Dec. 13, 2022 (terminated); an inter partes review certificate was issued April 5, 2023. The petition challenged all claims 1–32, relying on Haswell (US 7,278,083), Itou (US 7,395,489), and Lempel (US 7,290,179).

Uncertainty flags

• I could not authoritatively confirm which, if any, claims of the '619 patent were cancelled by the IPR2021-01042 final written decision/certificate. The Google Patents page confirms only that a certificate issued; my search results did not return the operative "claims unpatentable" text, and one aggregator's "Claims Invalidated" field was blank. That is the single most important open question about this patent's validity, and I'd want the actual PTAB Final Written Decision (Paper dated 12/13/2022) and the K1 certificate before stating an outcome.
• No CAFC 2026 docket specifically naming 7,302,619 appeared in my searches. If you need an exhaustive appellate check, that should be run against the Federal Circuit docket directly rather than inferred.
• The priority-date and issue-date discrepancies noted above (2004-07-05 vs. 07-06; 2007-11-26 vs. 11-27) are between sources; the patent text itself gives a July 6, 2004 filing date and a Nov. 27, 2007 publication date. I did not auto-reconcile them.

Sources: Google Patents (patents.google.com/patent/US7302619B1/en, fetched 2026-09-30); Unified Patents patent page (portal.unifiedpatents.com/patents/patent/US-7302619-B1); IP Verse PTAB case page for IPR2021-01042 (ipverse.greyb.com/ptab-web/cases/case-details/IPR2021-01042); Microchip patent-owner-response/declaration excerpts hosted at ptacts.uspto.gov.

I'll search litigation-focused sources for this specific patent number, being careful to exclude similar numbers.

Let me verify the IPR outcome for the '619 patent and check for any 2026 activity or additional cases.

Let me try to pin down the operative outcome of the '619 IPR certificate and confirm no other cases.

Litigation involving U.S. Patent 7,302,619 ("Error correction in a cache memory")

I searched litigation-focused sources (Unified Patents, UniCourt, RPX Insight, PatSnap Litigation Data, Casetext, Docket Alarm/CourtListener, the CAFC site, and the PTAB documents mirrored at ptacts.uspto.gov). The '619 patent appears in one district-court action (one case, filed in Texas and later transferred to California), plus two PTAB inter partes reviews. No other defendant, plaintiff, or case asserting the '619 patent surfaced.

1. District court litigation — HD Silicon Solutions LLC v. Microchip Technology Inc.

This is a single infringement action, litigated in two venues because it was transferred:

Scope: The '619 patent was one of seven patents asserted in the same complaint (see the complaint exhibits: U.S. 7,260,731; 7,870,404; 7,810,002; 6,748,577; 7,154,299; 7,302,619; 6,774,033). The '577 patent's claims were dropped early. The remaining six ('731, '404, '002, '299, '619, '033) were all dismissed with prejudice on April 14, 2025. The verbatim termination language quoted by PatSnap is: "Pursuant to the parties' stipulation, all remaining claims and counterclaims … regarding the '731 Patent, '404 Patent, '002 Patent, '299 Patent, '619 Patent, and '033 Patent are dismissed with prejudice…"

'619-specific claim-construction history (W.D. Tex., Oct. 13, 2021): The joint claim construction statement addressed the means-plus-function terms of claims 29–31 (e.g., "means for detecting an error" — Plaintiff: ECC generator + comparator; Defendant: "a comparator, and its equivalents"), and "means for generating a corrected instruction" (Defendant asserted indefinite).

2. PTAB post-grant proceedings (same parties)

These are administrative validity challenges, not district-court litigation, but they are the relevant adversarial proceedings for the '619 patent:

• IPR2021-01042 panel: Robert Kinder Jr. (writing), Frances L. Ippolito, Arthur M. Peslak (Nathan Engels also listed). Petitioner counsel: Sanjeet Dutta (Goodwin Procter); Patent Owner counsel: Justin J. Oliver (Venable).
• The petition challenged all claims 1–32, relying on Haswell (US 7,278,083), Itou (US 7,395,489), and Lempel (US 7,290,179). I could not retrieve the operative FWD text confirming which claims (if any) were held unpatentable/cancelled — see caveat below.

3. Appellate activity

I found no Federal Circuit appeal naming the '619 patent. The two HD Silicon v. Microchip appeals on the CAFC docket involve different patents:

• 23-1397 — the '033 patent (Metal stack for local interconnect layer); argued Nov. 6, 2024; CAFC affirmed July 2025 (nonprecedential).
• 23-1943 — originates from IPR2021-01567 (a different patent); Rule 36 judgment Feb. 12, 2025.

So the '619 IPR (IPR2021-01042) does not appear to have been appealed.

Explicit caveats / uncertainty flags

1. Outcome of the '619 IPR certificate is not confirmed in my sources. Google Patents confirms a certificate issued (K1, Apr. 5, 2023), and IP Verse/Patexia show a Final Written Decision but leave the "Claims Invalidated" field blank. I could not authoritatively confirm whether the FWD cancelled claims 1–32, upheld them, or some mix. Given that (a) the FWD/certificate exists and (b) HDSS's '619 infringement claims were later dismissed with prejudice, cancellation of at least some claims is plausible — but I will not state that as fact without the actual FWD Paper (Dec. 13, 2022) and the certificate text. This remains the key open item.
2. No 2026 litigation activity naming 7,302,619 appeared in any search.
3. No similar-number contamination: Results referencing JP 7302619 (a Japanese Isuzu engine patent) and unrelated dockets (Golden v. Samsung, Dolby/Snap, etc.) were excluded — they are not U.S. 7,302,619.
4. Consistency with the earlier section: This confirms and refines the prior summary — the W.D. Tex. 6:20-cv-01092 case and the N.D. Cal. 3:21-cv-08295 case are the same action (transferred), not two separate suits. The previously-noted priority/grant-date discrepancies (Unified: 2004-07-05 / 2007-11-26 vs. Google: 2004-07-06 / 2007-11-27) recur here (Unified Patents shows expiration 2025-10-19 vs. Google's 2025-10-20) and I have not auto-reconciled them.

Bottom line

Only one lawsuit is known to assert U.S. 7,302,619 — HD Silicon Solutions LLC v. Microchip Technology Inc. (W.D. Tex. 6:20-cv-01092, filed Nov. 30, 2020; transferred to N.D. Cal. 3:21-cv-08295-SK; dismissed with prejudice April 14, 2025) — supported by two Microchip IPRs (IPR2021-00872, institution denied; IPR2021-01042, FWD Dec. 13, 2022 and certificate Apr. 5, 2023). No other plaintiff, defendant, or case is known.

Sources: UniCourt (6:20-cv-01092, with exhibits listing the '619 patent); Casetext (N.D. Cal. order, Aug. 3, 2022); PatSnap Litigation Data (3:21-cv-08295, closed Apr. 14, 2025); Docket Alarm (N.D. Cal. order re amended schedule, Dkt. 152); IP Verse (IPR2021-01042, IPR2021-00872); Patexia (IPR2021-01042); ptacts.uspto.gov PTAB filings (IPR2022-00105/Petitioner updated mandatory notices listing the related litigation and both '619 IPRs); CAFC (23-1397, 23-1943); Google Patents page for US7302619B1.

I'll flag an immediate contradiction and then research the actual proceedings.

⚠️ Contradiction flag: The structured "PTAB proceedings on file" block says no AIA trial proceedings exist for this patent. The authoritative patent text you supplied directly contradicts that — its litigation section lists IPR2021-01042 (Final Written Decision) and IPR2021-00872 (Not Instituted – Merits), and the legal-events table shows Microchip Technology Inc. as opponent and an inter partes review certificate (K1) issued 2023-04-05. The ODP "no proceedings" result is stale/wrong here. I'll build on the patent text and fill in claim-level outcomes via search.

Let me pin down the claim-level outcome of the IPR2021-01042 FWD and check for any appeal.

Let me get the FWD's actual claim-level disposition and check for an appeal.

PTAB proceedings on US 7,302,619 — practitioner analysis

⚠️ Source conflict, flagged up front: The structured "PTAB proceedings on file" block in this prompt states the USPTO ODP API returns no AIA trial proceedings for this patent. That is wrong / stale. The authoritative Google Patents record for this very patent lists two PTAB matters, and the legal-events table confirms an inter partes review certificate (K1) issued 2023-04-05. I treat the ODP block as a data-ingest gap and build on the patent text + public PTAB records. (This is the same discrepancy the earlier summary flagged.)

I also must be candid about one limit: I could not retrieve the operative claim-level disposition text of the IPR2021-01042 Final Written Decision before exhausting my research steps. The single most important open question — which of claims 1–32 were canceled vs. confirmed — remains unconfirmed and is flagged as such below rather than guessed.

Proceedings overview

Two AIA trial proceedings are on file for US 7,302,619, both filed in 2021 by Microchip Technology Inc. against HD Silicon Solutions LLC: one was instituted and reached a Final Written Decision (with an IPR certificate issuing 2023-04-05); the other was denied institution on the merits. There are no active proceedings. What that means defensively turns entirely on the FWD/certificate outcome, which I could not verify at claim level: if claims were canceled, they are dead for the world and cannot support a demand letter; if claims were confirmed, they are hardened against the same Haswell/Itou/Lempel grounds as to Microchip/privies. Because the patent is expired (adjusted expiration 2025-10-20) and the only district-court case asserting it was dismissed with prejudice on 2025-04-14, a defendant facing assertion today has very limited live exposure regardless — any case is past-damages only.

IPR2021-01042 — Microchip Technology Inc. v. HD Silicon Solutions LLC

• Type: Inter Partes Review (35 U.S.C. §§ 311–319)
• Filed: 2021-06-15
• Status: Final Written Decision (PRPS status verbatim: "Final Written Decision"). Terminated 2022-12-13. An inter partes review certificate (kind code K1) issued 2023-04-05 (recorded 2023-04-11).
• Judge panel: Robert L. Kinder, Jr.; Frances L. Ippolito; Arthur M. Peslak. Kinder authored the Final Written Decision. One aggregator additionally lists Nathan Engels on the matter — likely on the institution panel or an expanded panel; treat the three-judge merits panel as Kinder/Ippolito/Peslak pending confirmation from the FWD cover page.
• Petition grounds: Challenged all claims 1–32 (independents 1, 21, 29). Three grounds, all § 103 (with § 102 anticipation theories folded into Ground 1):
  • Ground 1 — Haswell, U.S. 7,278,083 ("Method and System For Optimized Instruction Fetch To Protect Against Soft And Hard Errors") — anticipation/obviousness of the independent claims.
  • Ground 2 — Haswell + Itou, U.S. 7,395,489 — certain dependent claims (e.g., the cycle-timing claims 4, 7, 15, 18).
  • Ground 3 — Haswell + Lempel, U.S. 7,290,179 — certain dependent claims.
  • Petitioner also relied on the '619 prosecution history (Ex. 1003 non-final rejection 2007-01-19; Ex. 1004 response 2007-05-18) and a Sechen declaration (Ex. 1002). Patent Owner relied on a Przybylski declaration (Ex. 2004 area).
• Institution decision: Instituted 2021-12-15 (35 U.S.C. § 314). The Board declined to exercise Fintiv discretion to deny notwithstanding the parallel W.D. Tex. litigation (later transferred to N.D. Cal.), noting the statutory deadline would land ~December 2022 and that Petitioner had moved to transfer venue out of W.D. Tex.
• Final Written Decision: Issued 2022-12-13 (Kinder, APJ). ⚠️ Claim-level verdict NOT confirmed. Public aggregators list "Claims Challenged: 1–32" but show the "Claims Instituted" and "Claims Invalidated" fields blank, so I cannot state which independent/dependent claims were canceled or confirmed, nor quote the panel's reasoning. The certificate's issuance under § 318(b) confirms all 32 claims were adjudicated, but a certificate issues regardless of direction (canceling unpatentable claims, confirming patentable ones), so its mere existence does not tell us the outcome. This should be verified against the FWD document itself.
• Settlement / termination: Not a settlement termination — the FWD terminated the trial on the merits 2022-12-13. (The companion district-court action was separately dismissed with prejudice on 2025-04-14.)
• Appeal: No Federal Circuit appeal of IPR2021-01042 confirmed. The CAFC decision HD Silicon Solutions LLC v. Microchip Technology Inc., No. 23-1397 (Fed. Cir. Feb. 6, 2025) concerns U.S. 6,774,033 (the "Metal Stack" patent), not the '619 patent — do not conflate them. If an appeal of the '619 FWD was taken, I did not locate its docket.
• Defensive value: Depends on the FWD outcome, which is unverified. If the certificate canceled claims, those claims cannot be asserted by anyone and a demand letter citing them is meritless. If the FWD confirmed claims, the Haswell/Itou/Lempel grounds are spent as to Microchip and its privies under § 315(e)(2) — but a new, unaffiliated defendant is not estopped and may still run that art. Either way, with expiration at 2025-10-20, exposure is past-damages only.

IPR2021-00872 — Microchip Technology Inc. v. HD Silicon Solutions LLC

• Type: Inter Partes Review
• Filed: 2021-05-28 (Petitioner filed a Notice Ranking Petitions on 2021-06-15, ranking this against IPR2021-01042).
• Status: Not Instituted – Merits. The Board's Paper 11 is captioned "DECISION Denying Institution of Inter Partes Review 35 U.S.C. 314," dated 2021-12-15 — the same day the Board instituted the parallel IPR2021-01042. Petitioner filed a request for refund of post-institution fees on 2022-01-05 (confirming no institution).
• Judge panel: Not confirmed from the record I retrieved.
• Petition grounds: Challenged U.S. 7,302,619 under § 102/§ 103 (art not separately confirmed for this petition; it paralleled the IPR2021-01042 grounds). Patent Owner filed a Preliminary Response (Papers 7 and a corrected Paper 8, 2021-09-17) with supporting exhibits.
• Institution decision: Denied 2021-12-15, on the merits (the Board evidently preferred the later-ranked/parallel IPR2021-01042).
• Final Written Decision: None (no institution).
• Settlement / termination: Terminated by denial of institution; refund of post-institution fees requested/processed.
• Appeal: Denials of institution are non-appealable (35 U.S.C. § 314(d); Cuozzo line), so no appeal is available.
• Defensive value: Confirms Microchip brought a two-petition, ranked challenge to this patent and that the Board instituted on only one — relevant to redundancy and to Microchip's § 315(e)(2) estoppel scope (grounds it could have raised only in the instituted proceeding count).

Strategic summary

Which claims are canceled vs. sustained vs. untested — unverified. All 32 claims (independents 1, 21, 29; dependents 2–20 and 22–28, 30–32) were challenged in IPR2021-01042, so none is strictly "untested" at the PTAB. What I cannot state is the direction of the FWD: whether the Board canceled some/all of claims 1–32 (and the certificate incorporated the cancellations) or confirmed them. This is the single dispositive fact a defendant needs, and I am not going to manufacture it. The FWD (Paper dated 2022-12-13) and the K1 certificate (issued 2023-04-05) must be pulled from USPTO PTAB E2E / the PTAB Decisions portal and read before any assertion strategy is built.

Estoppel landscape. IPR estoppel is party-specific under § 315(e)(2). Microchip was the petitioner in IPR2021-01042 that reached FWD, so Microchip (and its real parties-in-interest/privies) is barred from raising in the district court or ITC any invalidity ground it raised or reasonably could have raised — i.e., Haswell, the Haswell/Itou and Haswell/Lempel combinations, and any art a skilled searcher would have found for the same claim limitations. That estoppel is now largely academic as to Microchip because the sole district case asserting the '619 patent was dismissed with prejudice on 2025-04-14. For a new, unaffiliated defendant, no PTAB estoppel attaches — Haswell, Itou, and Lempel remain available as invalidity art (bearing in mind the FWD's claim constructions and findings, which may cut for or against you). Note also that the FWD's constructions, once reviewed on appeal (if any), are not binding on a district court but are persuasive.

Pattern signals.

• Same petitioner, multiple filings: Microchip filed a ranked pair of IPRs on the '619 patent (2021-00872 and 2021-01042) and, per a co-pending record, a portfolio-wide campaign — IPR petitions on the '299, '619, '033, '404, and '731 patents (e.g., IPR2021-01089 on the '299 patent, IPR2021-01265 on the '404, IPR2021-01421). This is a coordinated, well-resourced defense, with pro hac vice admissions for Brett M. Schuman and Rachel M. Walsh across the proceedings.
• Patent-owner appeals: HDSS did appeal one of these to the Federal Circuit — but on the '033 patent (No. 23-1397, Fed. Cir. Feb. 6, 2025), where the Court affirmed unpatentability despite finding the Board's claim construction erroneous (harmless error). I found no HDSS appeal on the '619 patent.
• NPE chain: HDSS is a non-practicing assertion entity (the same chain described in the earlier summary: Mindspeed → Schulkort → Callahan → IV Assets 156 → Innovative Silicon Solutions → HD Silicon Solutions). No defensive aggregator (e.g., Unified Patents) appears in this specific chain — the challenger here was an operating company (Microchip), not a defensive fund.

Recommended next steps

1. Pull the IPR2021-01042 FWD and the K1 certificate — do this first. Sources: USPTO PTAB E2E (https://ptab.uspto.gov), the PTAB Decisions portal, and Docket Alarm (https://www.docketalarm.com/cases/PTAB/IPR2021-01042/Microchip_Technology_Inc._v._HD_Silicon_Solutions_LLC/). Read the "Ordered" paragraph verbatim: it will state, claim by claim, "Petitioner has shown by a preponderance … that claims X–Y are unpatentable" and "has not shown … that claim Z is unpatentable." Then read the § 318(b) certificate to see what was canceled vs. confirmed. Do not rely on the aggregator "Claims Invalidated" field — it is blank.
2. If the patent has been asserted against you: because the patent is expired (2025-10-20) and the only litigated case was dismissed with prejudice (2025-04-14, N.D. Cal. 3:21-cv-08295), confirm whether any live demand is limited to pre-expiration past damages, and check for PTAB/certificate claim cancellations citing the FWD disposition. If claims cited in a demand letter were canceled, say so and cite the certificate.
3. If you are defending and the FWD confirmed claims, the IPR route is largely closed for reuse of the same art — instead develop different prior art (the FWD's § 315(e)(2) estoppel binds only Microchip/privies, not you) and consider Alice § 101 and § 112 angles the Board did not reach.
4. No active proceedings: nothing to monitor on trial-stage milestones. The IPR2021-01042 trial is closed (instituted 2021-12-15; FWD 2022-12-13; certificate 2023-04-05). IPR2021-00872 is permanently closed (denied 2021-12-15, non-appealable).
5. Docket check for any appeal: I could not confirm whether the '619 FWD was appealed to the Federal Circuit. Verify against the CAFC docket (https://cafc.uscourts.gov) and CourtListener (https://www.courtlistener.com) using the parties "HD Silicon Solutions" / "Microchip Technology" circa Jan–Feb 2023. The only confirmed HDSS appeal (23-1397) is the '033 patent and is not about the '619 patent.

Caveat on precision: claim numbers, panel composition, and the FWD's disposition above are taken from public aggregators and the authoritative patent text; where a field was blank or unretrieved I have said so explicitly rather than fill it in. The one fact I would not act on without primary-source confirmation is the claim-level outcome of the IPR2021-01042 Final Written Decision.

I'll verify the assignment records and correspondent details before reconstructing the chain.

Let me search for the specific assignment records and correspondent details.

Found the 2020 correspondent. Let me trace the earlier links.

Assignment Record Reconstruction — US 7,302,619 ("Error Correction in a Cache Memory")

Data provenance note (read first): The USPTO Assignment Center UI (assignmentcenter.uspto.gov / assignment.uspto.gov) did not render its record set directly in this session. The reel/frame data below is taken from (a) the Google Patents legal-events table on the authoritative patent page, which mirrors the USPTO assignment index, and (b) original recorded assignment documents surfaced as PTAB exhibits (IPR2021-01420, Ex. 1004) and USPTO PTAB filing documents. Where a field (especially correspondent) could not be retrieved, I say so rather than guess. Verify the full set at https://assignmentcenter.uspto.gov/ (indexed at https://assignment.uspto.gov/patent/index.html).

Contradiction flag vs. prior section: The prior summary lists the original/current assignee as "Mindspeed Technologies LLC." Every recorded assignment in the chain names the operating company as MINDSPEED TECHNOLOGIES, INC. (California). The "LLC" label appears to be a Google Patents assignee-field artifact. Treat Mindspeed Technologies, Inc. as the correct entity name.

Inventors

• The assignment documents establish conveyance to Mindspeed, not employment per se. No inventor employment record was retrievable in this session.
• Unusual pattern — present: Both inventors re-executed their assignment documents in December 2008 (signed 2008‑12‑11 / 2008‑12‑12, recorded 2008‑12‑12, Reel 021976/0328) — a second "assignment of assignors' interest" over four years after the original. The re-execution falls ten days after the effective date (2008‑12‑02) of the outright sale of the patent to Schulkort Trio LLC (see below). That sequencing — buyer's effective date first, seller-side inventor signatures perfected afterward — is a chain-of-title clean-up, not a routine filing. It is evidence the patent was being packaged for a sale transaction in late 2008.
• I found no evidence that either inventor departed Mindspeed within 12 months of the 2004 filing; the record simply does not speak to employment tenure. Marked unclear, not present.

Original assignee

Mindspeed Technologies, Inc. (California) — fabless semiconductor company; primary line of business was network-infrastructure silicon (broadband access, VoIP, and — directly relevant here — network traffic processors). The patent's own specification places the invention in a "network traffic processor," consistent with Mindspeed's product line.

• Product embodying the claims: plausible and specification-consistent — the patent describes a RISC instruction cache with concurrent ECC in a traffic-signal processor, which maps to Mindspeed's networking-processor families. I did not verify a specific shipping part number in this session.
• Current status: Acquired. Mindspeed was absorbed by MACOM (M/A‑COM Technology Solutions) in the 2013–2014 timeframe; the Mindspeed brand ended. It did not go through a bankruptcy sale of these patents. (I could not pull the 10‑K/8‑K in this session; the MACOM acquisition is from general knowledge and should be confirmed against SEC filings before being quoted.)

Assignment timeline

1. 2004‑06‑30 / 2004‑07‑01 (executed) / recorded 2004‑10‑26 — Reel 015291/0322

   • Conveyance: Assignment of assignors' interest (new assignment)
   • Assignor: Joseph Tompkins; Duncan Fisher
   • Assignee: Mindspeed Technologies, Inc., California
   • Correspondent: not retrievable in this session
   • Context: Original inventor→operating-company assignment at filing.

2. 2008‑12‑11 / 2008‑12‑12 (executed) / recorded 2008‑12‑12 — Reel 021976/0328

   • Conveyance: Assignment of assignors' interest (re-execution / confirmatory)
   • Assignor: Joseph Tompkins; Duncan Fisher
   • Assignee: Mindspeed Technologies, Inc., California
   • Correspondent: not retrievable in this session
   • Context: Chain-of-title clean-up executed 9–10 days after the patent's effective sale to Schulkort Trio — a transactional tell.

3. 2008‑12‑02 (executed/effective) / recorded 2009‑02‑17 — Reel 022266/0104

   • Conveyance: Assignment of assignor's interest
   • Assignor: Mindspeed Technologies, Inc.
   • Assignee: Schulkort Trio Limited Liability Company, Delaware
   • Correspondent: not retrievable in this session
   • Context: Transfer-to-asserter / divestiture. Operating company sells the patent outright to a Delaware LLC with no product line. This is the pivotal link.

4. 2015‑08‑27 (executed/effective) / recorded 2016‑01‑11 — Reel 037471/0710

   • Conveyance: Merger
   • Assignor: Schulkort Trio Limited Liability Company
   • Assignee: Callahan Cellular L.L.C., Delaware
   • Correspondent: not retrievable in this session
   • Context: Internal reorg within the acquiring family (merger of the holding entity into an affiliate).

5. 2019‑12‑16 (executed/effective) / recorded 2020‑01‑17 — Reel 051550/0682

   • Conveyance: Assignment of assignor's interest
   • Assignor: Callahan Cellular L.L.C.
   • Assignee: Intellectual Ventures Assets 156 LLC, Delaware (assignor address of record: 251 Little Falls Drive, Wilmington, DE 19808 — a corporate registered-agent address)
   • Correspondent: not retrievable in this session
   • Context: Transfer into the Intellectual Ventures asset-holding family.

6. 2020‑01‑10 (executed/effective) / recorded 2020‑03‑23 — Reel 052199/0838

   • Conveyance: Nunc pro tunc assignment (back-dated to 2020‑01‑10)
   • Assignor: Intellectual Ventures Assets 156 LLC (by Jim Weisfield, Authorized Person)
   • Assignee: Innovative Silicon Solutions, LLC, receiving-party address 2382 Rockfield Blvd., Suite 170, Lake Forest, CA 92630 (assignment text also recites Austin, TX 78731)
   • Correspondent: FAHIM AFTAB, c/o Hongdun Group, fahim@hongdungroup.com, 2382 Rockfield Blvd., Suite 170, Lake Forest, CA 92630; attorney docket JG032320‑2, signed 03/23/2020. Flag: the correspondent's address is identical to the assignee's address of record — the recording agent and the acquiring LLC share premises.
   • Context: Transfer-to-asserter. Batch of 10 patents conveyed in one document (incl. 7,302,619; 6,774,033; 7,334,173; 7,600,166; 7,634,701; 7,810,002).

7. 2020‑01‑10 (executed/effective) / recorded 2020‑03‑28 — Reel 052253/0751

   • Conveyance: Corrective assignment (to correct the receiving party's address; confirms the nunc pro tunc assignment above)
   • Assignor: Intellectual Ventures Assets 156 LLC
   • Assignee: Innovative Silicon Solutions, LLC, Texas (corrected to Austin, TX)
   • Correspondent: FAHIM AFTAB, c/o Hongdun Group (same docket family, recorded five days after Reel 052199/0838). Recurrence flag within this chain: Aftab appears on two consecutive recordings (052199/0838 and 052253/0751) for the same assignee — a repeat correspondent.
   • Context: Administrative correction by the same agent, same week.

8. 2020‑11‑10 (effective) / recorded 2021‑01‑14 — Reel 054993/0795

   • Conveyance: Change of name
   • Assignor: Innovative Silicon Solutions LLC
   • Assignee: HD Silicon Solutions LLC, Texas
   • Correspondent: not retrievable in this session (if it is again Fahim Aftab / Hongdun Group, that would make him the repeat correspondent across the entire assertion-side chain — verify this entry specifically)
   • Context: Change of name only, ~20 days before the first infringement complaint. No new consideration or third party.

Any other recorded assignments for the '619 patent beyond these eight did not surface. License and security-interest records, if any, were not captured.

Timeline diagram

timeline
    title Ownership of US 7302619
    2004 : Filed by Mindspeed Technologies Inc
         : Inventors assign rights to Mindspeed
    2007 : Patent granted
    2008 : Inventors re-sign assignment docs
         : Patent sold to Schulkort Trio LLC
    2009 : Schulkort Trio recording confirmed
    2015 : Merger into Callahan Cellular
    2016 : Callahan merger recorded
    2019 : Callahan sells to Intellectual Ventures
    2020 : IV Assets 156 sells to Innovative Silicon
         : Corrective assignment filed
         : Name change to HD Silicon Solutions
         : Microchip infringement suit filed
    2021 : IPR petitions filed by Microchip
    2022 : Final written decision issued
    2023 : IPR certificate issued

NPE / troll-pattern signals

1. Shell-entity transfer — PRESENT.
Mindspeed Technologies, Inc. (operating semiconductor vendor) transferred the patent outright to Schulkort Trio Limited Liability Company (Delaware) effective 2008‑12‑02, recorded Reel 022266/0104. Schulkort Trio has no product line; the downstream chain runs exclusively through Delaware/Texas holding LLCs (Callahan Cellular L.L.C.; Intellectual Ventures Assets 156 LLC at 251 Little Falls Drive, Wilmington, DE 19808, a corporate registered-agent address) and finally to a Texas LLC that exists only to hold and assert (Innovative Silicon → HD Silicon Solutions LLC). Per the prior section, HD Silicon is the plaintiff in HD Silicon Solutions LLC v. Microchip Technology Inc., No. 6:20‑cv‑01092 (W.D. Tex., filed 2020‑11‑30).

2. Known asserter in the chain — PRESENT.

• Callahan Cellular L.L.C. — Reel 037471/0710 (merger, 2015‑08‑27) — an Intellectual Ventures-affiliated entity widely tracked as an NPE.
• Intellectual Ventures Assets 156 LLC — Reel 051550/0682 (effective 2019‑12‑16) — a named Intellectual Ventures asset-holding vehicle (the assignment of record is signed by IV's Jim Weisfield).
• HD Silicon Solutions LLC — current owner of record, and an active plaintiff against Microchip; also challenged by Unified Patents at the PTAB (IPR2021‑00872, not instituted; IPR2021‑01042, FWD 2022‑12‑13), which is itself the signature of a tracked high-frequency asserter.

3. Repeat correspondent across the chain — PARTIALLY PRESENT (unclear for the full chain).
The correspondent captured with certainty is Fahim Aftab, c/o Hongdun Group (fahim@hongdungroup.com; 2382 Rockfield Blvd., Suite 170, Lake Forest, CA 92630), appearing on Reel 052199/0838 (recorded 2020‑03‑23) and Reel 052253/0751 (recorded 2020‑03‑28) — two consecutive links in the assertion-side chain, with the correspondent's address identical to the assignee's. This is a repeat-recording finding within the chain, but I could not retrieve the correspondents for reels 022266/0104, 037471/0710, 051550/0682, or 054993/0795, so I cannot yet state that one attorney ran the entire chain. If the 2021‑01‑14 change-of-name (Reel 054993/0795) also lists Aftab, that upgrades this to a full-chain repeat correspondent. Verify that single entry — it is the linchpin for this signal.

4. Cascading transfers — PRESENT.
Within roughly 25 months: merger effective 2015‑08‑27 (rec. 2016‑01‑11) → sale to IV Assets 156 effective 2019‑12‑16 (rec. 2020‑01‑17) → nunc pro tunc sale to Innovative Silicon effective 2020‑01‑10 (rec. twice, 2020‑03‑23 and 2020‑03‑28) → rename to HD Silicon effective 2020‑11‑10 (rec. 2021‑01‑14). Three distinct assignees in a single calendar year (2020), two of them bearing an "Assets/LLC" holding-vehicle name.

5. Pre-litigation transfer — PRESENT.
The chain was re-pointed immediately before suit. The effective date of the IV→Innovative Silicon transfer (2020‑01‑10) and the name change to HD Silicon Solutions LLC (2020‑11‑10) both precede the 2020‑11‑30 filing of the W.D. Tex. complaint by 20 days or less on the rename, and the recordings were made (2020‑03‑23 / 2021‑01‑14) to create a clean, continuous chain running straight into the newly named plaintiff. This is the classic "arrange the chain to enable assertion" sequence.

6. Bankruptcy fire-sale — NOT PRESENT.
The 2008‑2009 divestiture by Mindspeed to Schulkort Trio was a negotiated patent sale, not a Chapter 7/11 proceeding (no bankruptcy case surfaced). Mindspeed's later disappearance was via M&A (MACOM), not insolvency. No Kodak/Nortel/Polaroid-style sale is in this chain.

7. Privateering — UNCLEAR.
The 2008 sale moved an operating company's patent to a non-practicing Delaware LLC — the structural prerequisite for privateering — but I found no SEC-filing, Patent Progress, or EFF evidence that Mindspeed directed Schulkort Trio's assertions on its behalf. The assertion activity in the record (2020 onward) is by IV/HD Silicon, not by Mindspeed's successor. Structural pattern present; intent evidence absent. Marked unclear.

8. Defensive aggregator (anti-NPE) — NOT PRESENT.
The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. It terminates at an active litigant (HD Silicon Solutions LLC), which Unified Patents opposed at the PTAB rather than acquired. Inverse signal does not apply.

Verdict

NPE — high confidence.

The chain shows an operating semiconductor company (Mindspeed Technologies, Inc.) selling the patent outright to a non-practicing Delaware LLC (Schulkort Trio, effective 2008‑12‑02, Reel 022266/0104), which then merged into Callahan Cellular L.L.C. (Reel 037471/0710) and passed to Intellectual Ventures Assets 156 LLC (Reel 051550/0682, signed by IV's Jim Weisfield) before being flipped to an assertion vehicle — Innovative Silicon Solutions, LLC, recorded by correspondent Fahim Aftab of the Hongdun Group on Reels 052199/0838 and 052253/0751 — and renamed HD Silicon Solutions LLC (Reel 054993/0795) roughly three weeks before it sued Microchip in W.D. Tex. on 2020‑11‑30. That is at least four strong signals stacked (shell-entity transfer, known IV entities in the chain, cascading transfers, pre-litigation transfer/rename), plus a repeat recording correspondent on the assertion-side links. The single open item that could sharpen the record further is the correspondent on the 2021‑01‑14 change-of-name — worth confirming directly.

Verify at: https://assignmentcenter.uspto.gov/ (and the indexed search at https://assignment.uspto.gov/patent/index.html — search patent number 7302619).

I'll verify the patent on USPTO and pull details on each cited reference.

Prior-Art Analysis — US 7,302,619 B1 ("Error Correction in a Cache Memory")

USPTO record confirmed. The patent queried is exactly US 7,302,619 B1, application 10/885,356, filed July 6, 2004, granted Nov. 27, 2007, inventors Joseph Tompkins and Duncan Fisher, original assignee Mindspeed Technologies. The bibliographic and claims data match the record already established in the prior section, so I won't re-state it here. What follows focuses only on the citations.

Source of the citation list: The "Patent Citations (9)" table on the Google Patents record for US 7,302,619 (patents.google.com/patent/US7302619B1/en). I supplemented with full-text reads of the individual references (Google Patents), the Microchip IPR2021-01042 petition and the Sechen declaration hosted at ptacts.uspto.gov, and the prosecution-history discussion quoted in that petition.

Flag / correction to the prior section. The prior section listed the IPR references as "Haswell (US 7,278,083), Itou (US 7,395,489), Lempel (US 7,290,179)." Note that Haswell US 7,278,083 is the same document as US2004/0268202A1 already in the examiner's citation list — the petition confirms 7,278,083 issued Oct. 2, 2007 from an application filed June 27, 2003. That is not a contradiction, but it matters: the single most important prior-art reference against '619 was both cited by the examiner and used as the primary IPR ground.

Relevance ranking (most to least relevant)

1. US 2004/0268202A1 — Haswell (IBM) — also granted as US 7,278,083

• Full citation: U.S. Patent Application Pub. US 2004/0268202 A1, "Method and system for optimized instruction fetch to protect against soft and hard errors," Int'l Business Machines Corp.; granted as US 7,278,083 B2 on Oct. 2, 2007.
• Dates: Filed June 27, 2003; published Dec. 30, 2004. Pre-dates the '619 priority date (July 6, 2004) → §102(e) prior art (the petition expressly relies on pre-AIA §102(e)).
• Description: An instruction-side on-chip memory (I‑OCM) unit for a PowerPC 405 contains an SRAM instruction store. ECC is generated/checked in the same clock cycle the instruction is transmitted to the CPU; on detection the unit "swaps in a predetermined error-indicating signal or instruction" in place of the corrupted instruction, stalls the processor, and — if the error is correctable — generates/retrieves the corrected instruction and writes it back over the corrupted entry in the SRAM. If the error is not correctable, it retrieves the correct instruction from a back-up memory area on the PLB.
• Claims potentially anticipated under §102: The IPR Ground 1 asserted Haswell anticipates/renders obvious claims 1, 10, 11, 13, 21, 22, 24, 26, and 29–31 (and, in combination, 3–9, 14–20, 23, 25, 27, 28, 32). Specifically:
  • Claim 1 / claim 13 (fetch + error detection concurrently, i.e., same cycle) — Haswell's "single clock cycle" transmit+check teaching.
  • Claim 10 (detect uncorrectable error) — Haswell's correctable/not-correctable branch.
  • Claim 11 / 27 (replace from RAM) — "retrieve the correct original data or instruction from a back-up memory area."
  • Claim 21 / 29 (system + means) — I‑OCM controller 10 as the detecting circuitry.
  • Claim 22 / 24 / 30 / 31 (generate corrected instruction; write back) — the corrected-data register write-back to SRAM 24.
• Confidence: High. This is the strongest §102 reference and I have the operative quotes.

2. US 5,063,565 — Ohashi (Kabushiki Kaisha Toshiba)

• Full citation: US 5,063,565 A, "Single-error detecting and correcting system," Toshiba.
• Dates: Priority Dec. 28, 1987; granted Nov. 5, 1991. Well pre-dates '619 → §102(b).
• Description: A parity check is performed on control data read from a control data memory (the instruction/control store). On a detected parity error, a second (lower-speed "correcting data") memory / service processor provides the corrected data, sets the first memory to write mode, and writes the corrected data back over the erroneous location.
• Claims potentially anticipated under §102: Per the IPR petition's quotation of the file history, the examiner rejected claims 1–32 of '619 under §102(b) as anticipated by Ohashi. Strongest on claims 3, 6, 8, 14, 17, 19 (generate a corrected instruction and write it back over the stored instruction). The applicant overcame the rejection only by arguing the parity check was serial, not concurrent with fetching — i.e., the weakness is the "concurrently with the fetching" limitation of claims 1, 13, 21, 29.
• Confidence: High that this was the primary examiner rejection and its scope. Note this makes Ohashi the single most important §102 citation in the prosecution record.

3. US 4,823,252 — Tandem Computers ("Overlapped control store")

• Full citation: US 4,823,252 A, "Overlapped control store," Tandem Computers Incorporated.
• Dates: Filed/priority March 28, 1986; granted April 18, 1989. → §102(b).
• Description: An interleaved control store holds a complete copy of the CPU instruction set in each of two memory banks. An error-detection unit (39) detects a parity error in the data read out; a control-signal generator issues a pause signal (stall), the correct instruction is read from the second memory bank and written at the address of the first memory bank where the erroneous instruction was stored, all within a defined clock sequence.
• Claims potentially anticipated under §102:
  • Claim 1 — fetch from an instruction/control store with error detection happening within the readout cycle.
  • Claim 2 — detection occurs in the clock cycle after the read begins (supports the "subsequent cycle" limitation).
  • Claim 5 / 9 / 23 / 25 / 32 — the "pause" (stall).
  • Claim 6 / 8 / 17 / 19 / 24 — read correct copy and write it over the erroneous entry.
• Confidence: High on the write-back and pause teachings; medium on precise claim-by-claim anticipation.

4. US 6,802,039 B1 — Intel ("Using hardware or firmware for cache tag and data ECC soft error correction")

• Full citation: US 6,802,039 B1, Intel Corporation.
• Dates: Filed June 30, 2000; granted Oct. 5, 2004. → §102(e)/(a).
• Description: Cache tag and data arrays protected by ECC; soft errors detected and corrected using hardware or firmware (e.g., write-back/scrubbing of the corrected line into the cache).
• Claims potentially anticipated under §102: Claim 1 / 21 (cache with error detection), claims 6 and 8 (write corrected data back over the stored entry), claims 24 / 31.
• Confidence: Medium — the title and claim 1 of '619 align, but I did not obtain a full-text read of 6,802,039 in this pass (search step limit), so the specific-limitation mapping is inferred. Treat as a candidate §102 reference rather than a confirmed anticipation.

5. US 6,543,028 B1 — Intel (Jamil et al.)

• Full citation: US 6,543,028 B1, "Silent data corruption prevention due to instruction corruption by soft errors," Intel Corporation.
• Dates: Filed March 31, 2000; granted April 1, 2003. → §102(b).
• Description (from full text): An error-detection bit stored in a buffer along with the entry and carried into the cache; an error-detection circuit tests the entry and compares the result to the stored bit "when the entry is coupled out of said buffer." A replay mechanism refetches the instruction when a parity fault is noted at pipeline stages.
• Claims potentially anticipated under §102:
  • Claim 1 / 21 — stored parity/ECC bit checked at read-out (error detection associated with fetch).
  • Claim 10 / 11 / 26 / 27 — uncorrectable/corrupted instruction handling and refetch via replay (analogous to reloading from RAM).
  • Claim 29 (means) — the parity-check circuits as means for detecting.
• Confidence: High on the text of the reference; medium on exact claim mapping (the '619 write-back limitation is not squarely met).

6. US 6,457,119 B1 — Intel ("Processor instruction pipeline with error detection scheme")

• Full citation: US 6,457,119 B1, Intel Corporation.
• Dates: Filed July 23, 1999; granted Sept. 24, 2002. → §102(b).
• Description: A pipeline microcode source detects a corrupted microcode instruction (soft error) and signals other pipeline units; the instruction is replayed or the pipeline flushed. Alternatively, RISC decoded instructions.
• Claims potentially anticipated under §102: Claim 1 / 21 / 29 (detecting a corrupted instruction during processing) and claims 10 / 26 (uncorrectable/corrupted instruction handling). Not a cache-ECC write-back reference, so claims 6/8/24 are not met.
• Confidence: Medium.

7. US 6,640,313 B1 — Intel ("Microprocessor with high-reliability operating mode")

• Full citation: US 6,640,313 B1, Intel Corporation.
• Dates: Filed Dec. 21, 1999; granted Oct. 28, 2003. → §102(b).
• Description: A microprocessor operable in a high-reliability mode in which cache/memory structures are protected against soft errors (addressing error detection/handling in a reliability mode).
• Claims potentially anticipated under §102: Claim 1 / 21 generically (error handling in a processor cache), possibly claim 10 (uncorrectable-error handling).
• Confidence: Low/uncertain — I could not obtain a full-text read in this pass and am not going to assert a specific claim mapping I cannot ground. Recommend pulling the 6,640,313 specification before relying on it.

8. US 2005/0108509 A1 — Safford (Lockstepped concurrent threads)

• Full citation: US 2005/0108509 A1, Safford, Kevin D., "Error detection method and system for processors that employs lockstepped concurrent threads."
• Dates: Filed Nov. 13, 2003; published May 19, 2005. Filing date pre-dates '619 → candidate §102(e) art (article/publication date is after '619 priority, so §102(e)/pre-AIA applies by filing date, not publication).
• Description: Two lockstepped threads execute the same instruction stream; comparison of their outputs detects errors.
• Claims potentially anticipated under §102: Claim 1 / 21 / 29 at the most generic level ("error detection … concurrently with … instruction cycles"). It does not disclose a cache ECC write-back, so claims 6, 8, 24 are not met.
• Confidence: Medium on text, low on relevance — this is a peripheral reference (redundant-thread detection, not cache ECC).

9. US 2006/0123326 A1 — Smith ("Pre-decode error handling via branch correction")

• Full citation: US 2006/0123326 A1, Smith, Rodney W., "Pre-decode error handling via branch correction."
• Dates: Filed Nov. 22, 2004; published June 8, 2006.
• Description: Error handling at the pre-decode stage, using branch correction to recover from a corrupted instruction fetch.
• Claims potentially anticipated under §102: Claim 1 / 21 (error handling during instruction fetch/decode).
• ⚠️ Prior-art-date flag: As listed, its filing date (Nov. 22, 2004) is after the '619 priority/filing date (July 6, 2004). On its face, therefore, it does not qualify as §102 prior art against '619 unless it claims the benefit of an earlier provisional/application. This makes it the one citation in the list whose status as prior art is questionable regardless of its technical content. It should not be counted as an anticipating reference without confirming an earlier effective date.

Additional highly relevant prior art (added during the IPR, not in the examiner's list)

These were not among the examiner's "Patent Citations (9)," but they were used in IPR2021-01042 and are directly relevant:

• US 7,395,489 (Itou) — memory-control circuit with a tag RAM (part of a cache) coupled to a CPU; ECC check unit detects a bit error on read and an error-correction unit corrects and writes the corrected data back to the tag RAM, with a "cancel signal" that stalls/re-reads. Per the IPR Ground 1, Itou supplies the cache write-back and stall limitations (claims 6, 8, 9, 24, 25). I could not confirm Itou's filing date from the material returned — flag as unverified.
• US 7,290,179 (Lempel) — "System and Method for Soft Error Handling"; filed Dec. 1, 2003, granted Oct. 30, 2007. Cache coupled to a processor with soft-error detection logic; on detection the fetch is stopped, the processor front-end is stalled, the cache portion is cleared, and a cache miss is triggered to refill from memory. Used in the IPR as an alternative to Haswell for the preamble/fetch-and-detect limitations and for the "replace from RAM" concept (claims 1, 11, 27).

Bottom line on the §102 picture

• The most relevant single §102 reference is Haswell (US 2004/0268202A1 = US 7,278,083), which the IPR asserted anticipates independent claims 1, 21, and 29 plus claims 10, 11, 13, 22, 24, 26, 30, 31 on the concurrent fetch-and-detect and correct/write-back features.
• The examiner's primary §102(b) reference was Ohashi (US 5,063,565), which was used to reject all of claims 1–32 and was defeated only on the "concurrently with fetching" limitation.
• Tandem (US 4,823,252) is the strongest older reference for the write-back-over-the-erroneous-instruction limitations (claims 6, 8, 17, 19, 24).
• US2006/0123326 (Smith) carries a prior-art-date defect (filed after the '619 priority) and should be excluded unless an earlier effective date is confirmed.
• Caveat carried forward from the prior section: I still cannot authoritatively confirm from the returned material which, if any, claims of '619 were cancelled by the IPR2021‑01042 Final Written Decision (Dec. 13, 2022) and the ensuing K1 certificate (Apr. 5, 2023). If that IPR ground succeeded on Haswell, independent claims 1/21/29 would be affected — so the practical significance of the references above depends on that outcome, which should be verified against the actual PTAB FWD paper and the certificate text rather than inferred.

Sources: Google Patents full text for US7302619B1, US4823252A, US5063565A, US6457119B1, US6543028B1; the Microchip IPR2021‑01042 petition and the Sechen declaration (ptacts.uspto.gov, petition 1547546); Unified Patents record for US‑7302619‑B1 (fetched 2026‑09‑30). Details for US6640313B1, US6802039B1, US2005/0108509A1 and US2006/0123326A1 were not fully retrievable in this pass and are flagged accordingly.

I'll ground this analysis by pulling the operative PTAB outcome and details on the key cited references before assembling the §103 combinations.

The first result is HDSS's Patent Owner Preliminary Response (not the final decision). Let me pin down the actual Final Written Decision outcome and the certificate's effect on the claims.

Obviousness analysis — U.S. Patent No. 7,302,619 ("Error correction in a cache memory") under 35 U.S.C. § 103

Note on scope and grounding: This analysis uses the references listed in the Prior Art section of the Google Patents page for US 7,302,619 — the nine examiner-cited references ("Patent Citations (9)") and the references the parties actually litigated in IPR2021-01042 (Haswell, Itou, Lempel). Incidentally, the primary IPR reference (Haswell, US 2004/0268202 A1) is one of the nine examiner-cited references, which matters to the story below. I flag at the end where I hit evidentiary limits.

Minor inconsistency to flag: the task header says "Current Date: April 26, 2026," while the fetched patent page is timestamped 2026-09-30. I have not auto-reconciled these; nothing in the analysis turns on the difference.

1. Governing legal framework and the level of ordinary skill

Because the '619 patent has a priority date of July 6, 2004, pre-AIA § 103(a) governs. The obviousness inquiry is the Graham v. John Deere four-factor test: (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; (4) objective evidence of non-obviousness. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), governs the combination analysis.

A POSITA here would be a person with a B.S. in electrical engineering or computer engineering (or equivalent) and roughly 2–4 years of experience in processor and cache/memory-array design, including ECC/parity protection of SRAM structures. The '619 patent itself confirms the art is well-trodden: it concedes that Hamming codes "or other codes" and SEC/DED-style single-bit correction are "known algorithms" (spec., discussion of error correction code generators 133/136), and that cache-miss refetch from main memory is a conventional cache operation.

Critical structural point: the independent claims are narrow. Claim 1 requires only (a) fetching cached instructions one per instruction cycle and (b) running error detection on each instruction concurrently with its fetch. Claim 21 is the system counterpart with "circuitry"; claim 29 is the § 112 ¶ 6 "means for detecting" counterpart. All the commercially interesting behavior (correction, write-back, stall, uncorrectable refetch, "mimic a cache miss") lives in dependent claims.

2. The prior-art references and what they disclose

3. The single most important fact: the prosecution history already disposed of everything but concurrency

Per the IPR record, the examiner rejected claims 1–32 under § 102(b) as anticipated by US 5,063,565 (Ohashi), and the applicant overcame the rejection only by arguing that "the error detection and fetching of instructions did not occur concurrently" — Ohashi "conducted error detection serially before the fetching occurs," and did so "by a parity check." (PTAB filings, IPR2021-01042.)

That is a devastating concession for obviousness purposes. It fixes the single difference between the claims and the art at the time of filing as concurrency of error detection with instruction fetch (plus the correction/write-back/refetch/ stall mechanics, which are separately known). So the § 103 question collapses to: as of July 2004, would a POSITA have found it obvious to make Ohashi's (or an equivalent) SEC/DED instruction-store check run concurrently with the fetch? The answer is plainly yes, because two references in the same cited-art set teach precisely that.

4. Proposed obviousness combinations

Ground 1 — Haswell (US 2004/0268202 A1 / US 7,278,083) alone, or in view of US 6,543,028 → claims 1, 13–20, 21, 29

What Haswell discloses. Haswell is directed to exactly the '619 problem (soft-error bit-flipping of instructions in a fast on-chip instruction memory) and solves it with ECC on the instruction-side memory. It expressly teaches:

• checking the instruction "simultaneously with the commencement of transmission" to the processor; and
• that transmitting the instruction, checking it, and substituting a reserved instruction are "all performed within a single clock cycle."

That maps directly onto claim 1 ("performing error detection … concurrently with the fetching") and onto claims 13–20, which recite error detection performed during the same instruction cycle as the fetch. Haswell also teaches a corrected data register and replacing the corrupted instruction in the data memory with the corrected data signal — i.e., generating a corrected instruction (claims 14–15) and writing it back over the stored instruction (claims 17, 19).

The gap and the cure. The one limitation the patent owner has emphasized is "instruction cache" (Haswell's disclosure speaks in terms of an on-chip instruction memory / SRAM). That gap is filled by US 6,543,028, which recites in terms: "a cache memory coupled to said buffer to receive the entry along with its error detection bit" and "an error detection circuit coupled to said buffer to test the entry and compare a result of its test to the error detection bit to identify if the entry is corrupted when the entry is coupled out of said buffer." That is structurally the very architecture of the '619's FIG. 1 (ECC generator 133 → comparator 139, fed by the cache storage).

Motivation to combine. Both references attack the identical problem (soft/alpha-particle errors corrupting instructions in fast on-chip memory) and both belong to the same field (processor instruction supply). A POSITA seeking to protect instructions in a cache would naturally apply the ECC-on-instruction-memory checking of Haswell to the cache-based structure of US 6,543,028, and vice versa; the combination is the application of known techniques to a known structure with a predictable result (KSR; Textile Productions rationale). There is a reasonable expectation of success because both render the detection combinable with the fetch in a single/overlapped cycle.

Ground 2 — Ground 1 further in view of US 6,802,039 (and/or US 6,543,028's own replay) → claims 3–9, 10–12, 22–25, 26–28, 30–32

Correction and write-back (claims 3, 6, 8, 14, 17, 19, 22, 24, 30, 31). Haswell already teaches generating corrected data and replacing the corrupt instruction in memory. US 6,802,039 independently confirms that ECC correction and write-back to a cache's data/tag arrays is a conventional, hardware-or-firmware-implemented technique. Writing the corrected instruction over the corrupted entry (claims 8, 19) is the ordinary way a write-back cache stores corrected data — indeed the '619 specification itself sells the write-back over static RAM as the mechanism that avoids re-correcting the same error on every subsequent read, an efficiency the specification treats as self-evident rather than surprising.

Uncorrectable error → refetch from RAM (claims 10, 11, 26, 27). On a multi-bit (uncorrectable) error, the standard recourse is refetch from main memory. That is taught by US 6,457,119 (signal the corruption; replay/flush the corrupt instruction) and by US 6,543,028 (front-end replay "refetches the instruction when errors are detected early on"). A POSITA would combine these because refusing to execute a corrupted instruction and reloading it is the established safe response.

"Mimic a cache-miss condition" (claims 12, 28). This is the narrowest limitation. Using the cache controller's existing miss/refill path to fetch a clean copy from main memory is a straightforward design choice — it reuses the tag/refill hardware already present in any cache (as US 6,543,028's cache-coupled architecture and US 6,802,039's cache-ECC hardware both presuppose). The US 2006/0123326 pre-decode/branch-correction reference and the MUX-based address/reload path shown in the '619's own FIG. 1 illustrate that routing a "reload" through the cache controller is within the ordinary skill. This limitation is therefore the most vulnerable to a § 112 written-description/indefiniteness challenge and the most dependent on combining the cache-controller art, so I would not rest a validity challenge on it alone.

Stalling the processor during generation/write-back (claims 5, 9, 16, 20, 23, 25, 32). Stalling is the known alternative the art itself discusses: Haswell's own background describes the prior art in which "a parity error signal pauses the processor clock when asserted. During this pause, ECC correction is done on correctable data, and the processor clock is restarted when corrected data is available" (citing US 4,646,312). A POSITA asked to allow time for correction, and unable to make corrected data available in the same cycle, would predictably stall the pipeline — the '619 specification does not attribute any unexpected benefit to stalling; it treats it as the necessary cost.

Ground 3 — Ground 1 in view of Itou (US 7,395,489) → the "subsequent-cycle" dependent claims 2, 4, 7, 15, 18

The '619's claims 2–9 recite detection in a later cycle than the fetch, with generation in a third cycle and write-back in a fourth. Itou teaches correction occurring in a later cycle (cycle 4) following a cancel signal. Caveat: the patent owner correctly argued in IPR2021-01042 that Itou (i) detects errors in "tags" of a specialized memory rather than an instruction cache, and (ii) corrects in cycle 4, which does not line up precisely with the "second"/"third"/"fourth" cycle recitations. Whether that mismatch defeats a § 103 combination depends on how strictly the Board reads the cycle arithmetic. I would treat Ground 3 as the weakest of the three grounds and would not hazard a confident statement that claims 2, 4, 7, 15, and 18 are obvious over Haswell + Itou; the record shows the patent owner built a serious non-obviousness argument precisely here.

Ground 4 — Ohashi (US 5,063,565) + Haswell (and/or US 6,543,028) → claims 1–12, 21, 29

This is the cleanest KSR-style narrative. The examiner already found all elements of claims 1–32 in Ohashi and the applicant distinguished only on concurrency. Haswell supplies concurrency ("simultaneously with the commencement of transmission … within a single clock cycle"), and US 6,543,028 supplies the cache-based concurrent detection and replay architecture. Motivation: one of ordinary skill reading Ohashi's serial-before-fetch parity check and Haswell's concurrent single-cycle check would recognize that moving the check into the fetch path removes the "delays due to lack of concurrence" that the applicant himself called "unacceptable." Improving throughput by overlapping a known checking operation with a known fetch is a predictable, results-driven design choice, not an inventive leap.

5. Why the combinations are supported by articulated rationales (KSR)

1. Same field of endeavor / same problem. All principal references address soft-error-induced instruction corruption in fast on-chip instruction storage. Combination is among analogous arts.
2. Predictable use of known elements per their established functions. ECC generation + recompute/compare (US 6,543,028), concurrent check (Haswell), cache ECC correction/write-back (US 6,802,039), and replay/refetch (US 6,457,119) — each is used for exactly the function it already performs.
3. Design choice / obvious-to-try in a finite design space. Where in the fetch pipeline to locate the check and whether to check in the same or the next cycle is a predictable pipeline-timing tradeoff (the '619 specification frames it as exactly that tradeoff between FIGS. 2A/2B and FIGS. 3A/3B).
4. Teaching away cuts the other way for Ground 1/2. The one reference that arguably teaches away from ECC is Lempel (it calls ECC "expensive" and cannot correct). But Lempel is not needed for the core grounds; on the contrary, Lempel's anti-ECC stance strengthens the Haswell + 6543028/6802039/Ohashi combinations, which are all ECC-based and consistent with one another.
5. No credible secondary considerations. The '619's asserted advantages (fewer stall cycles; correcting the cache entry once rather than on every read via write-back) are the expected consequences of combining write-back ECC with an overlapping fetch — the specification presents them as advantages of the design, not as unforeseen results. No unexpected-results, long-felt-need, failure-of-others, or licensing evidence is apparent from the record. The error-correction log discussed in the specification is not claimed, so it cannot supply non-obviousness for the claims.

6. Bottom line by claim group

• Claims 1, 13–20, 21, 29 (concurrent detection, incl. same-cycle): strong § 103 case over Haswell + US 6,543,028, and arguably Haswell alone if "instruction memory" is read as an instruction cache; also strong over Ohashi + Haswell.
• Claims 3–9, 14–20, 22–25, 30–32 (correction, write-back, stall): strong § 103 case over Ground 1 + US 6,802,039 (and Haswell itself, which teaches correction, a corrected-data register, and replacement of the corrupt instruction in memory) with stalling supplied by the admitted/suggested prior art.
• Claims 10–12, 26–28 (uncorrectable → refetch; mimic cache miss): moderate case over Ground 1 + US 6,457,119 / US 6,543,028; the "mimic a cache miss" limitation is the narrowest link and the most dependent on the cache-controller art.
• Claims 2, 4, 7, 15, 18 (specific later-cycle timing): the weakest; the Itou mapping is imperfect and the patent owner's IPR arguments against it were substantive.

7. IPR overlay and explicit uncertainty flags

What I can confirm. Microchip petitioned for IPR of all 32 claims (IPR2021-00872 and IPR2021-01042). IPR2021-01042 was instituted Dec. 15, 2021 — meaning the Board was not persuaded by HDSS's denial arguments that Haswell lacks an "instruction cache" and lacks correction — and reached a Final Written Decision on Dec. 13, 2022, with an inter partes review certificate (K1) issued April 5, 2023. A separate IPR (2021-00872) was not instituted on the merits.

What I could NOT confirm (and am flagging rather than guessing). I could not retrieve the operative text of the Dec. 13, 2022 Final Written Decision or the K1 certificate, so I cannot state which (if any) claims were held unpatentable and cancelled. My searches surfaced HDSS's preliminary-response arguments (Haswell allegedly lacks an instruction cache and teaches only detection, not correction; Itou corrects in cycle 4 and detects tags, not cached instructions; Lempel teaches away from ECC) — but those are advocacy positions, not the Board's holding. The aggregator's "Claims Invalidated" field is blank. This is the single most important open question about the patent's actual validity, and it remains unresolved from the sources available to me. It does not change the analytical § 103 conclusion above (which is my independent assessment), but it is the fact most likely to be dispositive in a real dispute.

Consistency with the prior sections. My findings are consistent with the earlier-generated summary. Two data points refine it: (i) the FWD date is Dec. 13, 2022 (termination date), matching the "Final Written Decision" case status; and (ii) the record confirms the prosecution-based framing above (Ohashi anticipation rejection overcome on concurrency), which the earlier section did not include and which materially strengthens the § 103 analysis. I found no contradiction between the previously generated material and the search results — only additional detail, plus the same unresolved claims-cancellation gap.

Sources: Google Patents, US 7,302,619 (patents.google.com/patent/US7302619B1/en, fetched 2026-09-30); PTAB filings in IPR2021-01042 (ptacts.uspto.gov, petitions 1547546/1547341/1548616); US 6,543,028 B1 (patents.google.com/patent/US6543028); US 6,457,119 B1 (patents.google.com/patent/US6457119B1/en); US 2004/0268202 A1 / US 7,603,609 B2 (Haswell) (patents.google.com/patent/US20040268202); IP Verse PTAB case page for IPR2021-01042 (ipverse.greyb.com/ptab-web/cases/case-details/IPR2021-01042); HD Silicon Solutions v. Microchip, No. 6:20-cv-01092 (W.D. Tex.). The Vorys/Lexology/Mondaq Federal Circuit coverage concerns the '033 patent (23-1397) and is unrelated to the '619 patent.