Prior art — US Patent 7069287

Analysis of Prior Art for U.S. Patent 7,069,287

The core innovation protected by U.S. Patent 7,069,287, particularly in independent claims 1 and 11, is a method and system for finite field multiplication that improves efficiency on resource-constrained microcontrollers. This is achieved by first computing and summing multiple intermediate products without performing a modular reduction after each step, and only then performing a single modular reduction on the accumulated sum. This "add-first, reduce-later" approach is contrasted with the conventional method of performing a reduction after each multiplication.

The following is an analysis of the prior art cited on the face of patent 7,069,287, evaluating each reference's potential to anticipate the claims under 35 U.S.C. § 102.

U.S. Patent 6,049,815 A: Method and apparatus for finite field multiplication

Full Citation: U.S. Patent 6,049,815 A, "Method and apparatus for finite field multiplication," assigned to Certicom Corp.
Publication/Filing Date: Published April 11, 2000. Filed December 30, 1996.
Brief Description: This patent describes a method for multiplying two elements in a Galois Field GF(2^m). It details a process where partial products are generated and then combined. The method focuses on efficient implementation in hardware, particularly for binary fields (characteristic two), which are common in cryptography.
Anticipation Analysis: This reference is relevant as it addresses finite field multiplication for cryptography. However, it focuses on binary fields (GF(2^m)) rather than the "odd characteristic extension fields" (GF(p^m) where p>2) that are a key focus of patent 7,069,287. More importantly, the method described in US 6,049,815 appears to follow a more conventional approach where reduction is interleaved with the multiplication and addition steps, rather than being delayed until after a full sum of unreduced products is accumulated. Therefore, it does not appear to teach the core "add-first, reduce-later" element of claims 1 and 11.

U.S. Patent 6,230,179 B1: Finite field multiplier with intrinsic modular reduction

Full Citation: U.S. Patent 6,230,179 B1, "Finite field multiplier with intrinsic modular reduction," assigned to Motorola, Inc.
Publication/Filing Date: Published May 8, 2001. Filed April 18, 1997.
Brief Description: This patent discloses a hardware multiplier for finite fields GF(2^k) that performs modular reduction as an integrated, or "intrinsic," part of the multiplication process. The architecture is designed to compute the product and reduce it modulo an irreducible polynomial concurrently, aiming to increase speed and reduce hardware complexity.
Anticipation Analysis: The concept of an "intrinsic modular reduction" taught in this patent is fundamentally different from the method in patent 7,069,287. Where 7,069,287 delays the reduction, US 6,230,179 integrates it directly into the multiplication logic. This reference teaches away from the claimed invention by combining, rather than separating and delaying, the reduction step. It does not disclose computing a sum of intermediate products without an immediate modular reduction. Thus, it does not anticipate claims 1 or 11.

U.S. Patent 5,999,959 A: Galois field multiplier

Full Citation: U.S. Patent 5,999,959 A, "Galois field multiplier," assigned to Quantum Corporation.
Publication/Filing Date: Published December 7, 1999. Filed February 18, 1998.
Brief Description: This patent describes a multiplier for use in a Galois field, primarily for applications like error correction codes. The disclosure details a specific hardware architecture for performing the multiplication, often using lookup tables and XOR operations, which are characteristic of binary field (GF(2^n)) arithmetic.
Anticipation Analysis: Similar to the other hardware-focused references, this patent does not describe the specific method of accumulating a sum of unreduced products before performing a single modular reduction. Its focus is on an efficient hardware layout for a conventional multiplication-and-reduction sequence in binary fields. It does not disclose the key process steps outlined in claim 1 or the system architecture of claim 11 of patent 7,069,287.

U.S. Patent 6,377,969 B1: Method for multiplication in Galois fields using programmable circuits

Full Citation: U.S. Patent 6,377,969 B1, "Method for multiplication in Galois fields using programmable circuits," assigned to General Dynamics Government Systems Corporation.
Publication/Filing Date: Published April 23, 2002. Filed April 23, 1999.
Brief Description: This patent discloses implementing Galois field multipliers on programmable logic devices like FPGAs. The method involves pre-calculating and storing certain values to speed up the multiplication process. It breaks down the multiplication into a series of smaller, more manageable operations suitable for programmable hardware.
Anticipation Analysis: The focus of this patent is on implementation within a specific type of hardware (programmable circuits) and optimizing the flow for that environment. The detailed description does not appear to teach the specific software or hardware method of accumulating a multi-word integer sum of products and only then performing a delayed modular reduction, which is the central inventive concept of US 7,069,287. Therefore, it is unlikely to anticipate the claims.