US 7069287

Analysis of U.S. Patent 7,069,287

Washington, D.C. - A detailed analysis of United States Patent 7,069,287 reveals a method for improving the efficiency of cryptographic computations on microprocessors with limited capabilities, particularly those found in devices like smart cards. The patent, issued on June 27, 2006, addresses the computational bottleneck often encountered in finite field arithmetic, a cornerstone of modern public-key cryptography.

The patent is officially titled "Method for efficient computation of odd characteristic extension fields." It was assigned to the Worcester Polytechnic Institute. The inventors listed are Christof Paar, Adam D. Woodbury, and Daniel V. Bailey. The application for this patent was filed on September 19, 2001.

According to the patent's abstract, the invention provides a method for implementing elliptic curve or discrete logarithm cryptosystems on inexpensive microprocessors. It highlights a Galois Field (GF) implementation based on the finite field GF((2⁸ −17)¹⁷) for an Intel 8051 microcontroller, a common processor in smart cards. The core of the method is to accelerate finite field multiplication by minimizing the number of computationally expensive subfield modular reductions. This is achieved by structuring calculations in a way that is more efficient for low-end 8-bit and 16-bit processors.

A search of the United States Court of Appeals for the Federal Circuit (CAFC) dockets for the year 2026 did not reveal any cases specifically citing US Patent 7,069,287.

Overview of Independent Claims:

The patent includes two independent claims, which form the foundation of the protected invention.

Independent Claim 1 describes a method for performing finite field multiplication on a microcontroller. In simple terms, this claim outlines a process where, instead of performing a modular reduction after each multiplication of coefficients (the standard, but slow, method), the system first adds together multiple unreduced intermediate products. Only after these additions are complete is a single, more complex modular reduction performed on the sum. This approach is advantageous on microprocessors where adding large numbers is significantly faster than performing modular reductions. The claim specifies the steps of providing the microcontroller with its necessary components (CPU, memory, etc.), representing the field elements as arrays of coefficients, and then executing this "add-first, reduce-later" multiplication process.

Independent Claim 11 outlines a system that accomplishes the method described in the first claim. This claim focuses on the components of the system rather than the steps of the method. It details a microcontroller configured with memory locations to store the field elements and the intermediate and final results. The claim specifies the roles of the multiplier and addition modules in computing the temporary coefficients without immediate modular reduction. It also describes an arithmetic module for performing the single modular reduction on these accumulated temporary coefficients. Essentially, this claim protects the physical or logical arrangement of a device designed to carry out the novel multiplication method.