Obviousness

Obviousness Analysis of U.S. Patent 7,069,287 under 35 U.S.C. § 103

An analysis of U.S. Patent 7,069,287 under 35 U.S.C. § 103 suggests that the invention claimed, particularly the "add-first, reduce-later" method of finite field multiplication, would likely have been considered non-obvious to a person having ordinary skill in the art at the time of the invention. While the cited prior art addresses the general problem of efficient finite field multiplication, none of the references, either individually or in combination, appear to suggest the specific approach that is central to this patent.

The legal framework for obviousness, established in Graham v. John Deere Co., requires a factual inquiry into the scope of the prior art, the differences between the art and the claims, and the level of ordinary skill. The Supreme Court's later decision in KSR Int'l Co. v. Teleflex Inc. added flexibility, allowing for a "common sense" approach and recognizing that a motivation to combine prior art can arise from various sources, including market pressures and the nature of the problem itself.

1. Defining the Person Having Ordinary Skill in the Art (PHOSITA)

For this patent, a PHOSITA would be a computer scientist or electrical engineer with a graduate-level understanding of applied cryptography, particularly elliptic curve and discrete logarithm systems. This individual would have practical experience in implementing cryptographic algorithms on resource-constrained hardware, such as 8-bit or 16-bit microcontrollers found in smart cards. They would be well-versed in the trade-offs between different computational methods and hardware architectures, especially the relative costs of multiplication, addition, and modular reduction operations on such platforms. For software and computer-implemented inventions, a PHOSITA is often considered a programmer with experience in the relevant environment.

2. Scope and Content of the Prior Art

The prior art cited on the face of the patent (US 6,049,815 A, US 6,230,179 B1, US 5,999,959 A, and US 6,377,969 B1) predominantly focuses on hardware implementations of Galois field multipliers, particularly for binary fields (GF(2^m)).

• US 6,049,815 and US 5,999,959 describe hardware architectures for efficient multiplication in binary fields, a common choice for hardware-based cryptography.
• US 6,230,179 discloses a multiplier where modular reduction is tightly integrated, or "intrinsic," to the multiplication hardware, aiming to perform both tasks concurrently.
• US 6,377,969 discusses implementing multipliers on programmable logic devices (FPGAs), breaking down operations for that specific hardware.

Crucially, all these references address the problem of speeding up finite field multiplication. However, their solutions are architectural and specific to certain hardware or field types (primarily binary fields).

3. Differences Between the Prior Art and the Claims

The key difference lies in the fundamental strategy for handling modular reduction. The invention in 7,069,287 teaches a method specifically advantageous for microcontrollers where multi-precision addition is computationally cheaper than modular reduction. The patent claims a process of:

1. Computing multiple intermediate products (a_i * b_j).
2. Accumulating these products into a multi-word sum (c_k').
3. Crucially, performing these steps without an immediate modular reduction.
4. Performing a single modular reduction on the final accumulated sum (c_k') to get the result (c_k).

The cited prior art does not teach this delay and accumulation strategy. In fact, US 6,230,179 teaches the opposite: integrating the reduction into the multiplication process to make it "intrinsic." The other references describe conventional multiplication schemes where reduction is typically performed in an interleaved manner. Furthermore, the 7,069,287 patent specifically targets "odd characteristic extension fields" (GF(p^m) where p>2), whereas much of the cited art is optimized for binary fields.

4. Motivation to Combine and Analysis

For an invention to be obvious, there must have been a reason for a PHOSITA to combine elements from the prior art to arrive at the claimed invention. A potential obviousness argument might be constructed as follows:

• Argument for Obviousness (Hypothetical): A PHOSITA knew from general computer science principles that different operations have different costs on different processors. It was well-known that modular arithmetic, especially with large numbers, is expensive. The prior art (e.g., US 6,049,815) taught methods for polynomial multiplication by computing sums of products of coefficients. Therefore, a PHOSITA, faced with implementing this on a slow microcontroller, would have been motivated to rearrange the standard algorithm to minimize the most expensive step—the modular reduction. They would have naturally considered grouping all the cheaper addition operations together before performing the costly reduction once at the end.

• Rebuttal and Strength of the 7,069,287 Invention: This argument relies heavily on hindsight. The prior art, particularly US 6,230,179, points in the opposite direction by suggesting a tighter integration of multiplication and reduction. This reference "teaches away" from the claimed invention by suggesting a different path to efficiency. While optimizing for a specific platform is a common goal, the specific solution of accumulating a large, multi-word unreduced sum and then developing an efficient algorithm to reduce that large sum is not a trivial or predictable variation.

The inventors of 7,069,287 not only identified the potential benefit of delaying the reduction but also developed the necessary algorithms to efficiently reduce the resulting multi-word integer (as described in the "Example Algorithms" section of the patent text). This goes beyond simply rearranging known steps; it involves solving the new problem that arises from that rearrangement—namely, how to efficiently perform a modular reduction on a number much larger than the typical double-precision product. The prior art does not suggest this specific path or provide the tools to solve the resulting problem.

Conclusion

Based on the provided prior art, a strong argument can be made that the invention of US patent 7,069,287 would have been non-obvious to a person of ordinary skill in the art. The prior art focused on hardware-centric solutions for binary fields and, in one case, taught a method of integrating—not separating and delaying—the modular reduction step. The inventive concept of accumulating unreduced intermediate products to form a large integer and then performing a single, specialized reduction is a distinct and non-trivial departure from the methods disclosed in the cited references. There is no clear motivation in the cited art to combine existing elements to produce the specific "add-first, reduce-later" methodology claimed in the patent.