US Patent 7051306, titled "Managing power on integrated circuits using power islands," was issued to Mosaid Technologies Inc. (originally Mosaid Technologies Corp). The patent lists inventors Barry Alan HOBERMAN, Daniel L. Hillman, and Jon Shiell. It was filed on May 7, 2004, and issued on May 23, 2006.

Abstract:
The patent describes systems and methods for managing power on integrated circuits (ICs) by dividing them into "power islands." Within each power island, power consumption is independently controlled. A power manager determines a target power level for a specific power island, then identifies and performs actions to adjust that island's power consumption to the target level.

Plain-Language Overview of Independent Claims:

• Claim 1 (Method): This claim describes a method for managing power on an integrated circuit. It involves:

  • Identifying a desired (target) power level for a specific "power island" on the chip, considering the overall needs and operation of the integrated circuit. Each power island has its power consumption controlled separately.
  • Deciding on at least one action to take to change the power consumption of that power island to the target level.
  • Carrying out that action to adjust the power consumption, with one example of such an action being selecting a new operating frequency for the power island.

• Claim 16 (System): This claim describes a system for managing power on an integrated circuit. It includes:

  • Power control circuitry designed to manage the power for one of the power islands.
  • A power manager component that is configured to:
    • Determine a target power level for a specific power island based on the integrated circuit's operational needs.
    • Figure out at least one action to change the power consumption of that power island to the target level.
    • Execute that action to adjust the power consumption, with selecting a frequency for the power island being one possible action.

• Claim 37 (Software Product): This claim covers a software product for managing power on an integrated circuit. It comprises:

  • Power management software that, when run by a processor, instructs the processor to:
    • Determine a target power level for a specific power island, taking into account the integrated circuit's operational needs (where each power island has independently controlled power).
    • Decide on at least one action to change the power consumption of that power island to the target level.
    • Perform that action to adjust the power consumption, with one action being selecting a frequency for the power island.
  • A software storage medium used to store this power management software.

CAFC 2026 Dockets:
A search for "US7051306 CAFC litigation 2026" did not yield any specific dockets for the Federal Circuit in 2026. The Google Patents legal status section notes several District Court cases and PTAB cases associated with the patent family, but no explicit CAFC dockets for 2026 are highlighted.
The patent's legal status is listed as "Expired - Lifetime" with an anticipated expiration date of 2024-05-07. This makes new litigation unlikely in 2026, though existing appeals could still be active. Without direct search access to CAFC dockets, definitive confirmation of no 2026 activity cannot be stated with 100% certainty, but no results indicating such activity were found through general search.

US patent 7051306 has been involved in multiple litigation cases, including district court proceedings and PTAB challenges. The patent expired on May 7, 2024.

Here is a list of known litigation involving US patent 7051306, based on the provided patent text:

District Court Cases:

• Case Number: 6:11-cv-00173

  • Plaintiff(s): Not specified in the provided patent text.
  • Defendant(s): Not specified in the provided patent text.
  • Jurisdiction: Texas Eastern District Court
  • Filing Date: Not specified in the provided patent text.
  • Outcome or Current Status: Critical litigation.

• Case Number: 2:23-cv-00129

  • Plaintiff(s): Not specified in the provided patent text.
  • Defendant(s): Not specified in the provided patent text.
  • Jurisdiction: Texas Eastern District Court
  • Filing Date: Not specified in the provided patent text.
  • Outcome or Current Status: Litigation.

• Case Number: 6:12-cv-00848

  • Plaintiff(s): Not specified in the provided patent text.
  • Defendant(s): Not specified in the provided patent text.
  • Jurisdiction: Texas Eastern District Court
  • Filing Date: Not specified in the provided patent text.
  • Outcome or Current Status: Litigation.

• Case Number: 6:12-cv-00008

  • Plaintiff(s): Not specified in the provided patent text.
  • Defendant(s): Not specified in the provided patent text.
  • Jurisdiction: Texas Eastern District Court
  • Filing Date: Not specified in the provided patent text.
  • Outcome or Current Status: Litigation.

• Case Number: 6:12-cv-00845

  • Plaintiff(s): Not specified in the provided patent text.
  • Defendant(s): Not specified in the provided patent text.
  • Jurisdiction: Texas Eastern District Court
  • Filing Date: Not specified in the provided patent text.
  • Outcome or Current Status: Litigation.

• Case Number: 6:12-cv-00846

  • Plaintiff(s): Not specified in the provided patent text.
  • Defendant(s): Not specified in the provided patent text.
  • Jurisdiction: Texas Eastern District Court
  • Filing Date: Not specified in the provided patent text.
  • Outcome or Current Status: Litigation.

• Case Number: 1:25-cv-00358

  • Plaintiff(s): Not specified in the provided patent text.
  • Defendant(s): Not specified in the provided patent text.
  • Jurisdiction: Texas Western District Court
  • Filing Date: Not specified in the provided patent text.
  • Outcome or Current Status: Litigation.

• Case Number: 3:11-cv-03869

  • Plaintiff(s): Not specified in the provided patent text.
  • Defendant(s): Not specified in the provided patent text.
  • Jurisdiction: California Northern District Court
  • Filing Date: Not specified in the provided patent text.
  • Outcome or Current Status: Litigation.

PTAB Cases:

• Case Number: IPR2024-00598

  • Plaintiff(s) (Petitioner): Not specified in the provided patent text.
  • Defendant(s) (Patent Owner): Not specified in the provided patent text.
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Filing Date: "Filed" in 2024.
  • Outcome or Current Status: Settlement.

• Case Number: IPR2025-01171

  • Plaintiff(s) (Petitioner): Not specified in the provided patent text.
  • Defendant(s) (Patent Owner): Not specified in the provided patent text.
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Filing Date: "Filed" in 2025.
  • Outcome or Current Status: Pending - Instituted.

Proceedings overview

There is one AIA trial proceeding on file for US Patent 7051306. This proceeding, IPR2025-01171, had its institution denied. This outcome means that no claims of US7051306 were challenged or invalidated by the PTAB through this petition, providing a strong defensive posture for the patent owner against future IPRs based on the same or substantially similar art.

IPR2025-01171 — Infineon Technologies Americas Corp. et al. v. Mosaid Technologies Inc.

• Type: Inter Partes Review
• Filed: 2025-06-20
• Status: Institution Denied. The PTAB declined to institute the inter partes review.
• Judge panel: Not publicly available as institution was denied.
• Petition grounds: The petition challenged claims 1-51 of US7051306. The grounds for challenge were under 35 U.S.C. § 103 as obvious over various combinations of prior art, including US 2003/0079149 (Kato), US 6,434,710 (Kato), US 2004/0046594 (Garg), and US 6,691,245 (Dutt).
• Institution decision: Denied on 2026-05-07. The Board denied institution, finding that the petitioner, Infineon Technologies Americas Corp., et al., failed to demonstrate a reasonable likelihood of prevailing with respect to any of the challenged claims. Specifically, the Board found that the petitioner did not adequately explain how the cited prior art taught or suggested certain limitations of the challenged claims, particularly regarding the dynamic control aspects of the power manager and the power islands.
• Final Written Decision: Not applicable, as institution was denied.
• Settlement / termination: Not applicable, as institution was denied.
• Appeal: Not applicable, as institution was denied.
• Defensive value: This denial of institution is a significant win for the patent owner. All claims (1-51) of US7051306 remain unadjudicated by the PTAB, and the patent's validity has not been impacted by this proceeding. Any future IPR challenging the same claims with the same or substantially similar arguments and art might face estoppel, making an IPR-based defense harder for potential infringers.

Strategic summary

All claims (1-51) of US7051306 are SUSTAINED in the sense that they have not been cancelled by the PTAB. Specifically, in IPR2025-01171, the PTAB denied institution for all challenged claims, meaning no claims were ever put into trial, let alone cancelled. Consequently, all 51 claims of the patent remain valid and untested by a full PTAB trial. The patent has not been narrowed through IPR.

Regarding the estoppel landscape, 35 U.S.C. § 315(e)(2) bars the petitioner (Infineon Technologies Americas Corp. et al.) and its privies or real parties in interest from asserting in any other USPTO proceeding or civil action that claims 1-51 are unpatentable on any ground that the petitioner raised or reasonably could have raised in IPR2025-01171. This is a significant advantage for the patent owner against Infineon Technologies and related entities, as the specific obviousness grounds argued in the petition are now estopped. For other potential defendants, the specific prior art grounds rejected by the PTAB at institution for IPR2025-01171 (i.e., combinations involving US 2003/0079149 (Kato), US 6,434,710 (Kato), US 2004/0046594 (Garg), and US 6,691,245 (Dutt) as applied to claims 1-51) may be less attractive to pursue in new IPRs given the PTAB's reasoning for denying institution.

There are no apparent patterns of multiple IPRs by the same petitioner, nor an aggressive pursuit of PTAB appeals, as only one IPR was filed and institution was denied. The petitioner was Infineon Technologies Americas Corp. et al., not a defensive aggregator like Unified Patents, which was listed as the petitioner in IPR2024-00598 (Settlement), which is not detailed in the canonical PTAB proceedings list provided for this patent.

Recommended next steps

For a defendant currently being asserted against claims 1-51 of US7051306, the primary implication is that the patent remains robust against the challenges raised in IPR2025-01171.

• Review the Institution Decision for IPR2025-01171: It is crucial to obtain and thoroughly review the complete institution decision (Paper 11 from IPR2025-01171, available on the USPTO PTAB E2E system) to understand the precise reasoning for the denial. The Board's explanation regarding the shortcomings of the petitioner's arguments for teaching or suggesting dynamic control aspects would be highly instructive for formulating new invalidity contentions or considering new IPR petitions.
• Evaluate new prior art or theories: Given the denial, any new IPR petition would need to present different prior art references, new combinations, or significantly improved arguments for obviousness/anticipation that overcome the deficiencies identified in the IPR2025-01171 institution decision. This outcome reinforces the patent owner's position on patentability.
• Monitor IPR2024-00598: The Google Patents data mentions "PTAB case IPR2024-00598 filed (Settlement)". While this was not in the provided canonical list of active or recently concluded proceedings, its mention of a settlement suggests that some claims may have been challenged and a resolution reached. It would be prudent to investigate the details of this settled IPR, including which claims were challenged and the terms of the settlement (if publicly available). A settlement might imply some perceived risk by the patent owner or petitioner.

Note: The patent's legal status is listed as "Expired - Lifetime" with an anticipated expiration date of 2024-05-07. This means the patent is no longer enforceable for new acts of infringement, but damages for past infringement (prior to May 7, 2024) could still be pursued. This expiration significantly impacts the strategic landscape.

Inventors

• Barry Alan HOBERMAN
• Daniel L. Hillman
• Jon Shiell

Employer at the time of filing: Mosaid Technologies Corp.

Original assignee

Mosaid Technologies Corp. Their primary line of business was intellectual property licensing and development, particularly in the semiconductor and communications industries. Mosaid Technologies Corp. underwent several name changes and reorganizations, eventually becoming Conversant Intellectual Property Management Inc., and then reverting to Mosaid Technologies Incorporated. It primarily focused on patent assertion and licensing.

Assignment timeline

• 2004-11-09 (executed) / recorded 2004-11-09 — Reel 012586/0151

  • Conveyance: Assignment of Assignors Interest
  • Assignor: SHIELL, JON, HOBERMAN, BARRY ALAN, HILLMAN, DANIEL L.
  • Assignee: VIRTUAL SILICON TECHNOLOGY, INC.
  • Correspondent: BARRY C. KESTENBAUM, ATER WYNNE LLP, 222 SW COLUMBIA ST., STE 1800, PORTLAND, OR, 97201
  • Context: Transfer from inventors to Virtual Silicon Technology, Inc.

• 2005-12-07 (executed) / recorded 2005-12-16 — Reel 017122/0769

  • Conveyance: Merger
  • Assignor: VIRTUAL SILICON TECHNOLOGY, INC.
  • Assignee: MOSAID DELAWARE, INC.
  • Correspondent: LINDY C. JOHNSON, MOSAID TECHNOLOGIES INC., 11350 RANDOM HILLS ROAD, SUITE 800, FAIRFAX, VA, 22030
  • Context: Merger of Virtual Silicon Technology, Inc. into Mosaid Delaware, Inc.

• 2006-01-19 (executed) / recorded 2006-01-27 — Reel 017255/0795

  • Conveyance: Change of Name
  • Assignor: MOSAID DELAWARE, INC.
  • Assignee: MOSAID TECHNOLOGIES CORPORATION
  • Correspondent: LINDY C. JOHNSON, MOSAID TECHNOLOGIES INC., 11350 RANDOM HILLS ROAD, SUITE 800, FAIRFAX, VA, 22030. This correspondent recurs in this chain.
  • Context: Change of name from Mosaid Delaware, Inc. to Mosaid Technologies Corporation.

• 2011-01-05 (executed) / recorded 2011-01-05 — Reel 025827/0246

  • Conveyance: Change of Address
  • Assignor: MOSAID TECHNOLOGIES INCORPORATED
  • Assignee: MOSAID TECHNOLOGIES INCORPORATED
  • Correspondent: NICOLE K. PARIZO, MOSAID TECHNOLOGIES INCORPORATED, 11350 RANDOM HILLS RD., SUITE 800, FAIRFAX, VA, 22030
  • Context: Change of address for Mosaid Technologies Incorporated.

• 2011-01-05 (executed) / recorded 2011-01-05 — Reel 025827/0248

  • Conveyance: Assignment of Assignors Interest
  • Assignor: MOSAID TECHNOLOGIES CORPORATION
  • Assignee: MOSAID TECHNOLOGIES INCORPORATED
  • Correspondent: NICOLE K. PARIZO, MOSAID TECHNOLOGIES INCORPORATED, 11350 RANDOM HILLS RD., SUITE 800, FAIRFAX, VA, 22030. This correspondent recurs in this chain.
  • Context: Transfer from Mosaid Technologies Corporation to Mosaid Technologies Incorporated.

• 2012-01-10 (executed) / recorded 2012-01-10 — Reel 027582/0157

  • Conveyance: US INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM
  • Assignor: 658276 N.B. LTD., 658868 N.B. INC., MOSAID TECHNOLOGIES INCORPORATED
  • Assignee: ROYAL BANK OF CANADA
  • Correspondent: MATTHEW P. KADUC, CADWALADER, WICKERSHAM & TAFT LLP, 200 LIBERTY STREET, NEW YORK, NY, 10281
  • Context: Securitization agreement with Royal Bank of Canada.

• 2014-03-13 (executed) / recorded 2014-03-14 — Reel 031448/0263

  • Conveyance: Change of Name
  • Assignor: MOSAID TECHNOLOGIES INCORPORATED
  • Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Correspondent: KEVIN P. ANDERSON, CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., 11350 RANDOM HILLS RD., SUITE 800, FAIRFAX, VA, 22030
  • Context: Change of name from Mosaid Technologies Incorporated to Conversant Intellectual Property Management Inc.

• 2014-08-07 (executed) / recorded 2014-08-11 — Reel 032252/0173

  • Conveyance: RELEASE OF SECURITY INTEREST
  • Assignor: ROYAL BANK OF CANADA
  • Assignee: CONVERSANT IP N.B. 868 INC., CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CONVERSANT IP N.B. 276 INC.
  • Correspondent: MATTHEW P. KADUC, CADWALADER, WICKERSHAM & TAFT LLP, 200 LIBERTY STREET, NEW YORK, NY, 10281. This correspondent recurs in this chain.
  • Context: Release of security interest by Royal Bank of Canada.

• 2014-09-03 (executed) / recorded 2014-09-03 — Reel 032338/0342

  • Conveyance: Change of Address
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Correspondent: KEVIN P. ANDERSON, CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., 100 QUEEN STREET, 4TH FLOOR, OTTAWA, ON, K1P 1J9, CANADA
  • Context: Change of address for Conversant Intellectual Property Management Inc.

• 2014-09-09 (executed) / recorded 2014-09-09 — Reel 032386/0925

  • Conveyance: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS)
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: ROYAL BANK OF CANADA, AS LENDER, CPPIB CREDIT INVESTMENTS INC., AS LENDER
  • Correspondent: KEVIN C. MAHONEY, SKADDEN, ARPS, SLATE, MEAGHER & FLOM LLP, FOUR TIMES SQUARE, NEW YORK, NY, 10036
  • Context: New securitization agreement with Royal Bank of Canada and CPPIB Credit Investments Inc.

• 2018-08-22 (executed) / recorded 2018-08-27 — Reel 041300/0172

  • Conveyance: AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS)
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: CPPIB CREDIT INVESTMENTS, INC.
  • Correspondent: KEVIN C. MAHONEY, SKADDEN, ARPS, SLATE, MEAGHER & FLOM LLP, FOUR TIMES SQUARE, NEW YORK, NY, 10036. This correspondent recurs in this chain.
  • Context: Amended and restated security agreement with CPPIB Credit Investments, Inc.

• 2018-10-12 (executed) / recorded 2018-10-15 — Reel 041530/0308

  • Conveyance: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS)
  • Assignor: ROYAL BANK OF CANADA, AS LENDER
  • Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Correspondent: KEVIN C. MAHONEY, SKADDEN, ARPS, SLATE, MEAGHER & FLOM LLP, FOUR TIMES SQUARE, NEW YORK, NY, 10036. This correspondent recurs in this chain.
  • Context: Release of security interest by Royal Bank of Canada.

• 2020-11-02 (executed) / recorded 2020-11-05 — Reel 046467/0724

  • Conveyance: RELEASE BY SECURED PARTY
  • Assignor: CPPIB CREDIT INVESTMENTS INC.
  • Assignee: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Correspondent: KEVIN C. MAHONEY, SKADDEN, ARPS, SLATE, MEAGHER & FLOM LLP, FOUR TIMES SQUARE, NEW YORK, NY, 10036. This correspondent recurs in this chain.
  • Context: Release of security interest by CPPIB Credit Investments Inc.

• 2021-06-16 (executed) / recorded 2021-06-16 — Reel 047701/0173

  • Conveyance: Change of Name
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY INC.
  • Assignee: MOSAID TECHNOLOGIES INCORPORATED
  • Correspondent: KEVIN P. ANDERSON, MOSAID TECHNOLOGIES INCORPORATED, 100 QUEEN STREET, 4TH FLOOR, OTTAWA, ON, K1P 1J9, CANADA. This correspondent recurs in this chain.
  • Context: Change of name from Conversant Intellectual Property Inc. to Mosaid Technologies Incorporated.

• 2023-08-30 (executed) / recorded 2023-08-30 — Reel 056602/0253

  • Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY'S NAME PREVIOUSLY RECORDED AT REEL: 056602 FRAME: 0253. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME.
  • Assignor: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.
  • Assignee: MOSAID TECHNOLOGIES INCORPORATED
  • Correspondent: KEVIN P. ANDERSON, MOSAID TECHNOLOGIES INCORPORATED, 100 QUEEN STREET, 4TH FLOOR, OTTAWA, ON, K1P 1J9, CANADA. This correspondent recurs in this chain.
  • Context: Corrective assignment related to previous name change, confirming transfer to Mosaid Technologies Incorporated.

Timeline diagram

timeline
    title Ownership of US 7051306
    2004 : Inventors to Virtual Silicon
    2005 : Virtual Silicon merged to Mosaid Delaware
    2006 : Mosaid Delaware name change to Mosaid Corp
    2011 : Mosaid Corp to Mosaid Inc
         : Mosaid Inc security agreement with RBC
    2014 : Mosaid Inc name change to Conversant IP
         : RBC security interest released
         : Conversant IP security agreement with RBC/CPPIB
    2018 : CPPIB security agreement amended
         : RBC security interest released
    2020 : CPPIB security interest released
    2021 : Conversant IP name change to Mosaid Inc
    2023 : Corrective assignment to Mosaid Inc

NPE / troll-pattern signals

1. Shell-entity transfer — present.

   • Reel 017122/0769, recorded 2005-12-16: Virtual Silicon Technology, Inc. merged into Mosaid Delaware, Inc. Mosaid, and its subsequent iterations (Conversant), are widely recognized as patent assertion entities.
   • Reel 031448/0263, recorded 2014-03-14: Mosaid Technologies Incorporated changed its name to Conversant Intellectual Property Management Inc. This name clearly indicates a focus on intellectual property management, not product sales.
   • Reel 047701/0173, recorded 2021-06-16: Conversant Intellectual Property Inc. changed its name to Mosaid Technologies Incorporated, a known NPE.

2. Known asserter in the chain — present.

   • Mosaid Technologies Corp., Mosaid Technologies Incorporated, and Conversant Intellectual Property Management Inc. are all known patent assertion entities (NPEs) or companies that have primarily engaged in patent licensing and enforcement.
   • The Google Patents page itself lists "Mosaid Technologies Inc" as the Current Assignee and has "Family has litigation" with numerous district court and PTAB cases associated with the patent family, supporting its classification as an asserter.

3. Repeat correspondent across the chain — present.

   • LINDY C. JOHNSON (MOSAID TECHNOLOGIES INC.) appears on Reel 017122/0769 (2005-12-16) and Reel 017255/0795 (2006-01-27).
   • NICOLE K. PARIZO (MOSAID TECHNOLOGIES INCORPORATED) appears on Reel 025827/0246 (2011-01-05) and Reel 025827/0248 (2011-01-05).
   • MATTHEW P. KADUC (CADWALADER, WICKERSHAM & TAFT LLP) appears on Reel 027582/0157 (2012-01-10) and Reel 032252/0173 (2014-08-11).
   • KEVIN P. ANDERSON (CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. / MOSAID TECHNOLOGIES INCORPORATED) appears on Reel 031448/0263 (2014-03-14), Reel 032338/0342 (2014-09-03), Reel 047701/0173 (2021-06-16), and Reel 056602/0253 (2023-08-30).
   • KEVIN C. MAHONEY (SKADDEN, ARPS, SLATE, MEAGHER & FLOM LLP) appears on Reel 032386/0925 (2014-09-09), Reel 041300/0172 (2018-08-27), and Reel 041530/0308 (2018-10-15), and Reel 046467/0724 (2020-11-05).

4. Cascading transfers — not present. While there are multiple transfers and name changes, they are spread out over several years and do not show rapid, consecutive transfers within a short timeframe between distinct (non-merged/renamed) shell entities.

5. Pre-litigation transfer — unclear. The provided information states that the patent family has litigation, but specific dates of initial lawsuits relative to assignment dates are not precisely detailed in the provided Google Patents data or the USPTO assignment records.

6. Bankruptcy fire-sale — not present. No indication of bankruptcy proceedings for the original assignee.

7. Privateering — unclear. While Mosaid/Conversant are known NPEs, direct evidence of a specific operating company transferring this patent to them for assertion against competitors (i.e., privateering) is not explicitly detailed in the provided records.

8. Defensive aggregator (anti-NPE) — not present. The chain ends with Mosaid Technologies Incorporated, a known NPE, not a defensive aggregator.

Verdict

NPE — high confidence

The assignment chain clearly indicates a strong NPE pattern. Mosaid Technologies Corp. and its subsequent name changes (Mosaid Technologies Incorporated, Conversant Intellectual Property Management Inc.) are well-known patent assertion entities, as indicated by both the current assignee listed on Google Patents and the history of litigation associated with the patent family. The recurring correspondents across multiple transfers and name changes also strongly suggest a coordinated and consistent strategy for managing an assertion-focused portfolio.

USPTO Assignment Center search: https://assignmentcenter.uspto.gov/

To identify the most relevant prior art for US patent 7051306, a review of its cited references has been performed. The following patent was found in the search results as a cited reference within US7051306.

Prior Art Reference: US6598148B1

• Full Citation: US 6,598,148 B1, "Method and apparatus for managing power consumption in a processor", Moore et al..
• Publication/Filing Date: The publication date for US6598148B1 is July 2003. To confirm the filing date and get a full abstract, further search would be beneficial.
• Brief Description: US 6,598,148 B1 describes a method and apparatus for managing power consumption in a processor. This involves dynamically adjusting power by, for instance, turning off portions of the processor or reducing their operating frequency, often in response to processor utilization or other performance metrics. The underlying principle involves partitioning a system into components where power can be controlled independently.
• Potential Anticipation (35 U.S.C. § 102):
  • Claim 1 (Method): This claim in US7051306 details a method for managing power on an integrated circuit with power islands by determining a target power level, identifying actions to change power consumption, and performing those actions, with selecting a frequency being one such action. US6598148B1's concept of dynamically adjusting power in parts of a processor (which could be considered analogous to "power islands") by reducing operating frequency or turning off components potentially anticipates elements of Claim 1, especially the dynamic power management aspect and the use of frequency selection as an action. The phrase "dynamically change the power consumption of the power islands... based on the needs and operation of the integrated circuit" (as described in US7051306) aligns with the dynamic adjustment based on processor utilization described in US6598148B1.
  • Claim 16 (System): This claim describes a system with power control circuitry and a power manager to achieve similar dynamic power management. While US6598148B1 focuses on a "processor," the underlying system architecture for managing power in partitioned areas could potentially anticipate the broad concept of a system with power control circuitry and a power manager for independent power control in "power islands."
  • Claim 37 (Software Product): This claim covers a software product for power management. US6598148B1, by describing a "method and apparatus," implicitly or explicitly involves software or firmware to implement the dynamic power management. The "power management software operational when executed by a processor to direct the processor to determine a target power level... determine at least one of actions... and perform the at least one of the actions" could be broadly anticipated by a software product implementing the dynamic power management described in US6598148B1.

Due to the general nature of the snippet, further detailed analysis of the full text of US6598148B1 would be required to definitively assess the scope of anticipation, particularly concerning the specific "power island" delineation and hierarchical power management structure emphasized in US7051306.

To conduct an obviousness analysis under 35 U.S.C. § 103 for US Patent 7051306, it is crucial to identify specific prior art references cited during its prosecution. The "Prior art keywords" and the "Description of the Prior Art" sections within the provided patent text describe general challenges and existing techniques (like static voltage islands or multiple clocks) but do not list specific patent or publication numbers that could be combined for an obviousness argument.

A search for "US7051306 cited prior art" or "US7051306 references cited" did not yield an explicit list of prior art documents directly within the provided patent text or its immediate metadata. Without specific prior art references (e.g., other patents, scientific publications), it is not possible to perform a detailed obviousness analysis by combining their disclosed elements.

Therefore, I cannot identify combinations of prior art references that would render the claims of US7051306 obvious, nor can I explain the motivation for combining them, because no specific prior art references were provided or found within the authoritative patent text for this analysis.

To proceed with such an analysis, a list of prior art documents cited by the examiner or applicant during the prosecution of US7051306 would be required. This list typically includes specific patent numbers or non-patent literature that were considered relevant to the patentability of the claims. Once such references are available, each reference would need to be analyzed for its disclosures, and then a determination would be made as to whether a person having ordinary skill in the art (PHOSITA) would have been motivated to combine the teachings of two or more references to arrive at the claimed invention, with a reasonable expectation of success.

For US Patent 7,051,306, here's an analysis of its term and related applications:

Patent Term Adjustment (PTA) and Patent Term Extension (PTE):
The front page of US Patent 7,051,306 states, "Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days." This indicates that there was no Patent Term Adjustment (PTA) granted for this patent due to USPTO delays. PTA can add days to a patent's 20-year term to compensate for certain delays during prosecution at the USPTO.

There is no indication in the patent document itself or in the provided search results that this patent has received a Patent Term Extension (PTE). PTE is typically granted to patents covering products, such as pharmaceuticals or medical devices, that have undergone lengthy regulatory review periods by agencies like the FDA before they can be commercially marketed.

Continuation and Divisional Applications:
The patent lists a "Related U.S. Application Data" section, stating that it claims the benefit of U.S. Provisional Application Ser. No. 60/468,742, filed on May 7, 2003.

The Google Patents page for US7051306B2 lists several "Priority Applications," which can include continuations, divisionals, and continuations-in-part:

• US10/840,893 (this is the application number for US7051306B2 itself)
• US11/336,097, which resulted in US7415680B2 (filed 2006-01-20, priority to 2003-05-07)
• US12/176,645, which resulted in US7945885B2 (filed 2008-07-21, priority to 2003-05-07)
• US12/332,529, which resulted in US7996811B2 (filed 2008-12-11, priority to 2003-05-07)
• US13/164,362, which resulted in US8782590B2 (filed 2011-06-20, priority to 2003-05-07)
• US13/473,129, which resulted in US8762923B2 (filed 2012-05-16, priority to 2003-05-07)
• US14/324,297, which resulted in US9166412B2 (filed 2014-07-07, priority to 2003-05-07)
• US14/865,905, which resulted in US9660616B2 (filed 2015-09-25, priority to 2003-05-07)
• US15/490,557, which resulted in US10243542B2 (filed 2017-04-18, priority to 2003-05-07)
• US16/226,917, which resulted in US10749506B2 (filed 2018-12-20, priority to 2003-05-07)
• US16/928,311, which resulted in US11362645B2 (filed 2020-07-14, priority to 2003-05-07)

These applications generally claim priority back to the original provisional application, meaning they are related family members, likely continuations or divisionals, as they share the same priority date of May 7, 2003. A continuation application claims the same subject matter as an earlier non-provisional application and is filed before the parent application is abandoned. A divisional application is a later application for an independent invention carved out of an earlier application.

Projected Expiration Date:
For applications filed on or after June 8, 1995, the term of a utility patent in the US generally ends 20 years from the filing date of the earliest application for which a benefit is claimed under 35 U.S.C. 120, 121, or 365(c).

US Patent 7,051,306 was filed on May 7, 2004, and claims benefit from a provisional application filed on May 7, 2003. Therefore, its term would typically be 20 years from the earliest priority date, May 7, 2003.

Thus, the anticipated expiration date for US Patent 7,051,306 was May 7, 2023. The patent's legal status is already listed as "Expired - Lifetime" on Google Patents, with an anticipated expiration date of 2024-05-07, which is a year after the 20-year term from the priority date. It's important to note that the "anticipated expiration" date on Google Patents may sometimes reflect the filing date of the non-provisional application rather than the earliest priority date if no PTA or PTE were applied. However, without PTA or PTE, the patent would have expired on May 7, 2023 (20 years from the provisional filing date of May 7, 2003).

The search results confirm that the USPTO Patent Public Search tool can be used to look up patent numbers. I will proceed with generating the defensive disclosure directly, using the provided patent text as the authoritative source, as I already have the full patent text and do not need to retrieve it from USPTO for this task. I have also verified that the patent number is 7051306 and not a similar number.

---

Defensive Disclosure Document for US Patent 7051306

Title: Advanced Dynamic Power Management for Modular Integrated Circuits Using Power Islands

Purpose: This defensive disclosure aims to document numerous technical advancements and alternative implementations related to dynamic power management using power islands on integrated circuits (ICs), building upon the concepts described in US Patent 7051306. The intent is to establish prior art, rendering obvious or non-novel future incremental improvements in this field by competitors. This document explores variations across materials, operational parameters, cross-domain applications, integration with emerging technologies, and failure/low-power modes.

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Derivative Variations for Independent Claims 1, 16, and 37

The following derivatives expand upon the core concepts of US Patent 7051306, which generally describe methods, systems, and software products for managing power on an integrated circuit with a plurality of power islands, where power consumption is independently controlled within each island by a power manager determining a target power level, determining an action, and performing that action (e.g., selecting a frequency).

1. Material & Component Substitution

Derivative 1.1: Gallium Nitride (GaN) based Power Islands with Adaptive HEMT Switching

• Enabling Description: This derivative implements power islands within an integrated circuit fabricated using Gallium Nitride (GaN) semiconductor technology. Each power island utilizes GaN High Electron Mobility Transistors (HEMTs) as the primary power switching and regulation components within its local power control circuitry. The power manager (e.g., SPM, IPM, MPM) determines a target power level and dynamically controls the gate drive and switching frequency of the GaN HEMTs, or adjusts the bias voltage of enhancement-mode HEMTs, to achieve precise Vdd modification or power gating for the corresponding island. This provides superior power efficiency, higher switching speeds, and reduced form factor compared to traditional silicon-based power control, especially for high-frequency or high-power density applications. Signal isolation between GaN islands operating at different Vdd levels employs optical isolators integrated on-chip, leveraging GaN's transparent properties in certain wavelength ranges for improved noise immunity and breakdown voltage.

flowchart TD
    A[Application/OS] --> B(PMCL Firmware)
    B --> C(MPM/IPM)
    C --> D{SPM for GaN Power Island}
    D -- Target Vdd/Freq/GateBias --> E(GaN HEMT Control Logic)
    E --> F(GaN Power HEMT Array)
    F -- Regulated Power --> G(GaN Logic/IP Block)
    G -- Optical Feedback --> E
    H[External Voltage Input] --> F
    I[Optical Isolator] -- Isolated Signal --> G
    F -- Isolated Sense --> D

Derivative 1.2: Flexible Substrate Power Islands with Hybrid Integration

• Enabling Description: The integrated circuit is fabricated on a flexible polymer substrate, such as polyimide, incorporating power islands defined by areas of active circuitry. The power control circuitry for each island utilizes thin-film transistors (TFTs) made from metal oxides (e.g., IGZO) or organic semiconductors, allowing for flexible Vdd multiplexing and clock gating. The power manager, implemented as a separate rigid silicon die, is heterogeneously integrated onto the flexible substrate and communicates with the flexible power islands via embedded flexible interconnects (e.g., stretchable copper traces). Energy storage elements (e.g., thin-film supercapacitors) are co-integrated within each power island to buffer dynamic power demands. This enables power management in deformable or wearable electronic devices.

classDiagram
    class FlexibleSubstrate {
        +Polyimide Material
    }
    class PowerIsland_Flex {
        +Thin-Film Transistors
        +Metal Oxide/Organic Logic
        +Thin-Film Supercapacitor
    }
    class RigidSi_PowerManager {
        +MPM/IPM/SPM Logic
        +Communication Interface
    }
    class FlexibleInterconnect {
        +Stretchable Cu Traces
    }

    FlexibleSubstrate <|-- PowerIsland_Flex
    FlexibleSubstrate <|-- RigidSi_PowerManager
    RigidSi_PowerManager -- FlexibleInterconnect
    FlexibleInterconnect -- PowerIsland_Flex : Controls Power
    PowerIsland_Flex -- FlexibleInterconnect : Status Feedback

Derivative 1.3: Cryogenic Superconducting Power Islands with Quantum-Dot Switching

• Enabling Description: This derivative envisions an integrated circuit designed for cryogenic operation, where power islands are comprised of superconducting circuits (e.g., using NbN junctions) for ultra-low resistance power distribution paths. Power gating and Vdd adjustment within each island are achieved using quantum-dot single-electron transistors (SETs) or Josephson junction-based switches, which exhibit near-zero power dissipation in the superconducting state and highly precise switching characteristics at extremely low temperatures (e.g., 4K or below). The power manager's control signals are transmitted via superconducting transmission lines, and the target power levels are precisely managed by manipulating the quantum states of the switching elements, enabling unprecedented energy efficiency for quantum computing or deep-space applications.

stateDiagram-v2
    state Active_Superconducting {
        PowerOn: Power Island Active
        CriticalThreshold: Thermal Excursion
        PowerOn --> CriticalThreshold : T > T_critical
        CriticalThreshold --> Degraded_Superconducting : System Action
    }

    state Degraded_Superconducting {
        PowerOff: Power Island Power-Off
        Restored: Return to nominal temp
        Degraded_Superconducting --> Restored : T < T_critical
        Restored --> Active_Superconducting : Resume Operation
    }

    [*] --> Active_Superconducting
    Active_Superconducting --> PowerOff : Power_Off_Command
    Degraded_Superconducting --> PowerOff : Forced_Shutdown

    state Power_Manager {
        Control_Signals: Manage SETs/JJ switches
        Monitor_Temp: Monitor Cryo Temperature
    }
    Power_Manager --> Active_Superconducting
    Power_Manager --> Degraded_Superconducting

2. Operational Parameter Expansion

Derivative 2.1: Terahertz (THz) Frequency Power Islands with Dynamic Frequency Scaling

• Enabling Description: This implementation focuses on integrated circuits operating in the Terahertz (THz) frequency range, where each power island contains circuitry designed for THz signal processing (e.g., using resonant tunneling diodes or plasmonic interconnects). The power manager dynamically adjusts the operating frequency of individual THz power islands by controlling THz-source (e.g., photomixers or frequency multipliers) output power and resonant cavity parameters. The "target power level" for a THz island directly correlates with its required THz output power and processing throughput. Actions include scaling the THz clock signal frequency (e.g., 0.5 THz to 2 THz), modulating the amplitude of the THz carrier, or enabling/disabling THz-specific IP blocks. This allows for fine-grained power-performance trade-offs in next-generation high-bandwidth communication or imaging systems.

graph TD
    A[Application Request] --> B(PMCL)
    B --> C(MPM/IPM)
    C -- THz_Freq_Target, THz_Power_Target --> D{SPM for THz Island}
    D -- Control THz Source --> E(THz Clock & Power Generator)
    E --> F(THz Power Island Logic/IP)
    F -- THz_Freq_Actual, THz_Power_Actual --> D
    D -- Feedback --> C

Derivative 2.2: Extreme Temperature (Cryo/High-Temp) Tolerant Power Islands with Predictive Thermal Management

• Enabling Description: The integrated circuit is designed to operate under extreme temperature conditions, either cryogenically (e.g., -196°C) or at very high temperatures (e.g., +200°C for automotive under-hood applications). Each power island is equipped with integrated micro-thermocouples or resistance temperature detectors (RTDs). The power manager employs a predictive thermal model, fed by real-time sensor data from each island, to anticipate "hot spots" or cold-related performance degradation. The target power level is dynamically adjusted to maintain the island within its optimal operating temperature range or prevent thermal runaway/freeze-out. Actions include dynamically adjusting Vdd, clock frequency, or applying localized back-biasing to control leakage, or even pre-emptively powering down an island if thermal limits are projected to be exceeded, and restarting it after stabilization.

stateDiagram-v2
    state Normal_Op {
        entry / Monitor Temp Sensors
        exit / Update Thermal Model
        Normal_Op --> Overheat_Warning : Temp > Threshold_High_Warning
        Normal_Op --> Cold_Warning : Temp < Threshold_Low_Warning
    }
    state Overheat_Warning {
        entry / Reduce Power; Log Event
        exit / Re-evaluate Thermal State
        Overheat_Warning --> Thermal_Shutdown : Temp > Threshold_High_Critical
        Overheat_Warning --> Normal_Op : Temp < Threshold_High_Recover
    }
    state Thermal_Shutdown {
        entry / Power Off Island; Isolate
        Thermal_Shutdown --> Normal_Op : Temp < Threshold_High_Safe && Restart_Cmd
    }
    state Cold_Warning {
        entry / Increase Power; Log Event
        exit / Re-evaluate Thermal State
        Cold_Warning --> Cold_Shutdown : Temp < Threshold_Low_Critical
        Cold_Warning --> Normal_Op : Temp > Threshold_Low_Recover
    }
    state Cold_Shutdown {
        entry / Power Off Island; Maintain Standby Heat
        Cold_Shutdown --> Normal_Op : Temp > Threshold_Low_Safe && Restart_Cmd
    }

    [*] --> Normal_Op

Derivative 2.3: Ultra-Scale Data Center on Chip (DCoC) with Hierarchical Power Orchestration

• Enabling Description: This derivative scales the power island concept to an entire "Data Center on Chip" (DCoC) comprising hundreds to thousands of logically or physically segregated power islands. Each island represents a computational core, memory block, or I/O fabric portion. The power management hierarchy extends to multiple levels: Slave Power Managers (SPMs) at the individual core level, Intermediate Power Managers (IPMs) for racks/clusters of cores, and a Master Power Manager (MPM) orchestrating the entire DCoC. The MPM, often a dedicated power orchestration unit, dynamically allocates power budgets based on global workload scheduling and service level agreements (SLAs). Actions include migrating workloads between islands, throttling performance, or putting entire sections of the DCoC into deep sleep, optimizing for peak performance, energy cost, or cooling capacity across the entire system.

graph TD
    A[Global Workload Scheduler] --> B(MPM - DCoC Orchestrator)
    B -- Power Budget Allocation --> C1(IPM - Rack 1)
    B -- Power Budget Allocation --> C2(IPM - Rack 2)
    C1 -- Power Cmds --> D1(SPM - Core A)
    C1 -- Power Cmds --> D2(SPM - Core B)
    C2 -- Power Cmds --> D3(SPM - Core C)
    D1 -- Power/Freq Control --> E1[Power Island: Compute Core A]
    D2 -- Power/Freq Control --> E2[Power Island: Memory Block B]
    D3 -- Power/Freq Control --> E3[Power Island: I/O Fabric C]
    E1 -- Status/Telemetry --> D1
    E2 -- Status/Telemetry --> D2
    E3 -- Status/Telemetry --> D3
    D1 -- Aggregated Status --> C1
    D2 -- Aggregated Status --> C1
    D3 -- Aggregated Status --> C2
    C1 -- Global Status --> B
    C2 -- Global Status --> B

3. Cross-Domain Application

Derivative 3.1: Aerospace - Satellite Payload Power Management

• Enabling Description: In a satellite's onboard computer (OBC) or reconfigurable payload, power islands are defined for critical sub-systems such as communication transceivers, imaging sensors, attitude control processors, and telemetry units. The power manager, under control of the flight software, dynamically adjusts power to these islands based on orbital mechanics, mission phase (e.g., launch, orbit insertion, nominal operations, science data collection), and available solar array power. For instance, during eclipse, non-essential sensor islands might be powered down or placed in a low-frequency mode, while communication links are maintained at minimal power. Actions involve power cycling specific transponders, dynamically reconfiguring power converters (Vdd adjustment) for sensor arrays, or shifting clock frequencies for error-correction code (ECC) engines, optimizing for battery life and thermal stability in a radiation-hardened IC.

sequenceDiagram
    participant FS as Flight Software
    participant PM as Power Manager (MPM/IPM)
    participant SPM_Comm as SPM (Comm Transceiver)
    participant SPM_Sens as SPM (Imaging Sensor)
    participant SPM_Att as SPM (Attitude Control)

    FS->>PM: Mission_Phase_Update(Eclipse)
    PM->>SPM_Sens: Set_Rate(Low_Power_Mode)
    SPM_Sens->>SPM_Sens: Reduce_Vdd_Freq
    PM->>SPM_Comm: Set_Rate(Min_Comm_Power)
    SPM_Comm->>SPM_Comm: Reduce_Tx_Power_Freq
    PM->>SPM_Att: Maintain_Nominal_Power
    SPM_Att->>SPM_Att: No Change
    SPM_Sens->>PM: Status(Low_Power_Achieved)
    SPM_Comm->>PM: Status(Min_Power_Achieved)
    PM->>FS: Status(Power_Optimized_Eclipse)

    FS->>PM: Mission_Phase_Update(Science_Collection)
    PM->>SPM_Sens: Set_Rate(Full_Performance)
    SPM_Sens->>SPM_Sens: Increase_Vdd_Freq
    PM->>SPM_Comm: Set_Rate(High_Bandwidth)
    SPM_Comm->>SPM_Comm: Increase_Tx_Power_Freq
    PM->>FS: Status(Science_Ready)

Derivative 3.2: Automotive - Zonal ECU Power Optimization

• Enabling Description: In a modern vehicle's zonal electronic control unit (ECU) architecture, power islands are logically or physically segregated for functions like Advanced Driver-Assistance Systems (ADAS) processing (e.g., radar, lidar, camera fusion), infotainment, powertrain control, and body electronics. A central vehicle power manager (VPM), which acts as the MPM, dynamically controls the power levels of these zonal ECUs (IPMs/SPMs) based on driving conditions (e.g., highway cruising, city stop-and-go, parking), driver engagement, and active features. For example, during low-speed parking, high-performance ADAS processing for highway autonomy can be scaled down or powered off, while parking assist features are prioritized. Actions include enabling/disabling ADAS compute clusters (power islands), adjusting voltage/frequency for GPU cores in infotainment, or entering sleep modes for non-critical body control modules, all in real-time to optimize battery consumption and thermal dissipation.

graph LR
    A[Vehicle State/Driver Input] --> B(Vehicle Power Manager (MPM))
    B -- Power Policy --> C(ADAS Zonal ECU (IPM))
    B -- Power Policy --> D(Infotainment Zonal ECU (IPM))
    B -- Power Policy --> E(Powertrain Zonal ECU (IPM))

    C -- Control Signals --> C1[ADAS Sensor Fusion (SPM)]
    C -- Control Signals --> C2[ADAS Perception (SPM)]

    D -- Control Signals --> D1[Display Processor (SPM)]
    D -- Control Signals --> D2[Audio Processor (SPM)]

    C1 -- Vdd/Freq Adjust --> F1[Power Island: Radar/Lidar Processing]
    C2 -- Vdd/Freq Adjust --> F2[Power Island: Camera Vision Processing]
    D1 -- Vdd/Freq Adjust --> G1[Power Island: Graphics/UI]
    D2 -- Vdd/Freq Adjust --> G2[Power Island: Sound Codecs]

    F1 -- Status --> C1
    F2 -- Status --> C2
    G1 -- Status --> D1
    G2 -- Status --> D2
    C -- Status --> B
    D -- Status --> B
    E -- Status --> B

Derivative 3.3: Biomedical Implants - Energy Harvesting & Consumption Management

• Enabling Description: For long-term biomedical implants (e.g., neural interfaces, pacemakers, continuous glucose monitors), power islands are defined for sensing arrays, stimulation circuits, wireless communication modules, and data logging. The power manager intelligently balances energy consumption with often intermittent energy harvesting (e.g., thermoelectric, kinetic, RF-to-DC conversion) and limited battery capacity. It determines target power levels based on physiological activity, communication schedule, and battery state-of-charge. For example, during periods of low activity or sufficient battery charge, the implant might sample physiological data at a higher frequency, while during low battery or intense activity, non-critical sensing or communication is scaled down or temporarily disabled. Actions include reducing the sampling rate of bio-sensors, lowering the output power of telemetry radios, power-gating specific processing units, or adapting the duty cycle of stimulation pulses, all to extend the operational lifetime of the implant.

stateDiagram-v2
    state High_Battery {
        entry / Enable Full Functionality
        Normal_Op: High_Battery
        Normal_Op --> Low_Battery : Battery < Threshold_Low
    }
    state Low_Battery {
        entry / Enter Power_Saving Mode
        Reduced_Functionality: Low_Battery
        Reduced_Functionality --> Critical_Battery : Battery < Threshold_Critical
        Reduced_Functionality --> High_Battery : Battery > Threshold_Recharge
    }
    state Critical_Battery {
        entry / Minimal Functionality; Prioritize Life Support
        Shutdown_Imminent: Critical_Battery
        Shutdown_Imminent --> Low_Battery : Battery > Threshold_Emergency_Recharge
    }

    [*] --> High_Battery
    High_Battery --> PowerManager : Monitor_Energy_Harvesting
    Low_Battery --> PowerManager : Prioritize_Charging
    Critical_Battery --> PowerManager : Initiate_Emergency_Protocol

    PowerManager --> High_Battery
    PowerManager --> Low_Battery
    PowerManager --> Critical_Battery

    PowerManager -- Controls --> PowerIsland_Sensor
    PowerManager -- Controls --> PowerIsland_Comm
    PowerManager -- Controls --> PowerIsland_Stim

4. Integration with Emerging Tech

Derivative 4.1: AI-Driven Predictive Power Optimization

• Enabling Description: The power management system integrates a machine learning (ML) model (e.g., a Recurrent Neural Network or Transformer-based architecture) within the Power Management Control Layer (PMCL) and/or Master Power Manager (MPM). This ML model continuously analyzes historical workload patterns, real-time sensor data (temperature, current draw, voltage fluctuations from SPMs), and application-specific demands to predict future power requirements for each power island. Based on these predictions, the ML model proactively recommends or directly implements optimal power states (Vdd, frequency, Vt biasing, sleep modes) for individual power islands, thereby minimizing latency associated with reactive power scaling and preventing potential thermal excursions or brown-outs. Reinforcement learning can be employed for self-optimizing power policies over long operational periods.

flowchart TD
    A[Workload Data] --> B(Sensor Telemetry)
    C[Historical Data] --> B
    B --> D(Data Preprocessing)
    D --> E(ML Model Training - PMCL)
    E -- Trained Model --> F(ML Model Inference - MPM/IPM)
    F -- Predicted Optimal State --> G(Power Manager)
    G --> H(Power Island Control)
    H -- Actual Power State --> B

Derivative 4.2: IoT Sensor-Integrated Real-time Power Monitoring and Edge Control

• Enabling Description: Each power island is equipped with a micro-IoT sensor module, comprising ultra-low-power current, voltage, and temperature sensors, along with a tiny embedded microcontroller running an MQTT (Message Queuing Telemetry Transport) client. These IoT sensor modules, acting as distributed SPMs, publish real-time power consumption levels and environmental data from their respective power islands to a central MQTT broker. The power manager (MPM/IPM) subscribes to these topics, processes the aggregated sensor data at the edge, and issues optimized power commands (e.g., clock gating, dynamic Vdd scaling) back to the relevant IoT sensor modules/SPMs via MQTT, enabling highly granular, low-latency, and distributed power control across the IC, especially beneficial for large-scale SoCs or multi-chip modules.

graph TD
    A[Power Island 1] --> B1(IoT Sensor Module/SPM 1)
    A[Power Island N] --> B2(IoT Sensor Module/SPM N)
    B1 -- MQTT Publish (Telemetry) --> C(MQTT Broker)
    B2 -- MQTT Publish (Telemetry) --> C
    C -- MQTT Subscribe (Telemetry) --> D(Power Manager (MPM/IPM))
    D -- Decision Logic --> E(Power Policy Engine)
    E -- MQTT Publish (Commands) --> C
    C -- MQTT Subscribe (Commands) --> B1
    C -- MQTT Subscribe (Commands) --> B2
    B1 -- Power Control --> A
    B2 -- Power Control --> A

Derivative 4.3: Blockchain for Secure and Auditable Power Resource Allocation

• Enabling Description: For integrated circuits used in shared computing environments or critical infrastructure, a blockchain layer is introduced to manage and audit power resource allocation. Each power island is represented as a "node" on a permissioned blockchain. Power requests (e.g., "activate high-performance mode for Island X for Y duration") from applications or higher-level power management layers are recorded as transactions. The power manager acts as a smart contract executor, validating these requests against pre-defined power budgets and policies (e.g., maximum power, priority levels) before issuing actual power control commands. The power state changes (e.g., Vdd changed, frequency scaled) and actual power consumption reported by SPMs are cryptographically signed and stored on the blockchain, providing an immutable, transparent, and auditable log of power usage for billing, compliance, or forensic analysis.

sequenceDiagram
    participant App as Application/Client
    participant PMCL as PMCL Layer
    participant SmartContract as PowerAllocation Smart Contract
    participant MPM as Master Power Manager
    participant SPM as Slave Power Manager
    participant PI as Power Island

    App->>PMCL: PowerRequest(IslandID, TargetLevel, Priority)
    PMCL->>SmartContract: ProposePowerTx(IslandID, TargetLevel, Priority)
    SmartContract->>SmartContract: Validate (Budget, Policy, Permissions)
    alt Transaction Valid
        SmartContract-->>MPM: ExecutePowerCommand(IslandID, Action)
        MPM->>SPM: IssuePowerControl(Action)
        SPM->>PI: ApplyPowerChange(Action)
        PI->>SPM: ReportActualState(Power, Freq, Vdd)
        SPM->>MPM: SignedPowerReport(ActualState)
        MPM->>SmartContract: RecordPowerLog(SignedPowerReport)
        SmartContract->>SmartContract: UpdateBlockchain(PowerLog)
        SmartContract-->>PMCL: TxConfirmed(LogID)
        PMCL-->>App: PowerChangeAcknowledged
    else Transaction Invalid
        SmartContract-->>PMCL: TxRejected(Reason)
        PMCL-->>App: PowerRequestDenied
    end

5. The "Inverse" or Failure Mode

Derivative 5.1: Graceful Degradation and "Limp Home" Mode with Prioritized Island Operation

• Enabling Description: The integrated circuit incorporates a sophisticated "limp home" power management strategy. In response to a detected critical fault (e.g., external power supply failure, internal over-temperature event in a critical island, or significant power draw deviation) or a command to enter a low-power maintenance state, the power manager initiates a pre-programmed graceful degradation sequence. It identifies critical power islands (e.g., minimal CPU, emergency communication, safety monitoring) and prioritizes their operation, while non-essential islands are immediately powered off (hard-gated) or forced into an ultra-low-leakage sleep mode. The target power level for critical islands is automatically adjusted to the lowest functional setting required to maintain basic operation, ensuring system survivability or safe shutdown, effectively operating at a fraction of its nominal power budget and functionality.

stateDiagram-v2
    state Normal_Operation {
        entry / Full Functionality
        Normal_Operation --> Fault_Detected : Critical_Fault
        Normal_Operation --> Limp_Home_Command : User/System Cmd
    }
    state Fault_Detected {
        entry / Initiate Graceful Degradation
        Fault_Detected --> Limp_Home_Mode : Fault Assessment Complete
    }
    state Limp_Home_Command {
        entry / Prepare Limp Home Mode
        Limp_Home_Command --> Limp_Home_Mode : Configuration Loaded
    }
    state Limp_Home_Mode {
        entry / Prioritize Critical Islands; Power Off Non-Essential
        Limp_Home_Mode --> Recovery_Mode : Fault Cleared/Restore Cmd
        Limp_Home_Mode --> Emergency_Shutdown : Critical_System Failure
    }
    state Recovery_Mode {
        entry / Power Up Non-Essential; Restore State
        Recovery_Mode --> Normal_Operation : Full Power Up
    }
    state Emergency_Shutdown {
        entry / Immediate Power Off All Islands
        Emergency_Shutdown --> [*]
    }

    [*] --> Normal_Operation

Derivative 5.2: Ultra-Low Leakage Data Retention Mode with Shadow Registers

• Enabling Description: For power islands that contain critical state information (e.g., register values, configuration settings) that must be preserved during extended power-down periods, this derivative integrates "shadow registers" or non-volatile memory elements within each power island's power control circuitry. When the power manager determines an action to power off an island (or enter deep sleep), it first triggers a sequence to automatically save the state of all volatile registers within that island to the adjacent shadow registers. The power-off action then proceeds, reducing the island's Vdd to near-zero or completely disconnecting it, minimizing static leakage. Upon power-up, the power manager triggers the restoration sequence, reloading the saved state from the shadow registers, allowing for rapid and energy-efficient resumption of operation without full re-initialization. This includes the use of multi-threshold (Vt) transistors (high Vt for shadow registers, low Vt for active logic) and anti-glitch circuits during transitions.

sequenceDiagram
    participant PM as Power Manager
    participant SPM as Slave Power Manager
    participant PI as Power Island (Active Logic)
    participant SR as Shadow Registers (Non-Volatile)
    participant VDDM as Vdd Multiplexer

    PM->>SPM: PowerOffRequest(IslandID)
    SPM->>PI: Signal_Freeze_State
    PI->>SR: Save_State_Data
    SPM->>VDDM: Switch_Vdd_Off
    VDDM->>PI: Vdd_Off
    SPM->>PM: PowerOffAck

    PM->>SPM: PowerOnRequest(IslandID)
    SPM->>VDDM: Switch_Vdd_On
    VDDM->>PI: Vdd_On
    SPM->>SR: Restore_State_Data
    SR->>PI: Reload_State
    PI->>SPM: Ready_For_Operation
    SPM->>PM: PowerOnAck

Derivative 5.3: Self-Healing Power Islands with Reconfigurable Redundancy

• Enabling Description: This derivative implements power islands with built-in reconfigurable redundancy and self-healing capabilities. Each power island comprises multiple sub-islands or redundant functional blocks. The power manager (MPM/IPM/SPM) continuously monitors the operational health and power integrity of each sub-island (e.g., current transients, voltage drops, internal clock errors, temperature deviations). Upon detecting a localized failure or performance degradation within a sub-island (e.g., due to aging or soft error), the power manager determines an action to isolate the failing sub-island, re-route power and signals to a redundant healthy sub-island, and/or dynamically adjust the power and frequency of the remaining healthy sub-islands to compensate for the lost capacity. This enables continuous operation, albeit potentially at a reduced performance or increased power level, in the presence of internal faults, enhancing reliability in critical applications.

graph TD
    A[Power Manager] --> B{Power Island with Redundancy}
    B -- Health Monitoring --> C1[Sub-Island A]
    B -- Health Monitoring --> C2[Sub-Island B (Redundant)]
    B -- Health Monitoring --> C3[Sub-Island C]

    C1 -- Fault Detected --> D(Fault Detection & Isolation)
    D --> E{Reconfiguration Logic}
    E -- Power/Signal Reroute --> C2
    E -- Adjust Power/Freq --> C1, C3
    C2 -- Active --> F[Compensated Operation]

    F -- Status --> B
    B -- Aggregated Status --> A

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Combination Prior Art Scenarios with Open-Source Standards

Here are three scenarios combining the concepts of US Patent 7051306 with existing open-source standards, demonstrating how these integrations would constitute obvious advancements.

1. US7051306 and the AMBA (Advanced Microcontroller Bus Architecture) Standard

• Enabling Description: An integrated circuit (IC) is divided into multiple power islands, each with independently controlled power consumption. A hierarchical power management system, as described in US7051306 (comprising MPM, IPMs, and SPMs), is implemented. The communication backbone for control signals, status reporting, and power management commands between the power managers and the power islands themselves is built upon the ARM AMBA (Advanced Microcontroller Bus Architecture) 5 AHB/AXI protocol. Specifically, the power manager firmware (e.g., running on a CPU in a power island) communicates with the MPM via memory-mapped registers accessible over an AMBA AXI interconnect. The SPMs within each power island utilize an AMBA AHB-Lite interface for low-latency, dedicated communication with their respective IP blocks and local power control circuitry. This integration standardizes the communication infrastructure, making power management instructions and telemetry interoperable across diverse IP cores within the SoC.
  • Open-Source Standard: AMBA (Advanced Microcontroller Bus Architecture) Specification, freely available from ARM Holdings.

2. US7051306 and the RISC-V Instruction Set Architecture (ISA)

• Enabling Description: An integrated circuit includes several power islands. The power manager, instead of being a generic microcontroller or hardwired logic, is implemented as a dedicated RISC-V processor core (e.g., a simple RV32I core for SPMs or a more complex RV64GC core for the MPM). This RISC-V core executes the power manager firmware (as described in US7051306, e.g., PM firmware 224, GPAL 214, PMCL 218). The RISC-V processor dynamically determines target power levels, orchestrates actions (frequency scaling, voltage modification, power gating) for its respective power islands by writing to control registers of the power control circuitry. The extensibility of the RISC-V ISA allows for custom instructions to be added specifically for fast power state transitions or complex power monitoring operations.
  • Open-Source Standard: RISC-V Instruction Set Architecture, maintained by RISC-V International.

3. US7051306 and the OpenTelemetry Standard for Monitoring

• Enabling Description: An integrated circuit features multiple power islands, each monitored by a Slave Power Manager (SPM). These SPMs collect detailed power consumption levels, temperature, voltage, and frequency data. Instead of proprietary status messages, each SPM integrates an OpenTelemetry SDK (Software Development Kit). The SPMs export their collected telemetry data (metrics like current, voltage, temperature, events for power state changes) in an OpenTelemetry-compatible format (e.g., OTLP - OpenTelemetry Protocol) to a local OpenTelemetry Collector running within the integrated circuit (perhaps as part of an IPM or MPM). This collector then forwards the aggregated, standardized power management telemetry to an external observability system for analysis, debugging, and visualization. This enables seamless integration with existing monitoring tools and simplifies the development of diagnostic and optimization applications for complex SoCs.
  • Open-Source Standard: OpenTelemetry, an Apache 2.0 licensed project from the Cloud Native Computing Foundation (CNCF).

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