Prior art

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Here's an analysis of the prior art cited in US Patent 6888181:

Most Relevant Prior Art for US Patent 6888181

The following patents are cited as prior art in US Patent 6888181. For each, the full citation, publication/filing date, a brief description, and potential anticipation under 35 U.S.C. § 102 are provided.

1. US Pat. No. 4,996,574

• Full Citation: U.S. Pat. No. 4,996,574 by Shirasaki, entitled “MIS transistor structure for increasing conductance between source and drain regions”
• Publication/Filing Date: Filed Jun. 30, 1989 (Publication date: Feb. 26, 1991)
• Brief Description: This patent discloses a Metal-Insulator-Semiconductor (MIS) transistor. It includes an insulator layer, a silicon body on the insulator layer with source, drain, and a channel region. A gate insulator film covers the channel region (except for the part in contact with the insulator layer), and a gate electrode covers the channel region underneath the gate insulator film (also except for the part in contact with the insulator layer).
• Potential Anticipation (35 U.S.C. § 102): This patent describes a basic MIS transistor structure with a channel region on an insulator. While it introduces the concept of a covered channel and gate, it does not explicitly detail a "fin" structure, a composite fin with a SiGe core and strained silicon layer, or a "triple gate" configuration as claimed in US6888181. It primarily anticipates the general concept of a gate controlling a channel in a semiconductor device. It could potentially anticipate the broad idea of a gate insulating layer interposed between a channel and a gate electrode, which is a common element in all IGFETs (Claim 1, Claim 6). However, the specific strained-silicon and composite fin structure in US6888181 differentiate it significantly.

2. US Pat. No. 5,338,959

• Full Citation: U.S. Pat. No. 5,338,959 by Kim et al., entitled “Thin film transistor with three dimensional multichannel structure”
• Publication/Filing Date: Filed Mar. 30, 1993 (Publication date: Aug. 16, 1994)
• Brief Description: This patent discloses a thin film transistor (TFT) gate structure with a three-dimensional multi-channel structure. The TFT has multiple channel regions for high carrier mobility, each with a three-dimensional structure, and the polycrystalline silicon channel regions are surrounded by gates.
• Potential Anticipation (35 U.S.C. § 102): This patent is more relevant as it describes a three-dimensional multi-channel structure with gates surrounding the channel regions. This directly relates to the "three dimensional Triple Gate (Tri-gate) device" of US6888181 and the concept of a gate wrapping a channel (Claim 1, Claim 6). The description of "polycrystalline silicon channel regions are surrounded by gates" directly addresses the gate-all-around or multi-sided gate concept. However, it does not specify a "composite fin structure consisting of a silicon germanium core and a strained silicon epitaxy layer" (Claim 1) or a "semiconductor core and a strained epitaxy layer" with lattice mismatch (Claim 6), which are key distinguishing features of US6888181. It primarily anticipates the architectural aspect of a 3D multi-channel structure with surrounding gates.

3. US Pat. No. 6,413,802

• Full Citation: U.S. Pat. No. 6,413,802 by Hu et al., entitled “Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture”
• Publication/Filing Date: Filed Oct. 23, 2000 (Publication date: July 2, 2002)
• Brief Description: This patent discloses a FinFET device fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity.
• Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant as it describes a FinFET with a fin extending from an insulating layer and "double gates" over the sides of the channel. This directly addresses the "fin structure" and multi-gate (double gate) aspects of US6888181, which claims a "Triple Gate (Tri-gate)" device. The FinFET design in Hu et al. provides enhanced drive current and suppresses short channel effects, which are also objectives of US6888181. It anticipates the basic FinFET architecture, including a fin-shaped channel and gates on the sides of the channel (Claim 1 and Claim 6). However, US6888181 specifically claims a triple gate device, implying a gate on the top surface in addition to the two sidewalls, and critically, a composite fin structure with a strained silicon layer grown from a silicon germanium core to improve carrier mobility. While Hu et al. mention "double gates" and "a plurality of channels," they do not explicitly teach the strained silicon epitaxy layer on a SiGe core for enhanced mobility.

4. US Pat. No. 6,727,546

• Full Citation: U.S. Pat. No. 6,727,546 by Chau et al., entitled “Self-aligned triple gate silicon-on-insulator (SOI) device”
• Publication/Filing Date: Filed Nov. 13, 2000 (Publication date: Apr. 27, 2004)
• Brief Description: The patent describes a self-aligned triple gate silicon-on-insulator (SOI) device.
• Potential Anticipation (35 U.S.C. § 102): This patent is very relevant due to its title explicitly mentioning a "self-aligned triple gate silicon-on-insulator (SOI) device." This directly anticipates the "Triple Gate (Tri-gate) device" of US6888181 and its general structure built on SOI. This patent would likely anticipate the core concept of a triple-gate architecture (Claim 1 and Claim 6). The critical distinction for US6888181 would again be the specific "composite fin structure consisting of a silicon germanium core and a strained silicon epitaxy layer" (Claim 1) or the broader "semiconductor core and a strained epitaxy layer" with lattice mismatch (Claim 6), which provides the enhanced carrier mobility. Without the detailed description, it's difficult to assess if this reference discloses or suggests the strained silicon channel feature.

5. US Pat. No. 6,764,884

• Full Citation: U.S. Pat. No. 6,764,884 by Fried et al., entitled “Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device”
• Publication/Filing Date: Filed Apr. 3, 2003 (Publication date: Jul. 20, 2004)
• Brief Description: This patent describes a method for forming a gate in a FinFET device and thinning a fin in the channel region of the FinFET device.
• Potential Anticipation (35 U.S.C. § 102): This patent focuses on the method of fabricating a FinFET, specifically addressing gate formation and fin thinning. While it clearly relates to FinFET devices, a core element of US6888181, it is directed to manufacturing processes. It might anticipate aspects of forming a gate strip wrapping a portion of a composite fin structure (Claim 1, Claim 6) if its methods are generic enough to apply to the fin structure in US6888181. However, it does not appear to anticipate the composition of the fin, specifically the strained silicon layer on a silicon germanium core, which is central to US6888181's claims.

6. US Pat. No. 6,838,322

• Full Citation: U.S. Pat. No. 6,838,322 by Haukka et al., entitled “Method for forming a double-gated semiconductor device”
• Publication/Filing Date: Filed May 1, 2003 (Publication date: Jan. 4, 2005)
• Brief Description: This patent describes a method for forming a double-gated semiconductor device.
• Potential Anticipation (35 U.S.C. § 102): Similar to US6764884, this patent focuses on the method of forming a double-gated semiconductor device. While a double-gated device is a precursor to a triple-gated device and shares common principles, this patent describes a method, not necessarily the specific device structure of US6888181. It would likely anticipate general methods for creating multi-gated structures but would not, based on the brief description, disclose or suggest the composite strained-silicon fin structure and its unique materials (Claim 1, Claim 6) of US6888181.

In summary, the prior art most closely anticipates the architectural concepts of multi-gate and fin-based transistors. However, the unique contribution of US6888181 lies in the specific composite fin structure with a silicon germanium core and a strained silicon epitaxy layer for enhanced carrier mobility, which is not explicitly disclosed in these prior art citations. US Pat. No. 5,338,959 and US Pat. No. 6,413,802 touch on 3D multi-channel and FinFET structures, respectively, but lack the specific material composition for strain engineering. US Pat. No. 6,727,546's title explicitly mentions a "triple gate" SOI device, making it highly relevant to the architectural concept, but again, the unique strained silicon channel feature of US6888181 would be the distinguishing factor.