Obviousness

Obviousness Analysis of US Patent 6888181 Under 35 U.S.C. § 103

A patent claim is unpatentable if "the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains." 35 U.S.C. § 103. The Supreme Court's decision in KSR International Co. v. Teleflex Inc. emphasized that obviousness can arise from a combination of prior art elements where a person having ordinary skill in the art (POSITA) would have been motivated to combine them to achieve a predictable result. This motivation can stem from various sources, including the nature of the problem, market pressure, design incentives, or the background knowledge and common sense of a POSITA.

US Patent 6888181 ("the '181 patent") addresses the problem of improving the electrical performance, specifically carrier mobility and drive current, in Triple Gate (Tri-gate) devices and FinFETs. The claimed solution involves a composite fin structure comprising a silicon germanium (SiGe) core and a strained silicon epitaxy layer grown from its surface, integrated into a Tri-gate device.

Combination of Prior Art: Hu et al. (US6413802B1) with Known Strained Silicon Technology and its Implementation using SiGe

A person of ordinary skill in the art (POSITA) in March 2004, motivated to enhance the electrical performance (carrier mobility and drive current) of FinFET devices, would have found the claimed invention obvious by combining the teachings of Hu et al. (US6413802B1) with the widely known and documented advantages of strained silicon technology, including its common implementation using SiGe.

1. Primary Prior Art: Hu et al. (US6413802B1) — FinFET Structures

Hu et al. (US6413802B1) discloses a FinFET device fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX), with the device extending from the insulating layer as a fin. [cite: The Regents Of The University Of California. Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture. US6413802B1, issued July 2, 2002, column 2, lines 34-39] This reference teaches the fundamental three-dimensional "fin structure" and the concept of multiple gates ("double gates are provided over the sides of the channel") to enhance drive current and suppress short channel effects. [cite: The Regents Of The University Of California. Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture. US6413802B1, issued July 2, 2002, column 2, lines 40-44] The '181 patent itself acknowledges that "FinFET is built on a silicon-on-insulator (SOI) substrate. The silicon layer of the SOI substrate is etched into 'fin' like shaped body of the transistor. The gate is wrapped around and over the fin." [cite: United Microelectronics Corp. Triple gate device having strained-silicon channel. US6888181B1, issued May 3, 2005, column 1, lines 60-63] This demonstrates that FinFETs, as a type of 3D transistor with wrapped gates, were a recognized architectural choice in the prior art.

2. Known Problem and Solution: Enhancing Carrier Mobility with Strained Silicon

The '181 patent explicitly states that "the electrical performance such as carrier mobility or device driving current of the above-described SOI-based FinFET and Tri-gate devices can be further improved." [cite: United Microelectronics Corp. Triple gate device having strained-silicon channel. US6888181B1, issued May 3, 2005, column 2, lines 6-9] This highlights a clear and recognized need in the art for improving the performance of existing FinFET devices.

By 2004, the advantages of strained silicon for significantly improving carrier mobility and drive current in MOSFETs were widely recognized and extensively pursued within the semiconductor industry. Major players like Intel, IBM, and AMD were actively developing and integrating strained silicon technology into their microprocessors, including in 90nm technology nodes. Research and industry developments had thoroughly demonstrated that inducing tensile strain in the silicon lattice could substantially enhance both electron and hole mobility, leading to improved transistor performance.

A well-established method for creating the necessary tensile strain in a silicon channel was the epitaxial growth of a thin silicon layer on a relaxed silicon-germanium (SiGe) layer. The intrinsic lattice mismatch between Si and SiGe effectively induces the desired strain in the overlying silicon layer. This technique was a common approach for achieving "global strain" or "biaxial strain" at the wafer level.

3. Motivation to Combine

A POSITA, motivated to address the known problem of improving the electrical performance (specifically carrier mobility and drive current) of a FinFET device, as taught by Hu et al., would have naturally considered known performance-enhancing techniques. Strained silicon was a "Technology Booster" for CMOS developments and was a well-recognized solution for this precise problem. Significantly, prior art literature explicitly "advocated integration of strained-silicon technology in existing FinFETs, which is highly effective in enhancing ON currents through the strain effect."

Therefore, it would have been obvious for a POSITA to combine the FinFET structure described by Hu et al. with the well-understood strained silicon technology, implemented by growing a strained silicon epitaxy layer on a SiGe core. The clear motivation for this combination would be to leverage the superior carrier mobility provided by strained silicon to enhance the drive current of a FinFET device, thereby directly addressing the recognized need to improve FinFET performance. This represents a classic instance of combining known elements (FinFETs and strained silicon on SiGe) to achieve a predictable improvement in a known device.

Furthermore, extending a "double-gate" FinFET (as taught by Hu et al.) to a "Triple Gate" or "Tri-gate" device (where the gate additionally covers the top surface of the fin) would have been an obvious design optimization for a POSITA aiming to maximize gate control and further enhance drive current. The '181 patent itself references "Tri-gate" as a known term and concept in its background section, indicating that multi-sided gating beyond a double-gate structure was understood in the art. [cite: United Microelectronics Corp. Triple gate device having strained-silicon channel. US6888181B1, issued May 3, 2005, column 1, line 16, column 2, line 6] Moreover, Kim et al. (US5338959A) teaches three-dimensional multi-channel structures where channels are "surrounded by gates," further suggesting the concept of multi-sided gate control. [cite: [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) Thin film transistor with three dimensional multichannel structure. US5338959A, issued August 16, 1994, column 1, lines 63-65]

Obviousness of Independent Claims 1 and 6

Independent Claim 1:

• "A three dimensional Triple Gate (Tri-gate) device comprising": This element is taught by Hu et al. (FinFET, a 3D double-gate device), and the general knowledge of Tri-gate devices as an obvious extension for enhanced gate control, as implied by the '181 patent's background and Kim et al.'s "surrounded by gates" concept.
• "a composite fin structure consisting of a silicon germanium core and a strained silicon epitaxy layer grown from surface of said silicon germanium core": This specific composite channel structure is made obvious by combining the silicon fin of Hu et al. with the known technique of using a SiGe layer to induce strain in an overlying silicon layer, motivated by the desire to enhance carrier mobility and drive current, a well-known benefit of strained silicon.
• "a gate strip wrapping a portion of said composite fin structure": This is taught by Hu et al. (double gates over sides) and generally known FinFET principles of wrapped gates.
• "wherein portions of said composite fin structure not covered by said gate strip constitute source/drain regions of said Tri-gate device": This is a standard functional definition for transistors and would be obvious to a POSITA.
• "a gate insulating layer interposed between said composite fin structure and said gate strip": This is a fundamental and well-known component in all field-effect transistors.

Independent Claim 6:
This claim broadly defines a "composite fin structure consisting of a semiconductor core and a strained epitaxy layer grown from surface of said semiconductor core, said semiconductor core having a first lattice constant that miss-matches a second lattice constant of said strained epitaxy layer." This is a generalization of the specific SiGe/strained silicon structure of Claim 1. The same combination and reasoning for obviousness apply, as SiGe and strained silicon are a prominent and well-known example of a semiconductor core and a lattice-mismatched strained epitaxy layer used to achieve performance enhancement through strain.

Therefore, the subject matter of independent claims 1 and 6 of US6888181 would have been obvious to a person having ordinary skill in the art at the time of the invention.