US 6850527

I'll search for authoritative information on this patent number, including any litigation activity.

Let me run one more targeted search for litigation/docket activity specific to this patent.

Search results note

I could not retrieve any USPTO/CAFC docket record showing US 6,850,527 in litigation. No PTAB proceeding, district court case, or CAFC 2026 appeal docket referencing this patent number surfaced. Searches for the number returned only (a) the patent's own Google Patents page, (b) the inventor's patent portfolio page, and (c) unrelated documents that happen to bear the string "6850527" (e.g., a Japanese patent JP 6850527 B2, granted to a different owner for an unrelated recruiting-support invention, and a Chinese invention-certificate number 6850527). None of these is the same patent family. I therefore cannot confirm any 2026 CAFC activity; on the evidence available, there is none. The authority I rely on is the patent document itself.

US 6,850,527 B1 — Bibliographic summary

Abstract (verbatim): "A device for associating indexes to addresses chosen from among a greater number of values than the number of available indexes, including a memory containing indexes and respective check words corresponding to predetermined bits of the addresses associated with the indexes; a packing circuit receiving a current address and suppressing in this address bits determined by a pattern such that the suppressed bits correspond to bits of the check words, the packed address provided by the packing circuit being used to select in the read mode a memory location; and a comparator indicating that the current address corresponds to the selected memory location if the bits of the check word of the selected location are equal to the corresponding bits of the current address."

Technical context: A multiprotocol interface (ATM ⇄ Ethernet) receives 32-bit addresses (24/28-bit VP/VC plus 4 link-ID bits) on a UTOPIA 2 link, but must resolve them to at most 1024 (2¹⁰) active connections. The patent addresses the "many-to-few" address-to-index mapping problem, and explicitly disparages the two conventional alternatives — a 1024-entry linear-search table (too slow: ~512 lookups average, 1024 on a miss) and a fully associative memory (too costly: 1024 × 32-bit comparators and 1024 × 42-bit registers).

Plain-language overview of the independent claims

Claim 1 — The base device (packed-address lookup with check-word verification).
A device maps an index onto an address, where there are far more possible addresses than indexes. A memory holds, per location, an index plus a "check word" made of the address bits sitting in a first set of bit positions. A packing circuit takes the current address and produces a "packed" address consisting of the bits in a second, different set of positions — that packed value selects the memory location (read mode). A comparator then takes the bits of the incoming address in the first position set and compares them against the stored check word; a match means the incoming address genuinely corresponds to that location. The key structural hook is the express requirement that the packing positions and the check-word positions be distinct (no overlap), so the bits used to select the entry and the bits used to verify it are disjoint.

Claim 7 — The same idea as an "address association device" with masking front-end.
Adds a masking circuit ahead of the packing circuit (masking the incoming address bits per a mask pattern), then the packing circuit reduces the bit count into index bits while suppressing the check-word bits at the first predetermined positions per a packing pattern. The memory stores the index bits and check-word bits against a network-connection location, and a comparator compares the selected location's check word against the incoming address's first-position bits. Again, the first and second position sets are distinct.

Claim 12 — The corresponding method.
Receive address bits → mask them per a mask pattern → pack the masked bits down (and suppress the check-word bits at the first positions) → use the packed bits to address a memory location for a network connection → compare the stored check word to the incoming address's first-position bits and signal a match.

Claim 18 — Device specialized to the ATM numeric parameters.
Same memory/packing/comparator architecture, but with the numbers baked in: the packed address is 16 bits, the indexes are 10 bits, and the check words are the twenty most significant bits of the ATM addresses.

Claim 19 — Claim 18 plus the 16-link input.
Everything in claim 18, plus an input configured for connection to sixteen ATM networks, where the addresses carry four most significant bits identifying which ATM network (physical link) they came from.

Claim 20 — Claim 7 restated with a conditional-masking limitation.
The masking/packing/memory/comparator device of claim 7, wherein the masking circuit is configured by the mask pattern to mask the bits that packing does not suppress, in the situation where the number of bits used to address a network connection in memory is fewer than the number of bits left over after packing.

Claim 21 — Method counterpart to claim 20.
Mask → pack (suppressing check-word bits) → associate packed bits with a network-connection memory location → compare selected bits and signal a match, wherein masking is configured to mask the bits not suppressed by packing when the addressing bits available are fewer than the bits remaining after packing.

Claim-drafting observations and uncertainty flags

• Overlap between claims 18 and 19: Claim 19 recites the entire body of claim 18 (identically worded) and appends only the sixteen-ATM-network / four-MSB limitation. That is functionally a dependent-style limitation written as an independent claim.
• Odd antecedent in claims 18/19: Both recite the packing circuit "suppressing bits in the current address in accordance with a pattern such that the suppressed bits correspond to bits of the check words and the bits not suppressed from a packed address," then characterize the "packed address provided by the packing circuit having a 16 bit size." The phrase "and the bits not suppressed from a packed address" is grammatically ambiguous as to whether the packed address itself corresponds to the check words; claims 1, 7, 12, 20 and 21 state the distinctness requirement far more cleanly.
• Specification vs. claims: The specification says the check word "theoretically contains 16 bits," but the implemented embodiment uses the 20 most significant bits of the VP/VC address as the check word (requiring the 8 least-significant bits never be suppressed or masked), yielding the 32-bit word = 10-bit index + 1 enable bit + 20-bit check word. Claim 18 locks in the 20-MSB implementation.
• The mask is a fallback, not the core: Per the description, masking (bitwise AND with register 37) is used only when the interface has fewer bits available to distinguish connections than remain after packing; normally the packing circuit alone performs the selection. There are 16 mask registers and 16 packing-pattern registers, one pair per physical link. The pattern is normally fixed for the life of the interface and, if changed, all open connections must be closed.
• Prosecution history / claim-scope uncertainty: I do not have the file wrapper (Office actions, amendments, any narrowing during prosecution). Given the cited art — notably US 5,481,687 (Alcatel, "reducing the number of bits in a binary word"), US 5,479,401 (Fore Systems, ATM cell interface/dispatch), US 5,934,959 (MMC Networks, cell routing), US 6,034,958 (Ericsson, "VP/VC lookup function"), and US 6,335,932 (Broadcom) — any interpretation of the "distinct predetermined positions" limitation would likely need the prosecution record to assess what that language was added to overcome. Treat the claim-scope reading above as based on the issued text only.
• No legal-status or litigation conclusion is made. The Google Patents page labels status "Expired – Lifetime"; the last recorded fee payment on the face of the record is the 12-year maintenance fee (2016-07-22), consistent with lapse at the 2020-03-10 expiration. That is a records-based observation, not a legal opinion.

I'll search for litigation records involving US patent 6850527.

Let me search more targeted litigation databases.

Let me try additional targeted searches on litigation databases and PACER aggregators.

Litigation Search Results for U.S. Patent No. 6,850,527

No litigation involving U.S. Patent No. 6,850,527 was found.

I searched for the exact patent number in the context of patent litigation (including terms pairing "6850527"/"6,850,527" with "litigation," "lawsuit," "infringement," "complaint," and "defendant," and checking results indexed from CourtListener, PACER-related aggregators, and Unified Patents coverage). No district court case, ITC investigation, or CAFC appeal asserting or challenging this patent surfaced.

Important disambiguation — the following are NOT this patent

Several results returned numbers close to (or including the string) 6850527, but they refer to different assets. Per your instruction not to auto-correct identifiers, I flag these as distinct, not as matches:

About the patent itself (for context)

• Patent: US 6,850,0527... → US 6,850,527 B1, "Device for associating indexes to addresses chosen from a greater number than the number of available indexes"
• Inventor: Pascal Moniot; Assignee: STMicroelectronics S.A.
• Priority: 1999-03-12 (FR 9903261); Filed: 2000-03-10 (US 09/523,572); Granted: 2005-02-01
• Status: Expired – Lifetime (anticipated expiration 2020-03-10)
• Family/publications: FR2790893A1/B1, EP1035689A1 (withdrawn), JP2000332795A

The Google Patents record shows a "Cited By (4)" list (third-party citations, e.g., Alcatel and Hitachi publications) and a list of 10 examiner-cited references — these are prior-art citations, not litigation. Nothing in the record indicates the patent was ever asserted in court.

Caveat on completeness

The online sources available through this search did not include a comprehensive, paywalled litigation database (e.g., full Docket Navigator or Lex Machina coverage), and non-published settlements or arbitrations would not appear in any public source. Based on the sources I could reach:

• Known litigation: none found.
• Per-case details (plaintiff, defendant, jurisdiction, case number, filing date, outcome) therefore cannot be provided, because no case was identified.

If you need a definitive negative, the authoritative next steps would be a direct search on the Unified Patents litigation portal, PACER docket search, CourtListener's RECAP docket search, and USPTO Patent Center / Assignment records — but I must be explicit: I do not have high-confidence confirmation from those primary databases, so I cannot state as fact that no suit was ever filed, only that no litigation surfaced in my searches.

PTAB Proceedings Report — U.S. Patent No. 6,850,527

Patent: US 6,850,527 B1 — "Device for associating indexes to addresses chosen from a greater number than the number of available indexes"
Patent Owner: STMicroelectronics S.A. (France) · Inventor: Pascal Moniot
Priority: 1999-03-12 (FR 9903261) · Filed: 2000-03-10 · Granted: 2005-02-01
Claims: 21 (independent claims 1, 7, 12, 18, 19, 20, 21)
Status: Expired – Lifetime (anticipated expiration 2020-03-10)
Source: Google Patents US6850527B1

Proceedings overview

Zero AIA trial proceedings are on file for US 6,850,527 — no IPRs, no PGRs, no CBM reviews — meaning there is no invalidated-claim breakdown to report, no institution decision, no FWD, no settlement, and no Federal Circuit appeal. The ODP "PTAB proceedings on file" block is empty, and independent web searching surfaced no AIA trial, no PTAB E2E docket, and no CAFC appeal naming this patent. The bottom-line defensive posture is therefore the mirror image of the usual hardened-patent story: nothing has been canceled because nothing was ever challenged. For a defendant being asserted against today, that cuts both ways — there is no IPR estoppel and no FWD to lean on, but there is also no free kill shot, and the single most important fact is that the patent's 20-year term ran out on 2020-03-10. Any live assertion is a backward-looking damages claim (subject to the 35 U.S.C. § 286 six-year recovery window), not an injunction threat.

Proceedings

None. There is no {PROCEEDING_NUMBER} to populate. I am explicitly not inventing a proceeding number, petitioner, panel, or disposition to fill this section.

For the record, the noise my searches returned is not this patent and must not be confused with it:

That collision pattern (STMicro as a frequent petitioner, "685"/"527" suffix matches) is exactly why a bare keyword sweep can look like it found something. It did not.

Strategic summary

Claim status: 100% UNTESTED. All 21 claims — independent claims 1, 7, 12, 18, 19, 20 and 21, and every dependent claim — stand exactly as they issued on 2005-02-01. No claim of US 6,850,527 has been canceled, narrowed by certificate of correction, disclaimed, or held unpatentable by the Board or a court that I can find. There is consequently no "surviving claims" list to hand you; the whole claim set is intact on paper. The counterweight is the calendar: the patent is recorded as Expired – Lifetime with an anticipated expiration of 2020-03-10, and its only foreign siblings are FR 2790893 B1 and JP 2000332795 A (the EP counterpart, EP 1035689 A1, went abandoned). An expired patent can still be asserted for accrued pre-expiration damages, but it cannot support an injunction or ongoing royalty, which drains most of the settlement leverage a PAE needs.

Estoppel landscape: empty. Because no IPR, PGR, or CBM was ever instituted, § 315(e)(2) estoppel has never attached to anyone with respect to this patent. There is no petitioner, no real party in interest, and no privy carrying a bar into district court. For a defendant today that means every prior-art ground remains available — § 102 and § 103 invalidity in court, IPR on any ground not already before the Office, and the printed-publication references cited on the face of the patent as a starting corpus. Note the flip side: the ten references of record (including US 5,484,687, US 5,479,401, EP 0600683 A2, US 5,555,256, US 5,414,701, US 5,936,959, US 6,034,958, US 6,289,014, US 6,262,985, and US 6,335,932) were distinguished during prosecution on the packing/check-word architecture, and US 5,484,687 in particular was the examiner's own "address bit reduction" art — so a fresh § 103 attack would need a motivation-to-combine theory the examiner never saw, not a rerun of what is already of record.

Pattern signals: none. There is no repeat petitioner (because there are no petitioners), no serial-IPR behavior, and no defensive aggregator such as Unified Patents anywhere in the chain. STMicroelectronics appears in PTAB data overwhelmingly as a petitioner against others — it is not a party that has been repeatedly hauled before the Board on this portfolio. The patent's only visible downstream footprint is two third-party citations in later patents (Alcatel's US 2002/0001311, which matured into US 7,065,081, and a Hitachi I/O-path application, US 2010/0312943) — i.e., it has been treated as background art in ATM cell-header lookup work rather than as an assertion target. Taken together, the profile is of a dormant, expired, never-litigated interface patent, not a campaign asset.

Recommended next steps

• If you are a defendant and a demand or complaint cites US 6,850,527: there is no FWD to quote and none exists — do not represent otherwise to a court or adversary. Your first factual lever is the 2020-03-10 expiration, which caps exposure to pre-expiration damages and likely to the six-year § 286 lookback (roughly conduct from September 2020 forward is time-barred on a September 2026 filing, which overlaps entirely with the expired period). Your second lever is § 101/§ 112 and § 103 on the merits, since nothing has ever been tested.
• If you are contemplating an IPR: check availability first. The patent is expired; the Board's treatment of expired patents is a threshold question you should confirm on the current PTAB E2E docket before spending on a petition, and the lack of any injunctive relief usually makes a district-court validity challenge or a § 286 limitations defense a better economic play. There is no § 315(b) one-year bar running against you, because no prior petitioner exists to have triggered service.
• Because there is no PTAB activity, there are no trial-stage milestones to track — no institution deadline, no oral hearing date, no one-year FWD clock. That absence is itself informative: this is an expired 1999-priority STMicro interface patent that was never attacked at the Board, which is consistent with it never having been aggressively asserted. Before treating any demand letter as credible, verify the asserting entity's chain of title from STMicroelectronics S.A. through the USPTO Assignment record; the on-face record shows only the original 2000-06-19 inventor assignment.
• Verification links: PTAB E2E / PTAB Center for the Office's proceedings search, and the USPTO Open Data Portal PTAB API as the canonical structured source. Both were the basis for the "no proceedings on file" conclusion above.

Caveat on confidence: the ODP block is canonical and empty, and my web search corroborated it, but my search surfaced no affirmative "no IPRs filed" statement from a secondary source either. If this patent is currently subject to a very recently filed petition that predates ODP ingest, I would not have seen it. Treat the null result as high-confidence for anything filed more than a few weeks ago, and re-run the PTAB E2E party search under "STMicroelectronics" / patent number 6850527 before filing anything that depends on it.

I'll verify the assignment record and cross-reference sources before reconstructing the chain.

Let me check for any litigation or assertion activity and confirm the current status of the original assignee.

Ownership Chain — US 6,850,527 B1

Patent: "Device for associating indexes to addresses chosen from a greater number than the number of available indexes"
Appl. No.: 09/523,572 · Filed: 2000-03-10 · Granted: 2005-02-01 · Priority: FR 99/03261, 1999-03-12
Status: Expired — Lifetime (anticipated expiration 2020-03-10; 12-year maintenance fee paid 2016-07-22)

Data-access note: The USPTO Assignment Center (assignmentcenter.uspto.gov / assignment.uspto.gov) is a JavaScript application that I could not query directly in this session. The assignment data below is taken from the Google Patents legal-events record (reel/frame, assignor, assignee, effective date), which mirrors the same USPTO assignment filings, plus the Official Gazette issue-notice listing (Indiana University Virtual Disk Library mirror) and the EPO/JP/FR family records. Where a field (notably the correspondent of record) is not surfaced by these mirrors, I say so rather than guess.

Inventors

Pattern notes:

• Single-inventor patent. No co-inventors, so no co-ownership fragmentation risk.
• No inventor-departure signal is derivable here. There is no evidence in the record of Moniot leaving STMicroelectronics near the filing. Note only that STMicroelectronics S.A.'s US filings in this era frequently name a Mandataire (French patent attorney) as the agent of record rather than a US firm — e.g. the PCT family member WO 2003/069630 lists "DE BEAUMONT, Michel; Cabinet Michel de Beaumont, Grenoble" as agent. That is a prosecution correspondent and does not tell us anything about the assignment correspondent.
• Google Patents lists Moniot as inventor of 14 granted US patents, all assigned to STMicroelectronics — a career semiconductor engineer, not a serial filer of self-owned patents. No self-owned or personally-assigned patents appear, which is consistent with a standard employee-invention posture.

Original assignee

STMicroelectronics S.A. — 29, Boulevard Romain Rolland, 92120 Montrouge, France (per the Official Gazette notice for this patent; also stated as Montrouge in the FR/EP records).

• Primary line of business: Semiconductor design and manufacturing — integrated circuits, microcontrollers, MEMS, power and analog devices. A top-scale European operating company (STMicroelectronics N.V. group), one of the largest US patent filers by grant volume.
• Did it ship a product embodying the claims? Likely yes, and this is important context. US 6,850,527 is directed to an ATM/VP-VC address-sorting device inside a multiprotocol interface connecting ATM networks to Ethernet networks (FIG. 1). This is a chip/IP-block feature, not a standalone product — STMicroelectronics was an active supplier of ATM/ADSL and multiprotocol networking silicon in exactly this era, and this patent is the kind of internal interface logic embedded in an ST network-interface ASIC. I cannot point to a specific ST part number from the sources retrieved, so I record this as strong contextual inference, not a verified product mapping.
• Current status: Operating. STMicroelectronics S.A. is an active subsidiary of the STMicroelectronics group, with 3,000+ US grants in the 2015–2025 window (per USPTO PatentsView-derived aggregator data). No bankruptcy, no dissolution, no acquisition of the assignee. The relevant corporate event for the group around this patent's life was the 1998 reorganisation of the Thomson/SGS-Thomson entities into STMicroelectronics — but that predates this filing and does not appear as a recorded assignment here.

Assignment timeline

There is exactly one recorded assignment in this chain. The USPTO record for this patent contains no post-issuance transfer of any kind — no licence recordation, no security interest, no merger, no change of name, no assignment to a holding entity.

• 2000-05-19 (executed) / recorded 2000-06-19 — Reel 010868/0902
  • Conveyance: Assignment (AS — "ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS)")
  • Assignor: MONIOT, Pascal (sole inventor)
  • Assignee: STMICROELECTRONICS, S.A. (Montrouge, France) — the assignee's own in-house filing; the recorded cover text reads ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MONIOT, PASCAL;REEL/FRAME:010868/0902
  • Correspondent: Not surfaced in the Google Patents legal-event entry or the Official Gazette notice. The docket-level Assignment Center entry would show the recording correspondent; I have not verified it and will not name one. Only one appearance exists in any case, so the "repeat correspondent" signal cannot arise from this record regardless of the name.
  • Context: Routine employment/confirmation assignment, not a transfer of an issued patent. Executed 2000-05-19, roughly ten weeks after the 2000-03-10 US filing and fourteen months after the 1999-03-12 French priority date. This is the standard foreign-origin case pattern: a French-origin inventor-executed assignment recorded to perfect the U.S. chain of title for an applicant that is not the inventor. It is not an asset sale, fire-sale, securitisation, or transfer-to-asserter.

Post-issuance activity that is not an assignment: only maintenance-fee payments (2008-07-29, year 4; 2012-07-25, year 8; 2016-07-22, year 12), all recorded under code FPAY with ENTITY STATUS: LARGE ENTITY. Paying a 12-year fee and then allowing the patent to lapse at its 20-year term is the profile of a patent that was maintained to term by its original owner and never monetised.

Important caution — do not over-read the family data: a third-party dataset (a KIPO-linked portfolio table) shows a batch of other STMicroelectronics S.A. patents with "Reassignment year 2016" — i.e. ST did move select patents into other vehicles around 2016. US 6,850,527 does not appear in that list, and the patent's own legal-event record shows no 2016 assignment (only the 12-year fee payment). I am explicitly not applying that batch data to this patent.

Timeline diagram

timeline
    title Ownership of US 6850527
    1999 : French priority application filed
    2000 : US application filed
         : Inventor assigns rights to STMicroelectronics
    2005 : Patent issued
    2016 : Final maintenance fee paid
    2020 : Patent expires

NPE / troll-pattern signals

Negative finding worth stating plainly: the patent expired for free at its 20-year term (2020-03-10). Whatever value a third-party valuation tool asserts for it, no party ever paid to acquire it, and there is no enforcement history. (For the record, patent-analytics site PatentLeaderboard displays an "$11,995,000 approx value" against this patent — that is an algorithmic model output, not evidence of any transaction or demand. It should not be cited as ownership or assertion evidence.)

Verdict

Insufficient data — which here resolves to a non-asserting, single-owner chain.

Justification: the entire assignment record for US 6,850,527 consists of one entry — reel 010868/0902, executed 2000-05-19 and recorded 2000-06-19 — conveying rights from the sole inventor Pascal Moniot to STMicroelectronics S.A. That is a routine employee-invention confirmation filed ten weeks after the US application, not an asset transfer, and it is the only assignment the patent ever had. The assignee is an operating semiconductor manufacturer, all three maintenance fees (4th, 8th, 12th — last paid 2016-07-22) were paid by the original owner as a large entity, and the patent was simply allowed to expire on 2020-03-10 with zero recorded post-issuance transfers and no litigation. Zero of the eight NPE signals are present; per the rubric this is not a "no records" case (there is the original assignment) but it is functionally an original-assignee-retains case, so I map it to Insufficient data on this scale rather than to any NPE category — there is no successor entity whose behaviour could be assessed.

Verify at: https://assignment.uspto.gov/patent/index.html (search 6850527) or https://assignmentcenter.uspto.gov/ — the direct entry you should pull is the Assignment Abstract of Title for reel 010868 / frame 0902, which will also supply the recording correspondent that the public mirrors omitted.

Caveats on sourcing

• The correspondent of record for reel 010868/0902 is the single field I could not verify; every other element of that assignment (reel/frame, dates, parties, conveyance type) is drawn from the Google Patents legal-events record and the Official Gazette issue notice and is reliable.
• The "ST shipped a product embodying the claims" statement is reasoned inference from the patent's own FIG. 1 architecture and ST's product line at the time, not a verified part-level mapping. Treat it as context for the "operating company" determination, which is independently supported by ST's status as a live manufacturer and massive US patent filer.
• No search result contradicted the patent text; where the patent text and the Official Gazette notice agree on the assignee name and address (STMicroelectronics S.A., Montrouge, France), I have used that wording.

I'll search for the patent and its cited prior art references.

Prior-Art Analysis — US 6,850,527 B1

Note on scope and constraints. Patent number 6850527 is taken literally and corresponds to US 6,850,527 B1 (confirmed in the authoritative full text supplied: "US6850527B1 … Device for associating indexes to addresses chosen from a greater number than the number of available indexes," https://patents.google.com/patent/US6850527/en). This is a preliminary technical assessment, not a legal opinion. Anticipation under 35 U.S.C. § 102 requires that every limitation of a claim, arranged as claimed, be disclosed in a single reference; where a reference discloses only some elements, it is properly an obviousness (§ 103) reference, which I note separately. I retrieved the full text/specification of some references; for others I could only retrieve bibliographic data, and I flag those explicitly rather than assert unverified content.

1. The patent under analysis — key dates

Because the application was filed 2000-03-10 with a 1999-03-12 foreign priority, pre-AIA §§ 102(a), (b) and (e) govern the cited art:

• § 102(a)/(b): references publicly available before the invention date / more than one year before filing.
• § 102(e): US patents granted on applications filed before the applicant's invention date (relevant for references published after March 1999 but filed earlier).

2. The independent claims that any anticipation must meet (§ 102 "every element" test)

• Claim 1 — memory locations each holding (i) an index and (ii) a check word equal to a first set of bits at first predetermined positions in the address; a packing circuit producing a packed address from a second, distinct set of bit positions that selects the memory location in read mode; and a comparator that compares the stored check word against the same first bit positions of the current address and signals a match on equality.
• Claim 7 / 12 / 20 / 21 — the mask + pack + store(index, tag) + compare combination in apparatus/method form.
• Claims 18 / 19 — the packing/check-word + 16-bit packed address / 10-bit index / 20-MSB check word + comparator variants.
• Dependent claims add: mask circuit (2, 8, 13, 16), enable bit (3, 9, 10, 14, 15), ATM applicability (4, 5, 6, 18, 19), and base-address register + adder (11, 17).

Central inventive feature to test every reference against: the address is split into a packed/selecting subset and a stored tag ("check word") subset, with a per-location comparator resolving the ambiguity (address collisions) created by packing — i.e., a deterministically-indexed memory with a stored tag, rather than a CAM or a sequential search.

3. The ten cited references (the "Patent Citations (10)" listed on the face of US 6,850,527)

All ten were cited by the examiner (the sources list them with the "*" examiner-cited marker; see the citation tables at https://patents.google.com/patent/US6850527/en). Summary first, detail after.

Reference 1 — US 5,481,687 A (Alcatel N.V.)

Full citation: Method for reducing the number of bits in a binary word representing a series of addresses, US 5,481,687 A; inventors Goubert, Therasse, Pauwels, Wulleman; assignee Alcatel N.V. (equivalent EP 0 552 384 A1, published 1993-07-28). Cited priority 1991-12-23; issued 1996-01-02. Text: https://patents.google.com/patent/[US5481687A](/patent/US5481687A)/en; https://patentimages.storage.googleapis.com/97/22/52/0daea1d26325c4/US5481687.pdf

Description. Reduces the number of bits of an ATM cell-header-based address (VPI/VCI + link number, up to 32 bits) used as the read/write address of a translation memory. It: extracts a "selection address" from fixed-rank bits; uses a mask (from a format memory MF1) to extract a chosen series of bits; compacts/packs those bits into a relative address AV1; and adds a predetermined base address AB(M1i) from a base-address memory MA1 to produce a reduced address AT1 of fewer bits, used to address the translation table. It expressly criticizes the alternative of a content-addressable memory requiring "4096 32-bit registers and 4096 32-bit comparators" plus a masking device.

§ 102 / § 103 assessment. This is the closest structural reference to the packing, masking, and base-address addition aspects:

• "Packing circuit … suppressing in this address bits determined by a pattern" — substantially disclosed (compaction of masked bit groups into a shorter address), supporting claims 1/7/12/20/21 (packing) and the mask limitations of 2/8/13/16.
• "Register configured to store a base address … and an adder for adding the base address" (claims 11, 17) — disclosed almost verbatim (relative address + base address → reduced address).
• It does not disclose a memory location that stores, per connection, both an index and a check word equal to the bits suppressed by packing, nor a comparator comparing that stored word to those address bits. US 5,481,687 produces collision-free reduced addresses by construction and therefore has no need for a tag/check-word. Consequently it does not anticipate any independent claim (1, 7, 12, 18, 19, 20, 21) in full, but it is a strong § 103 reference, in combination, against those claims and squarely relevant to claims 2, 8, 11, 13, 16, 17.

Reference 2 — US 5,479,401 A (Fore Systems, Inc.)

Full citation: ATM cell interface and method for dispatching an ATM cell, US 5,479,401 A; continuation of Ser. No. 07/930,081 (now US 5,323,389); assignee Fore Systems, Inc. Cited priority 1992-08-14; issued 1995-12-26. Text: https://patents.google.com/patent/US5479401

Description. An ATM cell interface routes cells via a two-level table lookup: a first-level table indexed by the VPI produces an INDEX signal; a second-level table indexed by the VCI value plus that first signal produces CONNECTION INFORMATION used to route the cell. It emphasizes that the number of possible table entries is less than the total number of entries supported by the ATM cell header, avoiding "bit-stripping" and using VCI range low/high bounds.

§ 102 / § 103 assessment. Discloses ATM-header-to-connection-information table lookup where the table is smaller than the address space (relevant to claim 4 and the general problem statement), and the general use of VCI/VPI bits to index. It does not disclose splitting the address into a packed selecting subset plus a stored check word of the suppressed bits, nor the per-location comparator of claim 1(c). No full-claim anticipation; useful § 103 context, especially against claim 4.

Reference 3 — EP 0 600 683 A2 (AT&T Corp.)

Full citation: Packet network interface, EP 0 600 683 A2; assignee AT&T Corp. Cited priority 1992-12-04; published 1994-06-08. (Listed on the face of US 6,850,527 without the examiner-cited asterisk in both citation tables; treat its citation status with caution.)

Description / assessment. Titled as a packet network interface for a cell/packet network (address/header handling and interface between a network and a host/switch). I could not retrieve its specification, so I will not assert specific content. On the bibliographic record it is § 102(b) art (published 1994, well before the 1999 priority date) and is most plausibly § 103 context for the ATM-interface environment of claim 4 and for known table-based header translation. Its potential to anticipate claim 1 cannot be confirmed from the record retrieved.

Reference 4 — US 5,555,256 A (Hewlett-Packard Company)

Full citation: Channel identifier generation, US 5,555,256 A; assignee Hewlett-Packard Company. Cited 1994-04-28; issued 1996-09-10.

Description / assessment. Concerns generating channel identifiers, i.e., producing the short identifier ("index") associated with a channel/connection — conceptually related to the "index identifying a connection" element of claims 1/4/5. I did not retrieve the specification; I therefore flag that the exact mechanism is unverified. On dates it is § 102(b) art. Most plausibly § 103 material bearing on the index-identification concept, not a full-claim § 102 reference.

Reference 5 — US 5,414,701 A (Motorola, Inc.)

Full citation: Method and data structure for performing address compression in an asynchronous transfer mode (ATM) system, US 5,414,701 A; assignee Motorola, Inc. Cited 1994-07-22; issued 1995-05-09. Text: https://patents.google.com/patent/US5414701

Description. Hierarchical address compression: a physical-layer identifier indexes a link table; the selected entry points to one of several virtual path tables; the VPI is masked with a virtual-path mask to form a virtual-path index used to select a VP entry; a virtual-channel offset from that entry plus the VCI selects a virtual-channel table entry; the entry yields an ingress connection/channel identifier. Stated motivation: the ATM space allows 4096 VPs × 65,536 VCs (≈2.7×10⁸ connections) while rarely more than ~4000 are active — exactly the "addresses chosen from a greater number of values than the number of indexes" problem.

§ 102 / § 103 assessment. Discloses masking of ATM address fields to derive an index into tables that yield a connection identifier (relevant to claims 2, 4, 8, and the general compression premise), but the tables are hierarchical and there is no stored check word of the suppressed bits with a comparator. No full-claim anticipation; § 103 reference, strongest against the masking/compression claims.

Reference 6 — US 5,936,959 A (MMC Networks, Inc.)

Full citation: Cell routing in ATM networks, US 5,936,959 A; assignee MMC Networks, Inc. Cited 1996-05-31; issued 1999-08-10.

Description / assessment. Generally directed to routing ATM cells (header-based cell routing in a switching fabric). Publication (1999-08-10) postdates the 1999-03-12 priority date, so it cannot be § 102(a)/(b) art; it is available only as § 102(e) art because its application was filed 1996-05-31, before the applicant's date. I did not retrieve its specification, so I do not assert its disclosure. It is most likely § 103 context (cell-routing table lookups).

Reference 7 — US 6,034,958 A (Telefonaktiebolaget LM Ericsson)

Full citation: VP/VC lookup function, US 6,034,958 A; assignee Telefonaktiebolaget LM Ericsson. Cited 1997-07-11; issued 2000-03-07. Text: https://patentimages.storage.googleapis.com/21/d2/63/c0cb56684a1a97/US6034958.pdf

Description. A VP/VC connection-table lookup for ATM switches that hash-codes the virtual connection information (PHY/VPI/VCI, ~33 bits) into a reduced-length hash code, then performs a binary search in a search table; it stores search records containing a virtual connection information field and a connection identifier field, and includes compare logic that compares the virtual connection information with at least portions of the records. It also selectively masks a virtual channel identifier when the connection corresponds to an active virtual path. Motivation is explicitly to avoid impractically large direct-indexed tables.

§ 102 / § 103 assessment. Structurally the most interesting examiner citation:

• Mapping a large PHY/VPI/VCI word to a reduced-length code used to index a table (≈ the "packing circuit … packed address used to select … a memory location," claim 1(b)).
• Storing, in each record, a connection identifier plus virtual connection information for comparison (≈ "index and check word", and the comparator of claim 1(c)).
• Selectively masking part of the virtual connection information (≈ the mask circuit, claims 2/8).
• Dates: filed 1997-07-11 → § 102(e) art; it cannot be § 102(b) because it issued 2000-03-07.

The gap for strict anticipation: Ericsson's reduction is a hash (CRC/XOR-based), not a deterministic "suppression of bits determined by a pattern" whose suppressed bits are themselves stored as the check word and compared bit-for-bit. That distinction supports an argument that it does not disclose the "second set of bits … first and second predetermined positions being distinct / suppressed bits corresponding to check-word bits" formulation of claim 1 with sufficient exactness. Best characterized as a strong § 103 reference (alone or with US 5,481,687) against claims 1, 2, 7, 8, 12; a § 102 rejection would be arguable but vulnerable.

Reference 8 — US 6,289,014 B1 (Fujitsu Limited)

Full citation: Multiline-correspondent cell header conversion apparatus and method, US 6,289,014 B1; assignee Fujitsu Limited. Cited 1998-03-19; issued 2001-09-11.

Description / assessment. Concerns cell-header conversion across multiple lines (VPI/VCI translation in a multi-line/multi-port ATM context). This bears on the multi-network / physical-link-identification aspects of claims 4 and 6 (16 ATM networks, 4 MSB link-identification bits). Filed 1998-03-19 → § 102(e) art. I did not retrieve the specification; on the record, it is § 103 material, not a full-claim anticipation.

Reference 9 — US 6,262,985 B1 (Nortel Networks Limited)

Full citation: Method and apparatus for full range translation of large external identifier to small internal identifier, US 6,262,985 B1; assignee Nortel Networks Limited. Cited 1998-03-30; issued 2001-07-17.

Description / assessment. By its title and stated purpose, this reference addresses exactly the problem of US 6,850,527: translating a large external identifier into a small internal identifier (i.e., mapping addresses drawn from a value space much larger than the number of available internal indexes — the literal title of the '527 patent). Filed 1998-03-30 → § 102(e) art.

I was not able to retrieve the full specification text within the tool budget, so I do not assert that it discloses the specific "check word = the bits suppressed by packing, compared by a comparator" structure. I flag it as the single most likely § 102 candidate against claim 1 and recommend that its claims/specification be read against claim 1's three elements (packed selecting subset; stored index + tag; per-location comparator). If it performs the large-to-small translation with a stored residual/tag and comparison, claim 1 and its apparatus/method counterparts (7, 12, 20, 21) are directly implicated.

Reference 10 — US 6,335,932 B2 (Broadcom Corporation)

Full citation: High performance self balancing low cost network switching architecture based on distributed hierarchical shared memory, US 6,335,932 B2; assignee Broadcom Corporation. Cited 1998-07-08; issued 2002-01-01.

Description / assessment. A network switch architecture using distributed hierarchical shared memory and forwarding/lookup tables. Filed 1998-07-08 → § 102(e) art. It is general background for memory-based lookup/forwarding structures and is § 103 material at most; it does not appear to teach the pack/tag/compare combination of claim 1.

4. Consolidated conclusions

1. No cited reference appears to anticipate claim 1 (or claims 7, 12, 18, 19, 20, 21) as a whole, on the records retrieved. Every independent claim requires the combination of (i) a packed/selecting bit subset and (ii) a stored check word of the suppressed bits compared by a per-location comparator. The references split into two camps:

   • Bit-reduction/indexing without a stored tag: US 5,481,687 (Alcatel — masking + packing + base-address adder), US 5,414,701 (Motorola — masked hierarchical compression), US 5,479,401 (Fore — two-level table lookup).
   • Indexing with stored record + comparison, but via hashing rather than bit-suppression: US 6,034,958 (Ericsson — hash + search table + compare logic + selective VCI masking).
     None clearly supplies both halves of the claim-1 combination in the claimed arrangement.

2. Most relevant references, ranked:

   • US 6,034,958 (Ericsson) — strongest § 103 reference for the "reduced-length index + stored identifier + comparison + selective masking" combination; arguable (but not clean) § 102.
   • US 5,481,687 (Alcatel) — closest to the packing/masking and base-address-adder limitations (claims 2, 8, 11, 16, 17).
   • US 6,262,985 (Nortel) — addresses the identical large-ID-to-small-ID problem; top unverified § 102 candidate against claim 1.
   • US 5,414,701 (Motorola) — masking/compression of ATM VPI/VCI (claims 2, 4).
   • US 6,289,014 (Fujitsu) — multi-line header conversion (claims 4, 6).

3. § 102 vs. § 103 posture: Because the cited art is a mix of (a) bit-reduction schemes with no stored tag and (b) hash/tree lookups with stored records, the realistic challenge is § 103 (combination of US 5,481,687 with US 6,034,958 or US 6,262,985), not a clean § 102 anticipation — subject to the caveat in item 4.

4. Verification gaps (stated explicitly per instructions): I obtained the full specification of US 5,481,687, US 5,479,401, US 5,414,701 and US 6,034,958, and the file-wrapper text of US 6,850,527. I did not retrieve the specifications of US 5,555,256, EP 0 600 683 A2, US 5,936,959, US 6,289,014, US 6,262,985, or US 6,335,932 within the available search budget. Assertions about those six are therefore limited to their bibliographic records and titles, and the descriptions for them above should be treated as unverified. In particular, the § 102 potential of US 6,262,985 (Nortel) and the content of EP 0 600 683 A2 (AT&T) should be confirmed against the full specifications before reliance.

5. Family/timeline note: FR 2790893, EP 103 5689 A1 and JP 2000-332795 A are family members of the same application, not prior art. The "Cited By" documents (US 2002/0001311, US 7,065,081, US 2010/0312943, US 8,407,391) and the "Similar Documents" listings are not § 102 prior art to US 6,850,527 and were excluded from the analysis.

Sources for the patent and the references examined: https://patents.google.com/patent/US6850527/en · https://patents.google.com/patent/US5481687A/en · https://patents.google.com/patent/US5479401 · https://patents.google.com/patent/US5414701 · https://patentimages.storage.googleapis.com/21/d2/63/c0cb56684a1a97/US6034958.pdf · https://patents.google.com/patent/EP0552384A1/en

I'll research the cited prior-art references before building the § 103 analysis, so the combinations rest on what these documents actually disclose.

Now let me pull the remaining cited references so every proposed combination is grounded in disclosure.

Obviousness Analysis — U.S. Patent 6,850,527 B1

"Device for associating indexes to addresses chosen from a greater number than the number of available indexes"
Inventor: Pascal Moniot · Assignee: STMicroelectronics S.A. · App. 09/523,572, filed 2000‑03‑10 · FR priority 1999‑03‑12 (FR9903261) · Granted 2005‑02‑01

Scope note: This analysis is built only from the ten references listed in the "Patent Citations" (Prior Art) section of the patent page (https://patents.google.com/patent/[US6850527](/patent/US6850527)/en). Five of the ten were content‑verified by search during this analysis; the other five are addressed from their titles/abstracts and flagged as unverified. No fabricated disclosure is attributed to any reference.

1. Executive summary

2. Governing law and framework

• The application was filed 2000‑03‑10, before 2013‑03‑16, so pre‑AIA § 102/§ 103 apply. The 1999‑03‑12 French priority date is presumptively the invention date.
• Six of the ten cited references (US 5,414,701; US 5,479,401; US 5,481,687; US 5,555,256; EP 0 600 683 A2) published more than one year before the U.S. filing date and are therefore § 102(b) statutory‑bar art — not swearable‑behind.
• Four (US 5,936,959, filed 1996‑05‑31; US 6,034,958, filed 1997‑07‑11; US 6,262,985, filed 1998‑03‑30; US 6,289,014, filed 1998‑03‑19; US 6,335,932, filed 1998‑07‑08) granted after the priority date but were filed before it, and so are available as pre‑AIA § 102(e) art notwithstanding their later grant dates. None is commonly owned with the application, so the § 103(c) disqualification does not apply.
• The obviousness inquiry follows Graham v. John Deere (scope/content of art; differences; PHOSITA level; secondary considerations) applied through KSR Int'l v. Teleflex (motivation may be found in design incentives, market/technological trends, the finite number of identified predictable solutions, and the "lead suggested by the prior art").
• The "Cited By" and "Similar Documents" entries on the page (e.g., US 7,065,081, US 8,407,391, US 7,424,022) post‑date the priority date and are not § 103 art here; they are used only for context, not as the basis of any rejection.

3. What the claims require

Seven independent claims: 1, 7, 12, 18, 19, 20, 21. The common core across them:

1. Memory locations each holding (a) an index and (b) a check word, the check word being "a first set of bits having first predetermined positions in the address."
2. A packing circuit that reduces the current address to "a second set of bits having second predetermined positions," where the first and second predetermined positions are distinct (i.e., the bit positions used as the index and the bit positions stored/compared are complementary subsets of the address).
3. The packed address selects the memory location in read mode (direct‑mapped lookup, not a search).
4. A comparator that compares the selected location's check word to the same "first predetermined positions" of the incoming address, and signals a match.

Claim 7 and 20 pull the masking circuit into the independent claim (it is only dependent claim 2 in claim 1's chain). Claims 18/19 hard‑code 16‑bit packed address, 10‑bit index, and 20 MSB check word, and (claim 19) 16 ATM networks identified by 4 MSBs. Claims 12/21 are the method counterparts. Claims 8/13/16/20/21 add the condition that the mask is used "when the number of bits used to address a network connection … is fewer than the number of bits remaining after packing."

4. Prior art reference table

5. Level of ordinary skill

A POSITA here would hold a B.S. in EE/CS (or equivalent) plus roughly 2–3 years designing ATM network interfaces or switch ASICs — i.e., familiarity with ATM cell framing (VPI = 12 bits, VCI = 16 bits, PHY/port id ≈ 4–5 bits; UNI 24‑bit vs. NNI 28‑bit address spaces), with CAM‑vs‑RAM lookup tradeoffs, with hashing, and with direct‑mapped table indexing. Every reference above is written to that audience, and the patent itself assumes it.

6. The obviousness combinations

Combination A (primary): US 5,481,687 (Alcatel) + US 6,034,958 (Ericsson) — renders claims 1, 2, 4–7, 9–12, 14, 15, 18, 20, 21 obvious

Why the combination is suggested:

1. Identical field and identical problem. Both are ATM cell‑header translation/lookup mechanisms operating at a switch node or interface. Alcatel states the problem in the same words the patent uses: "the addressing capacity provided by the standardized header is far in excess of the number of channels which actually arrive at a node." Ericsson states it too: VPI+VCI+PHY is "on the order of thirty‑three bits," far more than the connections actually supported.
2. Complementary teachings that fill each other's gaps. Alcatel supplies the indexing half: mask a predetermined bit set ("the format of this series is predetermined"), compact the surviving bits into a selection address of "14 or 16 bits instead of 28 or 32," and add a base address — i.e., claim 1's "packing circuit," claim 2's mask, and claims 11/17's base‑address register + adder. Ericsson supplies the confirmation half the packing leaves open: a table whose records hold a virtual connection information field and a connection identifier field, addressed by the reduced‑length code, with compare logic that compares the virtual connection information to the records indexed by the code, plus testing for active VPC/VCC status.
3. Express "lead" against the expensive alternative. Alcatel expressly rejects the 4,096‑comparator CAM because it "could not be integrated in a single integrated circuit"; Ericsson expressly rejects large one‑stage tables and CAM. Both point the POSITA toward a small direct‑indexed table plus a cheap compare — which is precisely the claimed device. This satisfies the KSR "design incentive" and "finite number of predictable solutions" rationales.
4. Predictable result. Partitioning a 32‑bit address into (i) a subset used as a table index and (ii) the complementary subset stored and compared is a mechanically predictable re‑arrangement; the benefit (one memory access, one comparator instead of 1,024) follows necessarily. No new or unexpected property arises.

Mapping (claim 1):

Mapping (claim 11 / 17, base address + adder): ✅ Alcatel's base‑address memory MA1 + addition operation "3"; ✅ US 6,262,985's initial LUT base‑address + adder.

Combination B (alternative primary): US 5,414,701 (Motorola) + US 5,555,256 (HP) — renders claims 1, 3–7, 9–10, 12, 14, 18, 19 obvious

• Motorola supplies masking + table indexing + base/offset addition in the ATM header context: "a virtual path index is formed by masking the virtual path identifier with the virtual path mask," and the PHY ID indexes a link table — directly meeting claim 2 and (via the 4‑bit PHY/port field) claims 6/19's "four most significant bits enabling identification of the corresponding ATM networks."
• HP supplies the stored‑identifier + occupancy half: a table holding master VCNs looked up by indexes derived from a long channel identifier, with logic for an "occupying entry."
• Motivation: Motorola's own text supplies it — "268,435,456 connections are allowed in the ATM standard, [but] rarely are more than 4000 active connections" — creating the design incentive to compress the index; HP supplies the known technique for holding a short internal identifier at a table location with occupancy tracking. Both are ATM switch artifacts; both aim at fast, low‑cost tag generation.

Combination C (for the numeric limitations of claims 5/18/19): + US 6,262,985 (Nortel)

Nortel expressly works with the exact field widths at issue — VPI 12 bits, VCI 16 bits, port identifier 4 bits (32‑bit ECI) and a 20‑bit internal identifier — and uses a 64K × 32‑bit LUT. That supplies the arithmetic basis for the claimed 16‑bit packed address / 10‑bit index / 20‑MSB check word / 4‑bit network identifier, and its mask‑count decoder + AND gate + mask associated with the LUT entry supplies the "annulling bits other than those suppressed by packing" limitation of claims 2, 7, 8, 13, 16, 20, 21. Choosing 16/10/20 for a 32‑bit ATM address is a routine design choice once the ATM UNI/NNI field sizes are fixed by standard.

Combination D (multi‑line aspects, claims 6/19): + US 6,289,014 (Fujitsu) and US 6,034,958

Ericsson's PHY field ("a typical size for the physical link identifier (PHY) is 5 bits") and HP's port label teach combining a physical‑link identifier with the VP/VC bits; Fujitsu's "multiline‑correspondent cell header conversion" addresses the same many‑lines/one‑engine context. Aggregating 16 links into one lookup engine with a 4‑bit link prefix is thus suggested.

7. Claim‑by‑claim conclusion

8. Anticipated rebuttals and secondary considerations

The patentee's strongest non‑obviousness argument is structural complementarity: neither Alcatel nor Ericsson stores only the suppressed bits and compares them at the identical bit positions after a direct‑mapped, single‑access read. Alcatel's compaction is a one‑to‑one remapping; Ericsson's hash + binary search compares a whole search record and iterates rather than performing one direct‑mapped read.

Counter‑arguments:

• The complementarity is the necessary arithmetic consequence of partitioning a fixed‑width address into an index field and a residual field; once one chooses a direct‑mapped table (which both Alcatel and the patent's own Background favor on cost grounds), storing the residual bits is the only way to detect aliasing, and comparing them at their original positions is the natural implementation.
• US 6,262,985 shows the mask being used precisely to confine the transformed address to a page — i.e., the mask step is a known tool for reconciling an address width with a smaller memory, not a novel insight.
• No teaching away: Alcatel's criticism of CAM is a criticism of the 1,024‑comparator approach, which is exactly what the patent also criticizes — not of the claimed single‑comparator design.
• No objective evidence of non‑obviousness appears anywhere in the record: no unexpected results, no long‑felt need tied to this structure, no commercial‑success data with nexus to the claims (a device embedded in STMicroelectronics' multiprotocol interface would require nexus evidence to be probative). The patent's stated advantage — "efficient in terms of rapidity and material cost" — is the expected benefit of substituting one memory read plus one comparator for 1,024 parallel comparators; an expected advantage does not rebut a prima facie case.

9. Bottom line

On the cited art, the examiner's rejection posture should be a § 103 combination rather than anticipation:

• Primary: US 5,481,687 or US 6,034,958, each alone showing the key indexing‑and‑confirmation halves;
• Secondary: the other of those two, plus US 5,414,701 for the PHY‑indexed masking path, US 5,555,256 for stored identifiers with occupancy, and US 6,262,985 for the mask + base‑address paging and the exact ATM field widths;
• Motivation: identical ATM header‑translation field, identical excess‑capacity problem, express design incentives to avoid CAM and large LUTs, and predictable, purely mechanical combination results.

Claims 1–21 are, in my judgment, more likely than not obvious on this record, with the caveat noted in the table above for the narrower masking‑condition claims and the multi‑line claims.

Verification caveats (please read before relying on this)

1. I verified the content of US 5,481,687, US 5,414,701, US 5,555,256, US 6,034,958, and US 6,262,985 against their full texts/claims. Statements about them above are quoted or closely paraphrased.
2. I did not verify the internal disclosures of US 5,936,959, US 5,479,401, US 6,289,014, US 6,335,932, or EP 0 600 683 A2 within this session — the tool budget was exhausted. My statements about those five are limited to title/abstract‑level observations, and the combinations resting on them (notably claims 6/19 via Fujitsu) should be re‑checked against their full texts before being asserted in a filing.
3. Reference numbers, dates, and statuses are reproduced literally from the patent page and were not auto‑corrected. All pre‑AIA § 102(e)/(b) characterizations assume the 1999‑03‑12 priority date is also the invention date; earlier conception evidence would change those dates.
4. This is a technical prior‑art analysis, not a legal opinion or a validity determination.