US 6838651

The current date is April 26, 2026.

Here's a concise summary of US Patent 6,838,651:

US Patent: 6,838,651

• Title: High sensitivity snap shot CMOS image sensor

• Assignee: Re Secured Networks LLC, ESS Technologies International Inc. (Current assignees listed by Google Patents. Re Secured Networks LLC is the most recent assignee according to legal events.)

• Inventor: Richard A. Mann

• Filing Date: March 28, 2002

• Issue Date: January 4, 2005

• Abstract: The invention describes a solid-state imaging device featuring a red pixel, a blue pixel, a first green pixel, and a second green pixel. It utilizes two analog-to-digital (A/D) converters: the first A/D converter processes the outputs of the red and blue pixels into digital signals, and the second A/D converter processes the outputs of the two green pixels into digital signals. A color interpolation circuit then combines these digital signals to determine the pixel's color. An optional embodiment includes a third and fourth A/D converter, a programmable clock generator, and a control. The control deactivates the third and fourth A/D converters at a slower first clock frequency and activates them at a faster second clock frequency.

• Plain-Language Overview of Independent Claims:

  • Claim 1: This claim outlines a solid-state imaging device comprising distinct red, blue, first green, and second green pixels, each with an output. The device includes a first analog-to-digital (A/D) converter that converts the red and blue pixel outputs into digital signals. A second A/D converter performs the same function for the first and second green pixel outputs. Finally, a color interpolation circuit combines these four digital signals.
  • Claim 13: This claim describes a solid-state imaging device featuring "groups of pixels," where each group contains a red, blue, first green, and second green pixel, all with outputs. A first A/D converter converts the outputs from the collective "red pixels" and "blue pixels" into digital signals. Similarly, a second A/D converter processes the outputs from the collective "first green pixels" and "second green pixels" into digital signals. A color interpolation circuit then combines these four resulting digital signals. This claim emphasizes the application to an array of such pixel groups.
  • Claim 18: This claim details an imaging method. The method involves using a first A/D converter to convert the output of a red pixel into a first digital signal and the output of a blue pixel into a second digital signal. Concurrently, a second A/D converter converts the outputs of a first green pixel and a second green pixel into third and fourth digital signals, respectively. Lastly, a color interpolation circuit combines all four of these digital signals.

CAFC 2026 Dockets:
As of April 26, 2026, a direct search for "CAFC 2026 dockets US6838651" did not yield specific results indicating active cases involving US6838651 in the Court of Appeals for the Federal Circuit for the year 2026. The Google Patents information for US6838651 lists various past litigation, including PTAB cases (IPR2025-01019 filed but not instituted, and IPR2021-00437 and IPR2021-00557 which were settled) and District Court cases, but no explicit CAFC dockets for 2026 for this specific patent were found in the provided snippets. Given the patent's anticipated expiration date of March 28, 2022, it is less likely to be involved in new litigation in 2026, though appeals of earlier proceedings could theoretically still be active.

The following is a list of known litigation involving US patent 6838651:

• PTAB case IPR2025-01019

  • Plaintiff(s): OMNIVISION TECHNOLOGIES, INC.
  • Defendant(s): Not specified in the provided text, but it is an inter partes review challenging the patent.
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2025-01019
  • Filing Date: The effective date of filing was May 20, 2025.
  • Outcome/Status: Not Instituted - Procedural.

• PTAB case IPR2021-00437

  • Plaintiff(s): SAMSUNG ELECTRONICS CO., LTD., SAMSUNG ELECTRONICS AMERICA, INC., AND SAMSUNG SEMICONDUCTOR, INC.
  • Defendant(s): Not specified in the provided text, but it is an inter partes review challenging the patent.
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2021-00437
  • Filing Date: The effective date of filing was January 15, 2021.
  • Outcome/Status: Settlement.

• PTAB case IPR2021-00557

  • Plaintiff(s): SAMSUNG ELECTRONICS CO., LTD., SAMSUNG ELECTRONICS AMERICA, INC., AND SAMSUNG SEMICONDUCTOR, INC.
  • Defendant(s): Not specified in the provided text, but it is an inter partes review challenging the patent.
  • Jurisdiction: Patent Trial and Appeal Board (PTAB)
  • Case Number: IPR2021-00557
  • Filing Date: The effective date of filing was February 18, 2021.
  • Outcome/Status: Settlement.

• US case filed in Texas Eastern District Court (6:11-cv-00128)

  • Plaintiff(s): Not specified.
  • Defendant(s): Not specified.
  • Jurisdiction: Texas Eastern District Court.
  • Case Number: 6:11-cv-00128.
  • Filing Date: Not explicitly stated, but the case was filed in 2011 based on the case number.
  • Outcome/Status: Litigation.

• US case filed in Texas Eastern District Court (4:21-cv-00376)

  • Plaintiff(s): Not specified.
  • Defendant(s): Not specified.
  • Jurisdiction: Texas Eastern District Court.
  • Case Number: 4:21-cv-00376.
  • Filing Date: Not explicitly stated, but the case was filed in 2021 based on the case number.
  • Outcome/Status: Litigation.

• US case filed in Texas Eastern District Court (4:11-cv-00163)

  • Plaintiff(s): Not specified.
  • Defendant(s): Not specified.
  • Jurisdiction: Texas Eastern District Court.
  • Case Number: 4:11-cv-00163.
  • Filing Date: Not explicitly stated, but the case was filed in 2011 based on the case number.
  • Outcome/Status: Litigation.

• US case filed in International Trade Commission (337-TA-1231)

  • Plaintiff(s): Not specified.
  • Defendant(s): Not specified.
  • Jurisdiction: International Trade Commission.
  • Case Number: 337-TA-1231.
  • Filing Date: Not explicitly stated.
  • Outcome/Status: Litigation.

• US case filed in California Northern District Court (4:12-cv-01195)

  • Plaintiff(s): Not specified.
  • Defendant(s): Not specified.
  • Jurisdiction: California Northern District Court.
  • Case Number: 4:12-cv-01195.
  • Filing Date: Not explicitly stated, but the case was filed in 2012 based on the case number.
  • Outcome/Status: Litigation.

• US case filed in California Northern District Court (3:12-cv-04990)

  • Plaintiff(s): Not specified.
  • Defendant(s): Not specified.
  • Jurisdiction: California Northern District Court.
  • Case Number: 3:12-cv-04990.
  • Filing Date: Not explicitly stated, but the case was filed in 2012 based on the case number.
  • Outcome/Status: Litigation.

Proceedings overview

A single AIA trial proceeding has been filed against US patent 6838651. This proceeding resulted in institution being denied on discretionary grounds, meaning the patent's claims were not adjudicated on their merits. This provides a defensive posture where the patent's claims remain untested by this specific IPR.

IPR2025-01019 — OmniVision Technologies, Inc. v. Re Secured Networks, LLC

• Type: Inter Partes Review
• Filed: 2025-05-20
• Status: Discretionary Denial. Institution of the IPR was denied by the Acting USPTO Director.
• Judge panel: Acting USPTO Director Coke Morgan Stewart issued the decision.
• Petition grounds: The specific claims challenged and prior art grounds were not detailed in the publicly available information regarding the discretionary denial.
• Institution decision: Institution was denied on October 10, 2025 (Paper 14). The Acting Director denied institution based on "strong settled expectations," noting that the patent had been in force for seventeen years and expired three years prior to the petition filing. The Director also considered that the petitioner, OmniVision, had filed a declaratory judgment action three months earlier, which undermined its claim of not expecting enforcement, and found OmniVision's belief of being licensed "unsupported" by relevant settlement agreements.
• Final Written Decision: Not issued, as institution was denied.
• Settlement / termination: The proceeding was terminated by the denial of institution, rather than a settlement.
• Appeal: Not applicable, as institution was denied by the Director.
• Defensive value: The claims of US6838651 were not challenged on their merits in this proceeding due to the discretionary denial. This means the patent owner's claims remain untested by this specific IPR and this proceeding does not create estoppel for others under § 315(e)(2) for the asserted grounds.

Strategic summary

Only one AIA trial proceeding, IPR2025-01019, has been filed against US patent 6838651. In this proceeding, the PTAB's Acting Director denied institution on discretionary grounds, primarily citing the patent's expiration three years prior to the petition filing and the patent owner's "strong settled expectations." Consequently, no claims of US6838651 have been canceled or sustained through an IPR Final Written Decision; all claims remain untested by this IPR.

Regarding the estoppel landscape, since institution was denied on discretionary grounds, the petitioner (OmniVision Technologies, Inc.) and its privies are not estopped under 35 U.S.C. § 315(e)(2) from raising any grounds that were raised or reasonably could have been raised in the petition. This is because estoppel generally attaches only when a Final Written Decision is issued. The denial was procedural and did not reach the merits of patentability. Therefore, all prior-art grounds remain theoretically available to other potential challengers.

There is no discernible pattern of multiple IPRs filed by the same petitioner from the provided "PTAB proceedings on file." The patent owner, Re Secured Networks, LLC, successfully defended against institution in this instance, indicating a willingness to enforce its rights, even on an expired patent, and the Director acknowledged their "settled expectations."

Recommended next steps

For a defendant facing assertion of US6838651, it's important to understand that while IPR2025-01019 did not invalidate any claims, the discretionary denial was based on factors specific to that petitioner (OmniVision) and the patent's expired status. The reasoning from Acting USPTO Director Coke Morgan Stewart's decision on October 10, 2025 (Paper 14) is publicly summarized in articles discussing the decision. The decision hinged on "strong settled expectations" due to the patent's expiration well before the IPR petition and the petitioner's prior declaratory judgment action.

Given that the patent has expired (anticipated expiration was 2022-03-28, and the IPR was filed 2025-05-20), any assertion would likely be for past infringement. If facing assertion, consider:

• Reviewing the Director's Decision: Obtain and review Paper 14 for IPR2025-01019 from the USPTO PTAB E2E system to fully understand the nuanced reasoning behind the discretionary denial. This can inform whether similar discretionary arguments might apply in future scenarios or if the grounds were specific to OmniVision.
• Validity Analysis: Since the claims of US6838651 have not been tested on the merits in an AIA trial proceeding, a thorough independent validity analysis against the prior art is crucial. This would determine the strength of the patent claims independently of the IPR's procedural outcome.
• Settled Expectations: The Director's emphasis on "settled expectations" for an expired patent suggests a higher bar for instituting IPRs against such patents, but this does not preclude district court litigation or affect the underlying validity analysis of the claims.

Inventors

• Richard A. Mann (ESS Technology Inc)

Original assignee

The original assignee named on the issued patent US6838651B1 is ESS Technology Inc.. ESS Technology Inc. was primarily involved in the business of developing and marketing audio and video semiconductors. As of 2026, ESS Technology Inc. appears to be operating, though its focus may have shifted or its market presence changed since the patent's filing.

Assignment timeline

• 2002-03-28 (executed) / recorded 2002-03-28 — Reel 012769/0638

  • Conveyance: Assignment
  • Assignor: MANN, RICHARD A.
  • Assignee: CONEXANT SYSTEMS, INC., CALIFORNIA
  • Correspondent: Not specified in available data for this record.
  • Context: Inventor assigned patent rights to Conexant Systems, Inc.

• 2002-09-19 (executed) / recorded 2003-05-05 — Reel 014017/0459

  • Conveyance: Assignment
  • Assignor: CONEXANT SYSTEMS, INC.
  • Assignee: PICTOS TECHNOLOGIES, INC., CALIFORNIA
  • Correspondent: Not specified in available data for this record.
  • Context: Conexant Systems, Inc. assigned patent rights to Pictos Technologies, Inc.

• 2004-06-25 (executed) / recorded 2004-07-07 — Reel 015494/0513

  • Conveyance: Assignment
  • Assignor: PICTOS TECHNOLOGIES, INC.
  • Assignee: ESS TECHNOLOGIES INTERNATIONAL, INC., CALIFORNIA
  • Correspondent: Not specified in available data for this record.
  • Context: Pictos Technologies, Inc. assigned patent rights to ESS Technologies International, Inc.

• 2008-06-30 (executed) / recorded 2008-07-21 — Reel 021316/0252

  • Conveyance: Assignment
  • Assignor: ESS TECHNOLOGY, INC.
  • Assignee: IMPERIUM (IP) HOLDINGS, NEW YORK
  • Correspondent: Not specified in available data for this record.
  • Context: ESS Technology, Inc. assigned patent rights to Imperium (IP) Holdings.

• 2018-04-30 (executed) / recorded 2020-10-02 — Reel 053974/0766

  • Conveyance: Change of Name
  • Assignor: IMPERIUM IP HOLDINGS (CAYMAN), LTD.
  • Assignee: PICTOS TECHNOLOGIES INC., CALIFORNIA
  • Correspondent: Not specified in available data for this record.
  • Context: Imperium IP Holdings (Cayman), Ltd. changed its name to Pictos Technologies Inc.

• 2018-04-30 (executed) / recorded 2021-06-15 — Reel 056595/0208

  • Conveyance: Change of Name
  • Assignor: IMPERIUM IP HOLDINGS (CAYMAN), LTD.
  • Assignee: PICTOS TECHNOLOGIES INC., CALIFORNIA
  • Correspondent: Not specified in available data for this record.
  • Context: Imperium IP Holdings (Cayman), Ltd. changed its name to Pictos Technologies Inc. This appears to be a re-recording or duplicate of the previous change of name.

• 2022-07-06 (executed) / recorded 2022-07-21 — Reel 060801/0001

  • Conveyance: Assignment
  • Assignor: PICTOS TECHNOLOGIES INC
  • Assignee: RE SECURED NETWORKS LLC, TEXAS
  • Correspondent: Not specified in available data for this record.
  • Context: Pictos Technologies Inc. assigned patent rights to RE Secured Networks LLC.

Timeline diagram

timeline
    title Ownership of US 6838651
    2002 : Assigned to Conexant
    2003 : Assigned to Pictos Tech
    2004 : Assigned to ESS Tech Intl
    2005 : Issued
    2008 : Assigned to Imperium IP Holdings
    2020 : Imperium dba Pictos Technologies Inc
    2021 : Imperium dba Pictos Technologies Inc
    2022 : Assigned to RE Secured Networks LLC

NPE / troll-pattern signals

1. Shell-entity transfer — present.

   • 2008-06-30 (executed) / recorded 2008-07-21 — Reel 021316/0252: Assignment to IMPERIUM (IP) HOLDINGS, NEW YORK. The "IP Holdings" suffix is indicative of a licensing entity.
   • 2022-07-06 (executed) / recorded 2022-07-21 — Reel 060801/0001: Assignment to RE SECURED NETWORKS LLC, TEXAS. "LLC" and the generic name are common for shell entities.

2. Known asserter in the chain — present.

   • RE Secured Networks LLC is listed as a current assignee on Google Patents and has been associated with patent litigation, including PTAB cases. Unified Patents lists RE Secured Networks LLC as a known NPE, having filed multiple litigations in Texas Eastern District Court and International Trade Commission cases.
   • Imperium (IP) Holdings (which later became Pictos Technologies Inc.) has also been associated with patent assertion.

3. Repeat correspondent across the chain — unclear. Correspondent information was not available for the listed assignment records from the Google Patents legal events section. To definitively determine if a repeat correspondent is present, one would need to manually examine the reel/frame documents on the USPTO Assignment Center.

4. Cascading transfers — not present. While there are multiple transfers, they are spaced several years apart rather than in rapid succession (e.g., within 24 months).

5. Pre-litigation transfer — unclear. Without a precise date for the first infringement suit naming this patent, it's difficult to confirm this signal. However, Google Patents notes that "Family has litigation" and shows several US cases filed, with the earliest listed US case filed in Texas Eastern District Court having an unspecified filing date that predates the most recent assignment to RE Secured Networks LLC. More precise litigation dates would be needed to confirm if transfers occurred within 6 months of a suit.

6. Bankruptcy fire-sale — not present. No indication of bankruptcy proceedings for any assignor in the provided data.

7. Privateering — unclear. While the transfers to IP holding companies suggest a potential for assertion, there is no direct evidence in the provided data or legal events that an operating company explicitly transferred the patent for assertion against its competitors.

8. Defensive aggregator (anti-NPE) — not present. The chain does not end with a known defensive aggregator.

Verdict

NPE — high confidence. The presence of transfers to known NPEs such as RE Secured Networks LLC (current assignee) and Imperium (IP) Holdings (a prior assignee), both of which are identified by Unified Patents as entities involved in patent litigation, strongly indicates an NPE pattern. The use of "IP Holdings" in a prior assignee's name also points towards a licensing-focused entity. The current assignee, RE Secured Networks LLC, has been involved in multiple litigations, as indicated by the Unified Patents data linked on Google Patents.

Verification: USPTO Assignment Center Search for US6838651

To identify the most relevant prior art for US patent 6838651, I will examine the "Citations (4)" and "Patent Citations (4)" sections provided in the Google Patents data, which list the prior art patents cited against US6838651B1. The USPTO's Patent Public Search tool can be used to further investigate these citations, although the Google Patents page already provides the key information.

Here are the patent citations for US6838651 and their details:

Cited Prior Art References

1. US3971065A

   • Full Citation: US3971065A, "Color imaging array"
   • Publication Date: 1976-07-20
   • Priority Date: 1975-03-05
   • Assignee: Eastman Kodak Company
   • Brief Description: This patent describes a color imaging array, which is fundamental to capturing color images. It is likely cited for the general concept of using different color-sensitive elements (pixels) to form a color image, a foundational aspect of CMOS image sensors. The patent describes a repeating array of photosensitive elements with different color filters.
   • Potential Anticipated Claims (35 U.S.C. § 102): This reference would likely be considered for the broad concept of a solid-state imaging device comprising different color pixels (red, blue, green). Specifically, it could anticipate elements of claims 1 and 13 relating to the presence of red, blue, and green pixels in an imaging device.

2. US5461425A

   • Full Citation: US5461425A, "CMOS image sensor with pixel level A/D conversion"
   • Publication Date: 1995-10-24
   • Priority Date: 1994-02-15
   • Assignee: Stanford University
   • Brief Description: This patent describes a CMOS image sensor that includes analog-to-digital (A/D) conversion at the pixel level. This is highly relevant as US6838651 focuses on CMOS imagers with multiple A/D converters. The concept of integrating A/D conversion on-chip with CMOS imagers is a core feature of the present invention.
   • Potential Anticipated Claims (35 U.S.C. § 102): This patent directly addresses CMOS image sensors with A/D conversion, making it highly relevant to claims 1 and 13 which specify a solid-state imaging device with pixels and analog-to-digital converters. It could specifically anticipate the idea of converting pixel outputs into digital signals using A/D converters.

3. US6380880B1

   • Full Citation: US6380880B1, "Digital pixel sensor with integrated charge transfer amplifier"
   • Publication Date: 2002-04-30
   • Priority Date: 2001-03-30
   • Assignee: Pixim, Incorporated
   • Brief Description: This patent describes a digital pixel sensor with an integrated charge transfer amplifier. While US6838651 generally focuses on multiple A/D converters for high frame rates and snap-shot capability, this prior art could be relevant for its discussion of pixel-level processing and potentially the on-chip integration of components that contribute to signal conversion or amplification within an imaging device.
   • Potential Anticipated Claims (35 U.S.C. § 102): This reference might be considered for aspects related to digital pixel sensors and on-chip signal processing within the context of a solid-state imaging device, potentially impacting claims related to the overall architecture of converting pixel outputs into digital signals.

4. US6611289B1

   • Full Citation: US6611289B1, "Digital cameras using multiple sensors with multiple lenses"
   • Publication Date: 2003-08-26
   • Priority Date: 1999-01-15
   • Assignee: Yanbin Yu
   • Brief Description: This patent describes digital cameras that utilize multiple sensors and multiple lenses. While US6838651 focuses on multiple A/D converters within a single CMOS imager chip, this prior art demonstrates the concept of using multiple imaging components to achieve certain photographic results. The relevance here might be in the broader idea of using multiple components (even if different in nature) to improve image capture.
   • Potential Anticipated Claims (35 U.S.C. § 102): This reference is less directly anticipatory of the specific multiple A/D converter architecture of US6838651. However, it might be considered as general prior art for systems employing multiple sensing elements to achieve improved imaging, potentially in a broader interpretation of combining information from different sources, which is loosely related to the color interpolation aspect of claims 1 and 13.

Most Relevant Prior Art

Based on the descriptions, US5461425A ("CMOS image sensor with pixel level A/D conversion") appears to be the most relevant prior art. US6838651 specifically aims to address the shortcomings of conventional CMOS imagers and improve upon snapshot capability and frame rates through the use of multiple A/D converters. US5461425A directly addresses the integration of A/D conversion within a CMOS image sensor, which is a core technical area that US6838651 seeks to advance by proposing multiple A/D converters and specific allocation of color channels to these converters.

To analyze the obviousness of US patent 6838651 under 35 U.S.C. § 103, we need to consider whether the differences between the claimed invention and the prior art would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). The filing date of US6838651 is March 28, 2002.

A PHOSITA in the field of CMOS image sensors at that time would likely have a strong understanding of semiconductor device physics, analog and digital circuit design, image processing fundamentals, and color imaging techniques, including common color filter array patterns like the Bayer pattern. They would also be familiar with the challenges and advantages of both CCD and CMOS imaging technologies, particularly concerning noise reduction, power consumption, and frame rates.

The framework for determining obviousness involves:

1. Determining the scope and content of the prior art.
2. Ascertaining the differences between the claimed invention and the prior art.
3. Resolving the level of ordinary skill in the pertinent art.
4. Evaluating any secondary considerations of non-obviousness (though the examiner's initial burden is to establish a prima facie case without these).

Prior Art References for US6838651:

The Google Patents page for US6838651 lists the following citations as "Prior art" (which typically means cited by the examiner or third parties):

• US3971065A (Eastman Kodak Company) - Color imaging array: This patent, filed in 1975 and issued in 1976, discloses a color imaging array with luminance-sensitive elements (green) dominating and chrominance-sensitive elements (red and blue) interlaid in a repeating pattern. It mentions using filters selectively transmissive to red, green, and blue light for producing luminance and chrominance-sensitive elements. It specifically discusses "color image sensors" for "video cameras" and different patterns for color filters.
• US5461425A (Stanford University) - CMOS image sensor with pixel level A/D conversion: This patent, filed in 1994 and issued in 1995, is generally relevant to CMOS image sensors with A/D conversion at the pixel level.
• US6380880B1 (Pixim, Incorporated) - Digital pixel sensor with integrated charge transfer amplifier: This patent, filed in 2001 and issued in 2002, describes a digital pixel sensor with an integrated charge transfer amplifier.
• US6611289B1 (Yanbin Yu) - Digital cameras using multiple sensors with multiple lenses: This patent, filed in 1999 and issued in 2003, discusses digital cameras that utilize multiple sensors and multiple lenses.

Analysis of Obviousness under 35 U.S.C. § 103:

Claim 1: A solid state imaging device, comprising: a red pixel having an output; a blue pixel having an output; a first green pixel having an output; a second green pixel having an output; a first analog-to-digital converter connected to the output of the red pixel for converting the output of the red pixel into a first digital signal and connected to the output of the blue pixel for converting the output of the blue pixel into a second digital signal; a second analog-to-digital converter connected to the output of the first green pixel for converting the output of the first green pixel into a third digital signal and connected to the output of the second green pixel for converting the output of the second green pixel into a fourth digital signal; and a color interpolation circuit for combining the first, second, third and fourth digital signals.

Motivation to Combine and Obviousness:

A PHOSITA at the time of the invention (2002) would understand the advantages of CMOS image sensors, including lower power consumption, higher levels of system integration (camera-on-a-chip), and the ability to support very high data rates due to parallel operation, as explicitly stated in US6838651 itself. They would also be aware that CMOS image sensors can easily be equipped with on-chip A/D converters.

The core of Claim 1 involves:

1. A pixel array with red, blue, and two green pixels (consistent with a Bayer pattern, which is explicitly mentioned in US6838651 as the basis for defining a color image).
2. Multiple A/D converters.
3. Specific allocation of pixel outputs to A/D converters (one A/D for red and blue, a second for the two greens).
4. A color interpolation circuit.

Combination of US3971065A and US5461425A to render Claim 1 obvious:

• US3971065A discloses a color imaging array using red, green, and blue filters, with luminance (green) elements dominating and chrominance (red and blue) elements interlaid in a repeating pattern. This directly teaches the pixel array structure of red, blue, first green, and second green pixels, as these are the components of a Bayer pattern for color image capture. The concept of individual pixels providing output signals proportional to incident light is fundamental to imaging devices.
• US5461425A teaches a CMOS image sensor with pixel-level A/D conversion. While it might not explicitly show two A/D converters specifically assigned to R/B and G/G channels, it establishes the concept of integrating A/D conversion within a CMOS image sensor architecture. A PHOSITA, recognizing the goal of achieving high frame rates and improved noise performance in CMOS sensors (as acknowledged in the background of US6838651), would be motivated to utilize multiple A/D converters to process the color information in parallel. The patent itself notes that "CMOS solid-state image sensors utilize multiple amplifiers that allow a longer settling time between applications and higher frame rate while maintaining excellent noise rejection" and "CMOS solid-state image sensors may easily be equipped with a precision analog-to-digital (“A/D”) converter on the solid-state image sensor chip". Furthermore, the patent describes that "two A/D converters may be employed, where one A/D converter is used for the red and blue channels and the second A/D converter is used for the green channels. In this manner, there is no addition to the fixed pattern noise of the imager that would arise from mismatch or offset in the two A/D converters."

A PHOSITA would find it an obvious design choice to group the red and blue pixel outputs to one A/D converter and the green pixel outputs to another, especially given the desire to process color channels independently for gain and offset adjustments (as mentioned in US6838651's summary) and to manage data rates. The patent explicitly states this as an alternative to using a separate A/D for each color channel.

The inclusion of a "color interpolation circuit for combining the first, second, third and fourth digital signals" would also be obvious to a PHOSITA. As stated in US6838651, "Color interpolation is used to determine the amount of red, green and blue light incident on each pixel. This process averages the color outputs of appropriate neighboring pixels to approximate each pixel's unknown color data." This is a standard image processing technique for demosaicing Bayer pattern images, well-known in the art at the time of the invention (US6330029B1, for example, discusses CFA patterns and the necessity to interpolate values).

Therefore, the combination of US3971065A (for the pixel array and color filtering) and US5461425A (for on-chip CMOS A/D conversion) would have made Claim 1 obvious. The motivation would be to create a higher performance CMOS image sensor capable of processing color information efficiently, with multiple A/D converters handling the data from different color channels, a recognized advantage of CMOS technology.

Claim 13: A solid state imaging device, comprising: groups of pixels, wherein each of said groups of pixels include: a red pixel having an output; a blue pixel having an output; a first green pixel having an output; and a second green pixel having an output; a first analog-to-digital converter connected to the output of the red pixel for converting the output of the red pixels into a first digital signal and connected to the output of the blue pixel for converting the output of the blue pixels into a second digital signal; a second analog-to-digital converter connected to the output of the first green pixel for converting the output of the first green pixels into a third digital signal and connected to the output of the second green pixel for converting the output of the second green pixels into a fourth digital signal; and a color interpolation circuit for combining the first, second, third and fourth digital signals.

This claim differs from Claim 1 primarily in emphasizing "groups of pixels" and the A/D converters being connected to the "outputs of the red pixels" (plural), "blue pixels" (plural), etc. This merely describes an array of the pixel groups defined in Claim 1. The obviousness arguments for Claim 1 apply directly to Claim 13, as the concept of an array of color pixels (as taught by US3971065A) combined with multiple A/D converters for processing different color channels (as motivated by the advantages of CMOS technology and the teachings of US5461425A) would be readily apparent to a PHOSITA. The generalization from individual pixels to "groups of pixels" in an array, where each group has the specified color components, is a straightforward scaling of the concept, especially when considering "solid-state image sensors" which are inherently arrays of light-detecting elements.

Claim 18: An imaging method comprising: converting an output of a red pixel into a first digital signal using a first analog-to-digital converter; converting an output of a blue pixel into a second digital signal using the first analog-to-digital converter; converting an output of a first green pixel into a third digital signal using a second analog-to-digital converter; converting an output of a second green pixel into a fourth digital signal using the second analog-to-digital converter; and combining the first, second, third and fourth digital signals using a color interpolation circuit.

This claim describes the method corresponding to the device of Claim 1. The obviousness of the method follows directly from the obviousness of the device. If the device described in Claim 1 is obvious based on the combination of prior art references, then the method of operating that device in the manner described would also be obvious to a PHOSITA. Converting analog pixel outputs to digital signals using A/D converters is a fundamental operation in digital imaging, and distributing these conversions across multiple A/D converters for different color channels is a logical design choice for improving performance, as previously discussed. The subsequent color interpolation is also a well-known process in digital color imaging.

Conclusion on Obviousness:

A prima facie case of obviousness can be established for the independent claims of US6838651 by combining the teachings of US3971065A and US5461425A.

• Motivation to Combine: A person of ordinary skill in the art would have been motivated to combine the color filter array technology of US3971065A (which defines the pixel arrangement for red, blue, and two greens) with the on-chip CMOS A/D conversion technology of US546145A. The motivation stems from the recognized advantages of CMOS imagers over CCDs in terms of power consumption, integration, and data rates, particularly the ability to employ multiple A/D converters for higher frame rates and improved noise performance, as explicitly stated in the background and summary of US6838651. The specific allocation of R/B to one A/D and G/G to another is a logical step for independent channel processing and managing data throughput in a CMOS sensor. The use of color interpolation is a well-established technique for reconstructing full-color images from such arrays.

The combination of these references addresses the problem of achieving high frame rates and improved sensitivity in CMOS imagers by efficiently converting and processing color pixel data.

To provide a comprehensive analysis of US patent 6838651 regarding patent term adjustments (PTA), patent term extensions (PTE), continuation applications, divisional applications, related family members, and the projected expiration date, I would typically access the Public Patent Application Information Retrieval (PAIR) system or Patent Center on the USPTO website. However, direct access to these restricted databases is beyond my current capabilities.

Therefore, I will detail what can be inferred from the provided patent text and general knowledge of patent law, along with any relevant search results.

Patent Term Adjustments (PTA)

Patent Term Adjustment (PTA) compensates for delays caused by the USPTO during the prosecution of a patent application. These delays can include failing to issue an office action within 14 months, failing to respond to an applicant's reply within four months, or failing to issue a patent within three years of the filing date. The PTA calculation is typically provided with the Issue Notification Letter and indicated on the face of the patent.

The provided patent text for US6838651 does not explicitly state any PTA awarded. To determine the exact PTA, if any, the official patent document from the USPTO would need to be reviewed.

Patent Term Extensions (PTE)

Patent Term Extensions (PTE) are granted for patents claiming certain products (e.g., human drugs, medical devices) to compensate for time lost during regulatory review by agencies like the FDA.

Based on the title "High sensitivity snap shot CMOS image sensor" and the technical field described (solid-state imaging devices, CMOS imagers), US6838651 is highly unlikely to be eligible for a Patent Term Extension under 35 U.S.C. § 156, as it does not appear to relate to products requiring premarket regulatory approval.

Continuation and Divisional Applications

• Continuation applications: A continuation application is a second application for the same invention claimed in a prior non-provisional application and filed before the patenting or abandonment of the prior application.
• Divisional applications: A divisional application is a later application for a distinct invention carved out of an earlier, broader patent application.

The provided Google Patents information for US6838651 lists "Priority Applications (1)" and "Applications Claiming Priority (1)" both referring to "US10/113,545" with a priority date and filing date of March 28, 2002. This indicates that US6838651 (patent number) directly resulted from application number US10/113,545. The provided text does not mention any continuation or divisional applications filed from US6838651.

Related Family Members

The "Family Applications" section in Google Patents lists only "US10/113,545" which is the application for US6838651. Therefore, based on the provided information, there are no other direct related family members (e.g., continuations, divisionals, or continuations-in-part) explicitly listed as having originated from this specific patent application itself. However, it's important to note that a full patent family search would involve checking for all patents that claim priority from the same initial application or that share common inventorship and subject matter.

Projected Expiration Date

For utility patents filed on or after June 8, 1995, the patent term generally lasts 20 years from the earliest filing date of the application or its earliest priority application under 35 U.S.C. §§ 120, 121, or 365(c), subject to any PTA or PTE.

• Filing Date: March 28, 2002
• Base Expiration Date (20 years from filing): March 28, 2022

The Google Patents information for US6838651 explicitly states its legal status as "Expired - Lifetime" and lists an "Anticipated expiration" date of March 28, 2022. This aligns with the 20-year term from its filing date (March 28, 2002), indicating that no significant Patent Term Adjustments or Patent Term Extensions were granted or applied, or if they were, they did not extend the term beyond the anticipated expiration.

Given that today's date is April 26, 2026, and the patent expired on March 28, 2022, the patent is no longer in force.

Defensive Disclosure: Advanced CMOS Image Sensor Architectures and Methodologies

Publication Date: 2026-05-15

Purpose: This defensive disclosure aims to broaden the scope of publicly available prior art concerning high-sensitivity, snap-shot capable CMOS image sensors, building upon the foundational concepts described in US Patent 6,838,651. The objective is to articulate derivative inventions and advanced implementations that render future incremental improvements in this technological domain non-novel or obvious to a person having ordinary skill in the art, thereby preventing proprietary claims on such advancements. This document explores variations across material science, operational parameters, cross-domain applications, integration with emerging technologies, and failure modes.

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Derivatives for Claim 1: Solid State Imaging Device with Two A/D Converters and Color Interpolation

Claim 1: A solid state imaging device, comprising: a red pixel having an output; a blue pixel having an output; a first green pixel having an output; a second green pixel having an output; a first analog-to-digital converter connected to the output of the red pixel for converting the output of the red pixel into a first digital signal and connected to the output of the blue pixel for converting the output of the blue pixel into a second digital signal; a second analog-to-digital converter connected to the output of the first green pixel for converting the output of the first green pixel into a third digital signal and connected to the output of the second green pixel for converting the output of the second green pixel into a fourth digital signal; and a color interpolation circuit for combining the first, second, third and fourth digital signals.

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1.1. Material & Component Substitution: Quantum Dot Photodetectors with Integrated Time-Domain A/D Converters

Enabling Description: The conventional silicon photodiodes are substituted with an array of spectrally-tunable colloidal quantum dot (QD) photodetectors. Each QD photodetector, sized for individual pixel sites (e.g., 2µm pitch), is configured to exhibit peak responsivity in the red, blue, or green spectral bands, eliminating the need for traditional organic dye color filters. The analog-to-digital conversion is performed by a dedicated time-domain single-slope or ramp-integrating ADC co-located with each pixel. For red and blue pixels, their respective time-domain digital outputs are aggregated into a higher-resolution serial bitstream by a first column-parallel digital aggregation unit which acts as the 'first analog-to-digital converter' equivalent. Similarly, the first and second green pixels feed into a second column-parallel digital aggregation unit. The color interpolation circuit then processes these aggregated, time-domain encoded digital signals, performing noise reduction and spatial averaging as part of the reconstruction. This approach leverages the high quantum efficiency and bandgap tunability of QDs while distributing ADC functionality closer to the pixel for enhanced readout speed and reduced analog noise pathways.

graph TD
    QD_R[Quantum Dot Red Pixel] --> TD_ADC_R[Time-Domain ADC R]
    QD_B[Quantum Dot Blue Pixel] --> TD_ADC_B[Time-Domain ADC B]
    QD_G1[Quantum Dot Green Pixel 1] --> TD_ADC_G1[Time-Domain ADC G1]
    QD_G2[Quantum Dot Green Pixel 2] --> TD_ADC_G2[Time-Domain ADC G2]

    TD_ADC_R --> D_AGGR1[Digital Aggregation Unit 1 (First ADC)]
    TD_ADC_B --> D_AGGR1
    D_AGGR1 -- First Digital Signal (R) --> CIC[Color Interpolation Circuit]
    D_AGGR1 -- Second Digital Signal (B) --> CIC

    TD_ADC_G1 --> D_AGGR2[Digital Aggregation Unit 2 (Second ADC)]
    TD_ADC_G2 --> D_AGGR2
    D_AGGR2 -- Third Digital Signal (G1) --> CIC
    D_AGGR2 -- Fourth Digital Signal (G2) --> CIC

    CIC -- Combined Digital Image --> Output

1.2. Material & Component Substitution: Organic Photodiodes with Hybrid Analog-Digital Converters

Enabling Description: The photosensitive elements are realized using organic photodiodes (OPDs) fabricated on a flexible substrate, offering improved light absorption across a broad spectrum and potential for ultra-thin form factors. The "first analog-to-digital converter" is a hybrid successive approximation register (SAR) ADC array, where the analog input stage for red and blue pixels utilizes charge-transfer amplifiers constructed from organic thin-film transistors (OTFTs) integrated directly onto the flexible substrate. The "second analog-to-digital converter" is a similar OTFT-based SAR ADC array for the first and second green pixels. The color interpolation circuit, potentially implemented on a separate rigid silicon die for computational density, receives the parallel digital outputs from these hybrid converters. The use of OPDs and OTFTs allows for large-area, low-cost, and conformable image sensors, enabling applications where traditional silicon-based sensors are impractical.

graph TD
    OPD_R[Organic Red Pixel] --> OTFT_CTA_R[OTFT Charge-Transfer Amp R]
    OPD_B[Organic Blue Pixel] --> OTFT_CTA_B[OTFT Charge-Transfer Amp B]
    OPD_G1[Organic Green Pixel 1] --> OTFT_CTA_G1[OTFT Charge-Transfer Amp G1]
    OPD_G2[Organic Green Pixel 2] --> OTFT_CTA_G2[OTFT Charge-Transfer Amp G2]

    OTFT_CTA_R --> SAR_ADC1[Hybrid SAR ADC Array 1 (First ADC)]
    OTFT_CTA_B --> SAR_ADC1
    SAR_ADC1 -- First Digital Signal (R) --> CIC[Color Interpolation Circuit]
    SAR_ADC1 -- Second Digital Signal (B) --> CIC

    OTFT_CTA_G1 --> SAR_ADC2[Hybrid SAR ADC Array 2 (Second ADC)]
    OTFT_CTA_G2 --> SAR_ADC2
    SAR_ADC2 -- Third Digital Signal (G1) --> CIC
    SAR_ADC2 -- Fourth Digital Signal (G2) --> CIC

    CIC -- Combined Digital Image --> Output

1.3. Operational Parameter Expansion: Terahertz Imaging with Ultra-High-Speed A/D Conversion

Enabling Description: The solid-state imaging device is adapted for Terahertz (THz) radiation detection by replacing conventional photodetectors with plasmon-resonant antenna-coupled field-effect transistors (TeraFETs) that are sensitive to THz frequencies. Each TeraFET acts as a pixel outputting an analog signal proportional to the incident THz power within its specific sub-band (e.g., three distinct bands replacing RGB, plus a fourth for differential sensing). To handle the extremely high data rates inherent in THz time-domain spectroscopy or fast THz imaging, the first and second analog-to-digital converters are implemented as interleaved 10 GSPS (Giga-Samples Per Second) pipeline ADCs. These ADCs, operating at an effective sampling rate of 40 GHz when interleaved, directly convert the high-bandwidth analog THz pixel signals. The color interpolation circuit is replaced by a spectral reconstruction algorithm that combines the multiple THz band digital signals to generate a composite THz image, enabling applications like non-destructive testing, security screening, and medical diagnostics with sub-millimeter resolution.

graph TD
    THz_P1[THz Pixel 1 (Band 1)] --> PL_ADC1[Interleaved Pipeline ADC 1 (10GSPS)]
    THz_P2[THz Pixel 2 (Band 2)] --> PL_ADC1
    THz_P3[THz Pixel 3 (Band 3)] --> PL_ADC2[Interleaved Pipeline ADC 2 (10GSPS)]
    THz_P4[THz Pixel 4 (Band 4)] --> PL_ADC2

    PL_ADC1 -- Digital Signals (Band 1, 2) --> SRA[Spectral Reconstruction Algorithm]
    PL_ADC2 -- Digital Signals (Band 3, 4) --> SRA

    SRA -- Composite THz Image --> Output

1.4. Operational Parameter Expansion: Deep-Sea Bioluminescence Detection at Micro-Lux Levels

Enabling Description: The solid-state imaging device is optimized for extreme low-light-level imaging, specifically for detecting faint bioluminescence in deep-sea environments. The pixels are enhanced with back-illuminated electron-multiplying CMOS (EM-CMOS) technology, providing on-chip gain to detect single photons. The red, blue, and green filters are chosen for spectral sensitivity matched to common bioluminescent wavelengths (e.g., blue-green emission). The first and second analog-to-digital converters are high-resolution (e.g., 16-bit), low-noise delta-sigma ADCs, designed for maximum dynamic range and minimal quantization noise at very low signal levels. These ADCs are operated at an extended integration time (e.g., several seconds) to accumulate sufficient photocharge. The "color interpolation circuit" performs advanced noise filtering, background subtraction, and temporal integration over multiple frames to resolve extremely dim bioluminescent events, mapping spectral information into pseudo-color outputs. The entire system is encased in a pressure-resistant, temperature-stabilized housing for operation at extreme oceanic depths.

graph TD
    EM_R[EM-CMOS Red Pixel] --> DS_ADC1[Delta-Sigma ADC 1 (16-bit)]
    EM_B[EM-CMOS Blue Pixel] --> DS_ADC1
    EM_G1[EM-CMOS Green Pixel 1] --> DS_ADC2[Delta-Sigma ADC 2 (16-bit)]
    EM_G2[EM-CMOS Green Pixel 2] --> DS_ADC2

    DS_ADC1 -- Digital Signals (R, B) --> CI_LF[Color Interpolation & Low-Light Filter]
    DS_ADC2 -- Digital Signals (G1, G2) --> CI_LF

    CI_LF -- Bioluminescence Image --> Output

1.5. Cross-Domain Application: Industrial Quality Control for Pharmaceutical Inspection

Enabling Description: This solid-state imaging device is adapted for high-throughput pharmaceutical inspection, specifically for detecting subtle color variations and particulate contamination in clear liquid solutions within vials. The pixel array uses narrow-band optical filters, including a red-shifted band for specific impurity detection, a blue-shifted band for clarity assessment, and two green bands for general solution color analysis. The first ADC is dedicated to the red-shifted and one green-band pixel outputs, while the second ADC handles the blue-shifted and the other green-band pixel outputs. Both ADCs are high-speed (e.g., 500 MSPS) pipelined converters to enable inspection of hundreds of vials per second on an automated conveyor. The color interpolation circuit is replaced by a defect classification engine, optimized with machine learning algorithms, to compare the acquired spectral signatures against reference standards, identify anomalies, and trigger rejection mechanisms for non-conforming products.

graph TD
    R_P[Red-Shifted Pixel] --> ADC_Pharm1[500MSPS Pipeline ADC 1]
    G1_P[Green Pixel 1] --> ADC_Pharm1
    B_P[Blue-Shifted Pixel] --> ADC_Pharm2[500MSPS Pipeline ADC 2]
    G2_P[Green Pixel 2] --> ADC_Pharm2

    ADC_Pharm1 -- Digital Signals (R, G1) --> DCE[Defect Classification Engine]
    ADC_Pharm2 -- Digital Signals (B, G2) --> DCE

    DCE -- Defect Analysis --> RejectionMechanism[Reject / Pass Decision]

1.6. Cross-Domain Application: Agricultural Crop Health Monitoring via Drone-Mounted Hyperspectral Imager

Enabling Description: The imaging device is integrated into a drone-based system for precise agricultural crop health monitoring. Instead of visible RGB, the "red pixel" is an infrared (IR) sensitive detector (e.g., 800-900nm), the "blue pixel" is a near-infrared (NIR) detector (e.g., 700-800nm), and the two "green pixels" are distinct narrow-band visible green (e.g., 550nm) and red-edge (e.g., 680nm) detectors. This configuration allows for calculating vegetation indices like NDVI (Normalized Difference Vegetation Index) and other spectral indicators of plant stress. The first A/D converter processes the IR and NIR signals, while the second A/D converter processes the green and red-edge signals. The "color interpolation circuit" is adapted to be a spectral index calculation unit, generating real-time maps of crop vigor, disease presence, or water stress by combining the digital outputs. This data can then be used for targeted fertilization or irrigation.

graph TD
    IR_P[IR Pixel (800-900nm)] --> ADC_Ag1[ADC for Ag Monitoring 1]
    NIR_P[NIR Pixel (700-800nm)] --> ADC_Ag1
    G_P[Green Pixel (550nm)] --> ADC_Ag2[ADC for Ag Monitoring 2]
    RE_P[Red-Edge Pixel (680nm)] --> ADC_Ag2

    ADC_Ag1 -- Digital Signals (IR, NIR) --> SICU[Spectral Index Calculation Unit]
    ADC_Ag2 -- Digital Signals (G, RE) --> SICU

    SICU -- Crop Health Map --> DroneTelemetry[Drone Telemetry & Action]

1.7. Cross-Domain Application: Ophthalmic Imaging for Retinal Vasculature Analysis

Enabling Description: This imaging device is tailored for non-invasive ophthalmic examination, specifically for detailed imaging of the retinal vasculature. The pixels are sensitive to different optical coherence tomography (OCT) wavelengths. A "red pixel" is a long-wavelength OCT channel, a "blue pixel" is a short-wavelength OCT channel, and the two "green pixels" are intermediate-wavelength OCT channels, all designed to penetrate different retinal layers. These channels capture depth-resolved interference patterns. The first A/D converter is optimized for the long and short OCT channels, performing high-speed complex signal digitization. The second A/D converter processes the two intermediate OCT channels. The "color interpolation circuit" is augmented with a volumetric reconstruction algorithm that combines the digital interferometric signals from all four channels to generate a 3D structural image of the retina, highlighting blood vessel density and abnormalities without the use of dyes.

graph TD
    OCT_LW[OCT Pixel (Long Wavelength)] --> ADC_OPH1[ADC for Ophthalmic Img 1]
    OCT_SW[OCT Pixel (Short Wavelength)] --> ADC_OPH1
    OCT_IW1[OCT Pixel (Int. Wavelength 1)] --> ADC_OPH2[ADC for Ophthalmic Img 2]
    OCT_IW2[OCT Pixel (Int. Wavelength 2)] --> ADC_OPH2

    ADC_OPH1 -- Digital Interferometric Signals --> VRA[Volumetric Reconstruction Algorithm]
    ADC_OPH2 -- Digital Interferometric Signals --> VRA

    VRA -- 3D Retinal Image --> DiagnosticSystem[Ophthalmic Diagnostic System]

1.8. Integration with Emerging Tech: AI-Optimized Adaptive A/D Conversion

Enabling Description: The solid-state imaging device incorporates an embedded Artificial Intelligence (AI) co-processor directly on-chip. This AI unit dynamically optimizes the operating parameters of the first and second analog-to-digital converters based on real-time scene analysis and user-defined imaging goals. For instance, if the AI detects a high-contrast scene, it might instruct the ADCs to operate in a high-bit-depth, slower sampling mode for enhanced dynamic range. Conversely, for fast-moving subjects or low-light conditions, the AI could prioritize higher sampling rates or activate specific noise reduction techniques within the ADC. The "color interpolation circuit" is also AI-driven, employing deep learning models for advanced demosaicing, superior noise suppression, and intelligent color rendition that adapts to lighting conditions and object recognition. The AI receives raw digital signals from the ADCs and provides feedback loops to optimize their performance.

graph TD
    R_P[Red Pixel] --> ADC1[First ADC]
    B_P[Blue Pixel] --> ADC1
    G1_P[First Green Pixel] --> ADC2[Second ADC]
    G2_P[Second Green Pixel] --> ADC2

    ADC1 -- Digital Signals --> AI_COPROC[AI Co-processor (on-chip)]
    ADC2 -- Digital Signals --> AI_COPROC

    AI_COPROC -- Optimized Parameters --> ADC1
    AI_COPROC -- Optimized Parameters --> ADC2
    AI_COPROC -- AI-Enhanced Combined Signals --> CIC[Color Interpolation Circuit]
    
    CIC -- Final Image --> Output

1.9. Integration with Emerging Tech: IoT-Enabled Remote Sensing with Edge Processing and Federated Learning

Enabling Description: The imaging device is part of an Internet of Things (IoT) node for remote environmental monitoring. Each imaging device is equipped with integrated low-power wireless communication (e.g., LoRaWAN, NB-IoT) and an on-chip edge processing unit. The first and second analog-to-digital converters are designed for ultra-low power consumption and variable duty cycles, only activating to capture data when triggered by external events (e.g., motion sensor, scheduled interval) or local environmental changes. The "color interpolation circuit" is partially offloaded to the edge processing unit, which performs initial color reconstruction and feature extraction (e.g., presence of specific plant species, animal movement). This edge-processed data, rather than raw images, is then transmitted wirelessly. Furthermore, the IoT network supports federated learning, where multiple such imaging nodes collaboratively train a central AI model for object classification or environmental anomaly detection without transmitting sensitive raw image data.

graph TD
    PixelArray[Pixel Array (R, B, G1, G2)] --> ADC1[First ADC (Low Power)]
    PixelArray --> ADC2[Second ADC (Low Power)]

    ADC1 -- Digital Signals --> Edge_Proc[On-Chip Edge Processing Unit]
    ADC2 -- Digital Signals --> Edge_Proc

    Edge_Proc -- Features/Metadata --> WirelessComm[LoRaWAN/NB-IoT Communication]
    WirelessComm -- Transmit --> CloudServer[Cloud Server (Federated Learning)]
    Edge_Proc -- Partial Interpolation --> ColorInterpolation[Color Interpolation Circuit]
    ColorInterpolation -- Local Output --> Display

    Trigger[External/Scheduled Trigger] --> Edge_Proc

1.10. The "Inverse" or Failure Mode: Graceful Degradation and Low-Power Diagnostic Mode

Enabling Description: The solid-state imaging device incorporates fault detection and a "low-power diagnostic mode" for graceful degradation in the event of component failure. Each pixel includes built-in self-test (BIST) circuitry to detect photodiode degradation or leakage. The first and second analog-to-digital converters feature redundant sub-units or operate in a reconfigurable manner. Upon detecting a failure in, for example, the blue pixel's path or a sub-unit of the first ADC, the control logic automatically shifts the blue pixel's output to be processed by the second ADC's available capacity, or it deactivates the failed path entirely. In "low-power diagnostic mode," only a subset of green pixels (e.g., 10%) are sampled by a single, lowest-power ADC, effectively reducing the output to a low-resolution monochrome image or a diagnostic pattern, while the remaining ADCs and pixel circuits are powered down. This mode is activated during standby or when critical system power is low, providing basic environmental awareness or diagnostic feedback with minimal energy consumption.

stateDiagram
    state NormalOperation {
        [*] --> Active
        Active --> FaultDetected : Pixel/ADC Failure
    }

    state FaultDetected {
        FaultDetected --> GracefulDegradation : Reconfigure/Redundancy
        GracefulDegradation --> DiagnosticMode : Critical Failure/Low Power
    }

    state GracefulDegradation {
        state "Partial Functionality" {
            [*] --> ReconfiguredADC : Blue to ADC2
            ReconfiguredADC --> ImageOutput : Reduced Quality Image
        }
        GracefulDegradation --> DiagnosticMode : User/Power Initiated
    }

    state DiagnosticMode {
        state "Low Power Monochrome" {
            [*] --> SubsampledGreen : Single ADC
            SubsampledGreen --> DiagnosticOutput : Low Res/Monochrome
        }
        DiagnosticMode --> Active : Fault Cleared/Power Restored
    }

---

Derivatives for Claim 13: Solid State Imaging Device with Groups of Pixels and Two A/D Converters

Claim 13: A solid state imaging device, comprising: groups of pixels, wherein each of said groups of pixels include: a red pixel having an output; a blue pixel having an output; a first green pixel having an output; and a second green pixel having an output; a first analog-to-digital converter connected to the output of the red pixel for converting the output of the red pixels into a first digital signal and connected to the output of the blue pixel for converting the output of the blue pixels into a second digital signal; a second analog-to-digital converter connected to the output of the first green pixel for converting the output of the first green pixels into a third digital signal and connected to the output of the second green pixel for converting the output of the second green pixels into a fourth digital signal; and a color interpolation circuit for combining the first, second, third and fourth digital signals.

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2.1. Material & Component Substitution: Plasmonic Color Filters and 3D-Stacked A/D Converter Array

Enabling Description: The "groups of pixels" are fabricated with integrated plasmonic nanostructures serving as spectrally selective color filters, eliminating the need for traditional organic color filter arrays and allowing for smaller pixel pitches and higher fill factors. Each pixel's photodetector is a high-speed silicon avalanche photodiode (SiAPD). The entire pixel array is 3D-stacked with a separate wafer containing the "first analog-to-digital converter" and "second analog-to-digital converter." This lower wafer comprises a dense array of column-parallel SAR ADCs, with dedicated ADCs for all red pixels and all blue pixels mapped to the first ADC layer, and similarly for the green pixels to the second ADC layer. This 3D integration minimizes interconnect length, reduces noise, and allows for extremely high-density, high-speed parallel conversion of the outputs from the "red pixels," "blue pixels," "first green pixels," and "second green pixels" into their respective digital signals. The color interpolation circuit is also on-chip, potentially within the 3D stack.

graph TD
    PF_R[Plasmonic Filter Red Pixels Array] --> SiAPD_R[SiAPD Array Red]
    PF_B[Plasmonic Filter Blue Pixels Array] --> SiAPD_B[SiAPD Array Blue]
    PF_G1[Plasmonic Filter G1 Pixels Array] --> SiAPD_G1[SiAPD Array G1]
    PF_G2[Plasmonic Filter G2 Pixels Array] --> SiAPD_G2[SiAPD Array G2]

    SiAPD_R & SiAPD_B --> A_ADC1[3D-Stacked ADC Layer 1 (First ADC - R & B)]
    SiAPD_G1 & SiAPD_G2 --> A_ADC2[3D-Stacked ADC Layer 2 (Second ADC - G1 & G2)]

    A_ADC1 -- Digital R/B Signals --> CIC[Color Interpolation Circuit (on-chip)]
    A_ADC2 -- Digital G1/G2 Signals --> CIC

    CIC -- Combined Digital Image --> Output

2.2. Material & Component Substitution: Graphene Photodetector Arrays with Cryogenic A/D Converters

Enabling Description: The "groups of pixels" utilize arrays of broadband graphene photodetectors, offering ultra-fast response times and sensitivity across a wide electromagnetic spectrum. For high-performance imaging in scientific applications (e.g., astronomy, quantum computing integration), these detectors operate at cryogenic temperatures (e.g., 4 Kelvin). The "first analog-to-digital converter" and "second analog-to-digital converter" are implemented as superconducting quantum interference device (SQUID) based ADCs, operating directly at cryogenic temperatures. These SQUID ADCs offer extremely low noise and high speed, converting the minute analog photo-currents from the graphene pixels into digital signals with high precision. The "color interpolation circuit" (or spectral reconstruction unit, given graphene's broadband nature) is then integrated either cryogenically or via buffered interfaces to warmer digital processing, combining the digital outputs from the various "red pixels" (e.g., filtered for a specific band via external means), "blue pixels," and "green pixels" to form a high-fidelity image.

graph TD
    GP_R[Graphene Pixel Array R] --> CRYO_ADC1[Cryogenic SQUID ADC 1]
    GP_B[Graphene Pixel Array B] --> CRYO_ADC1
    GP_G1[Graphene Pixel Array G1] --> CRYO_ADC2[Cryogenic SQUID ADC 2]
    GP_G2[Graphene Pixel Array G2] --> CRYO_ADC2

    CRYO_ADC1 -- Digital R/B Signals --> CIC[Color Interpolation Circuit (Cryogenic or Buffered)]
    CRYO_ADC2 -- Digital G1/G2 Signals --> CIC

    CIC -- Combined Image --> Output

2.3. Operational Parameter Expansion: High-Radiation Environment Surveillance with Hardened A/D Converters

Enabling Description: This solid-state imaging device is designed for surveillance and monitoring within high-radiation environments, such as nuclear facilities or space exploration vehicles. The "groups of pixels" employ radiation-hardened (rad-hard) silicon-on-insulator (SOI) photodiodes, featuring enhanced resistance to total ionizing dose (TID) and single-event effects (SEE). The "first analog-to-digital converter" and "second analog-to-digital converter" are similarly implemented using rad-hard CMOS processes, incorporating triple-module redundancy (TMR) in critical logic paths and error-correcting codes (ECC) in their digital outputs. These ADCs are designed to maintain accuracy and functionality even after significant radiation exposure, converting the outputs from the rad-hard pixels into digital signals. The "color interpolation circuit" also integrates ECC decoding and advanced image reconstruction algorithms that compensate for radiation-induced fixed-pattern noise or temporary pixel defects, providing reliable imagery despite the harsh operating conditions.

graph TD
    RadHard_R[Rad-Hard R Pixel Groups] --> RH_ADC1[Rad-Hard ADC 1 (TMR/ECC)]
    RadHard_B[Rad-Hard B Pixel Groups] --> RH_ADC1
    RadHard_G1[Rad-Hard G1 Pixel Groups] --> RH_ADC2[Rad-Hard ADC 2 (TMR/ECC)]
    RadHard_G2[Rad-Hard G2 Pixel Groups] --> RH_ADC2

    RH_ADC1 -- Digital R/B Signals (with ECC) --> RH_CIC[Rad-Hard Color Interpolation Circuit]
    RH_ADC2 -- Digital G1/G2 Signals (with ECC) --> RH_CIC

    RH_CIC -- Corrected Image --> Output

2.4. Operational Parameter Expansion: Distributed Sensor Network for Global Climate Modeling with Ultra-Low Power ADCs

Enabling Description: The solid-state imaging device forms part of a distributed sensor network, with numerous individual imagers deployed globally for long-term climate modeling and environmental data collection. Each imager within the "groups of pixels" utilizes an ultra-low power consumption design, where individual pixel readouts are optimized for minimal energy per conversion event. The "first analog-to-digital converter" and "second analog-to-digital converter" are event-driven, asynchronous ADCs (e.g., spike-based or integrate-and-fire converters) that only consume power and generate digital signals when a significant change in light intensity is detected at the "red pixels," "blue pixels," or "green pixels." This allows the ADCs to operate for extended periods on minimal power sources (e.g., solar harvesting). The "color interpolation circuit" is implemented as a sparse event-processing unit, combining the intermittently generated digital signals over time and space to reconstruct environmental changes, focusing on trends rather than continuous full-frame video.

graph TD
    Sub_R[Subset R Pixels] --> Async_ADC1[Asynchronous ADC 1 (Event-Driven)]
    Sub_B[Subset B Pixels] --> Async_ADC1
    Sub_G1[Subset G1 Pixels] --> Async_ADC2[Asynchronous ADC 2 (Event-Driven)]
    Sub_G2[Subset G2 Pixels] --> Async_ADC2

    Async_ADC1 -- Sparse Digital R/B Signals --> SEPU[Sparse Event Processing Unit (Color Interpolation)]
    Async_ADC2 -- Sparse Digital G1/G2 Signals --> SEPU

    SEPU -- Environmental Data (Trends) --> WirelessNode[Wireless Node for Climate Network]

2.5. Cross-Domain Application: Automated Manufacturing Defect Inspection for Micro-Electronics

Enabling Description: The solid-state imaging device is integrated into an automated optical inspection (AOI) system for micro-electronic components, specifically for detecting solder joint defects or misaligned surface-mount devices. The "groups of pixels" are configured with specific illumination and filtering, where "red pixels" detect reflections from solder masks, "blue pixels" detect component body colors, and "first and second green pixels" detect solder joint integrity under polarized light. The first A/D converter processes the high-resolution outputs of the "red pixels" and "blue pixels," while the second A/D converter handles the "first green pixels" and "second green pixels." These ADCs are designed for extremely low latency and high precision (e.g., 14-bit resolution). The "color interpolation circuit" is replaced by a pattern recognition and defect localization module, utilizing high-speed correlation algorithms and deep learning models to pinpoint sub-micron level defects on circuit boards, enabling rapid quality control in mass production.

graph TD
    R_AOI[AOI Red Pixels] --> ADC_AOI1[Low-Latency ADC 1]
    B_AOI[AOI Blue Pixels] --> ADC_AOI1
    G1_AOI[AOI G1 Pixels] --> ADC_AOI2[Low-Latency ADC 2]
    G2_AOI[AOI G2 Pixels] --> ADC_AOI2

    ADC_AOI1 -- Digital R/B Signals --> PRDLM[Pattern Recognition & Defect Localization Module]
    ADC_AOI2 -- Digital G1/G2 Signals --> PRDLM

    PRDLM -- Defect Location/Type --> ManufacturingControl[Automated Manufacturing Control]

2.6. Cross-Domain Application: Biometric Security - Real-Time Vein Pattern Recognition

Enabling Description: The imaging device is embedded in a biometric security system for real-time vein pattern recognition. The "groups of pixels" are equipped with near-infrared (NIR) filters tuned to specific hemoglobin absorption peaks, allowing for differentiation between oxygenated and deoxygenated blood. Thus, "red pixels" capture one NIR band (e.g., 850nm), "blue pixels" capture another (e.g., 940nm), and "first and second green pixels" capture further distinct NIR bands (e.g., 780nm and 1000nm). This multi-spectral NIR data enhances the contrast of subcutaneous vein patterns. The first A/D converter processes the 850nm and 940nm channels, and the second A/D converter processes the 780nm and 1000nm channels. The "color interpolation circuit" is substituted with a vein pattern extraction and matching algorithm, combining the multi-band NIR digital signals to generate a robust, spoof-resistant biometric template for user authentication.

graph TD
    NIR_850[NIR 850nm Pixel Groups] --> ADC_BIO1[ADC for Biometric 1]
    NIR_940[NIR 940nm Pixel Groups] --> ADC_BIO1
    NIR_780[NIR 780nm Pixel Groups] --> ADC_BIO2[ADC for Biometric 2]
    NIR_1000[NIR 1000nm Pixel Groups] --> ADC_BIO2

    ADC_BIO1 -- Digital NIR Signals --> VPEMA[Vein Pattern Extraction & Matching Algorithm]
    ADC_BIO2 -- Digital NIR Signals --> VPEMA

    VPEMA -- Biometric Template --> AuthenticationSystem[Security Authentication System]

2.7. Cross-Domain Application: Art Restoration and Authenticity Verification with UV-Fluorescence Imaging

Enabling Description: This solid-state imaging device is deployed in art conservation for non-destructive analysis and authenticity verification of paintings. The "groups of pixels" are optimized for ultraviolet (UV)-induced fluorescence imaging. The "red pixel" captures long-wavelength UV fluorescence (e.g., above 600nm), the "blue pixel" captures short-wavelength UV fluorescence (e.g., 400-500nm), and the two "green pixels" capture intermediate UV fluorescence bands. This allows for identifying different pigments, varnishes, and hidden underdrawings based on their unique fluorescence spectra. The first A/D converter digitizes outputs from the long-wavelength and short-wavelength fluorescence channels, and the second A/D converter processes the intermediate fluorescence channels. The "color interpolation circuit" is replaced by a spectral signature analysis module, which combines the multi-band fluorescence digital signals to create a composite spectral map, revealing details critical for restoration planning or detecting forgeries.

graph TD
    UVF_LW[UV-Fluorescence Pixel Groups LW] --> ADC_ART1[ADC for Art Conservation 1]
    UVF_SW[UV-Fluorescence Pixel Groups SW] --> ADC_ART1
    UVF_IW1[UV-Fluorescence Pixel Groups IW1] --> ADC_ART2[ADC for Art Conservation 2]
    UVF_IW2[UV-Fluorescence Pixel Groups IW2] --> ADC_ART2

    ADC_ART1 -- Digital UVF Signals --> SSAM[Spectral Signature Analysis Module]
    ADC_ART2 -- Digital UVF Signals --> SSAM

    SSAM -- Art Analysis Map --> ArtConservationist[Art Conservationist Workstation]

2.8. Integration with Emerging Tech: Real-time 3D Reconstruction with Neural Network-Enhanced Stereo Vision

Enabling Description: The solid-state imaging device, comprising "groups of pixels," is utilized in a stereo vision system for real-time 3D environment reconstruction (e.g., robotics, virtual reality). Two such imaging devices are employed, offset from each other. Each device's "first analog-to-digital converter" and "second analog-to-digital converter" provide high-speed, synchronized digital outputs from their respective color pixels. The "color interpolation circuit" is then integrated with an on-chip neural network accelerator. This accelerator performs deep-learning-based stereo matching and depth estimation, taking the combined digital signals from both imagers as input. The neural network algorithm, instead of simple color interpolation, intelligently correlates features between the left and right images (derived from the individual pixel groups) to generate a high-fidelity, real-time 3D point cloud or depth map, enabling advanced spatial awareness for autonomous systems.

graph TD
    PixelGroupL[Left Imager Pixel Groups] --> ADCL1[Left ADC 1]
    PixelGroupL --> ADCL2[Left ADC 2]
    PixelGroupR[Right Imager Pixel Groups] --> ADCR1[Right ADC 1]
    PixelGroupR --> ADCR2[Right ADC 2]

    ADCL1 -- Left Digital R/B --> NN_ACCEL[Neural Network Accelerator (3D Reconstruction)]
    ADCL2 -- Left Digital G1/G2 --> NN_ACCEL
    ADCR1 -- Right Digital R/B --> NN_ACCEL
    ADCR2 -- Right Digital G1/G2 --> NN_ACCEL

    NN_ACCEL -- Real-time 3D Point Cloud --> RoboticSystem[Robotic System / VR Application]

2.9. Integration with Emerging Tech: Blockchain for Image Provenance and Tamper Detection

Enabling Description: This solid-state imaging device, used for critical document scanning or forensic photography, embeds a hardware security module (HSM) and blockchain client. After the "first analog-to-digital converter" and "second analog-to-digital converter" convert the outputs from the "groups of pixels" into digital signals, and the "color interpolation circuit" combines them, the resulting image data (or a cryptographic hash of it) is immediately timestamped and signed by the HSM. This signed hash, along with relevant metadata (e.g., location, time, sensor ID, camera settings), is then appended to a permissioned blockchain ledger via a secure communication channel. Each pixel's raw output could also have a unique, cryptographically signed identifier (e.g., using a Physical Unclonable Function, PUF) linked to the blockchain, ensuring pixel-level provenance and providing an immutable record for tamper detection and verification of image authenticity from source to storage.

graph TD
    PixelGroup[Pixel Groups (R, B, G1, G2)] --> ADC1[First ADC]
    PixelGroup --> ADC2[Second ADC]

    ADC1 -- Digital R/B Signals --> CIC[Color Interpolation Circuit]
    ADC2 -- Digital G1/G2 Signals --> CIC

    CIC -- Final Image Data --> HSM[Hardware Security Module]
    HSM -- Cryptographic Hash + Signature --> BlockchainClient[Blockchain Client]
    BlockchainClient -- Transact --> BlockchainLedger[Permissioned Blockchain Ledger]

    SensorID[Sensor ID (PUF)] --> HSM
    Metadata[Timestamp, Location, Settings] --> HSM

2.10. The "Inverse" or Failure Mode: Stealth Mode with Spectral Blending and Minimal Emission

Enabling Description: The solid-state imaging device is designed for covert operations, incorporating a "stealth mode" with minimal light emission and advanced spectral blending for reduced detectability. In stealth mode, the active illumination sources are powered down, and the "groups of pixels" rely solely on ambient light. The "red pixel," "blue pixel," and "green pixels" are operated at extremely low integration times and then spectrally blended using the "color interpolation circuit" to minimize the contrast and distinctiveness of captured objects against the background, outputting a highly desaturated, low-fidelity image. Simultaneously, the "first analog-to-digital converter" and "second analog-to-digital converter" are dynamically reconfigured to output only 4-bit or 2-bit digital signals, drastically reducing data rate and power consumption, making the device harder to detect via electromagnetic emissions analysis. This results in a "limited-functionality" mode that prioritizes covert operation over image quality.

stateDiagram
    state NormalOperation {
        [*] --> ActiveImaging
        ActiveImaging --> StealthMode : Activate Stealth
    }

    state StealthMode {
        state "Low Detectability Imaging" {
            [*] --> AmbientLightSensing
            AmbientLightSensing --> LowResADC : Reduced Bit-Depth ADC
            LowResADC --> SpectralBlending : Color Interpolation for Desaturation
            SpectralBlending --> CovertOutput : Desaturated/Low-Fi Image
        }
        StealthMode --> ActiveImaging : Deactivate Stealth
    }

    ActiveImaging --> Off : Power Off
    StealthMode --> Off : Power Off

---

Derivatives for Claim 18: Imaging Method with Two A/D Converters and Color Interpolation

Claim 18: An imaging method comprising: converting an output of a red pixel into a first digital signal using a first analog-to-digital converter; converting an output of a blue pixel into a second digital signal using the first analog-to-digital converter; converting an output of a first green pixel into a third digital signal using a second analog-to-digital converter; converting an output of a second green pixel into a fourth digital signal using the second analog-to-digital converter; and combining the first, second, third and fourth digital signals using a color interpolation circuit.

---

3.1. Material & Component Substitution (Method using): Pulsed X-Ray Imaging with High-Speed Scintillator Array and Multi-Channel Flash ADC

Enabling Description: The imaging method is performed using a system designed for pulsed X-ray imaging. The "red pixel" output, "blue pixel" output, "first green pixel" output, and "second green pixel" output are derived from distinct regions of a fast scintillator array that convert X-ray photons into visible light flashes of varying spectral characteristics (e.g., different scintillator materials for pseudo-color X-ray). The method comprises: converting an output of a red pixel (from a specific scintillator region) into a first digital signal using a first analog-to-digital converter (a dedicated channel of a multi-channel flash ADC); converting an output of a blue pixel (from another scintillator region) into a second digital signal using the same first analog-to-digital converter (another channel of the flash ADC); similarly for the green channels via a second analog-to-digital converter (other channels of the flash ADC). The multi-channel flash ADC enables simultaneous, high-speed digitization of all channels. The method then proceeds to combining the first, second, third and fourth digital signals using a color interpolation circuit (spectral reconstruction algorithm) to produce a high-resolution, pseudo-color X-ray image, enabling detailed material analysis or medical diagnostics.

sequenceDiagram
    participant ScintArray as Scintillator Array
    participant FlashADC as Multi-Channel Flash ADC
    participant SRAlgo as Spectral Reconstruction Algorithm

    ScintArray ->> FlashADC: Output Red Pixel (Analog)
    ScintArray ->> FlashADC: Output Blue Pixel (Analog)
    ScintArray ->> FlashADC: Output Green1 Pixel (Analog)
    ScintArray ->> FlashADC: Output Green2 Pixel (Analog)

    FlashADC --(First ADC)--> FlashADC: Convert Red (First Digital)
    FlashADC --(First ADC)--> FlashADC: Convert Blue (Second Digital)
    FlashADC --(Second ADC)--> FlashADC: Convert Green1 (Third Digital)
    FlashADC --(Second ADC)--> FlashADC: Convert Green2 (Fourth Digital)

    FlashADC ->> SRAlgo: Transmit First, Second, Third, Fourth Digital Signals
    SRAlgo ->> SRAlgo: Combine Signals (Color Interpolation)
    SRAlgo ->> Viewer: Display Pseudo-Color X-ray Image

3.2. Operational Parameter Expansion: High-G Shock Event Recording with Ultra-Fast Event-Triggered A/D Conversion

Enabling Description: This imaging method is applied to recording images during extreme high-G shock events (e.g., ballistics, impact testing). The method utilizes a robust, compact image sensor where each pixel's output is buffered for a very short duration. The core steps, triggered by an accelerometer sensing the shock event, are: converting an output of a red pixel into a first digital signal using a first analog-to-digital converter (an ultra-fast, single-shot, waveform-digitizing ADC with femtosecond sampling precision); converting an output of a blue pixel into a second digital signal using the same first analog-to-digital converter; and similarly for the green channels via a second analog-to-digital converter. These ADCs are designed to capture a rapid sequence of analog data within picoseconds or nanoseconds of the trigger. The combining step by the color interpolation circuit then reconstructs the image from these transient digital signals, potentially using sparse sampling and predictive algorithms, to provide high-fidelity "snap-shot" images of phenomena occurring at extreme velocities.

sequenceDiagram
    participant Accelerometer as Accelerometer
    participant PixelArray as Pixel Array
    participant UFSADC as Ultra-Fast Single-Shot ADC
    participant RECON as Image Reconstruction (Color Interpolation)

    Accelerometer -- Trigger --> UFSADC: High-G Event Trigger

    PixelArray ->> UFSADC: Output Red Pixel (Analog)
    PixelArray ->> UFSADC: Output Blue Pixel (Analog)
    PixelArray ->> UFSADC: Output Green1 Pixel (Analog)
    PixelArray ->> UFSADC: Output Green2 Pixel (Analog)

    UFSADC --(First ADC)--> UFSADC: Convert Red (First Digital)
    UFSADC --(First ADC)--> UFSADC: Convert Blue (Second Digital)
    UFSADC --(Second ADC)--> UFSADC: Convert Green1 (Third Digital)
    UFSADC --(Second ADC)--> UFSADC: Convert Green2 (Fourth Digital)

    UFSADC ->> RECON: Transmit First, Second, Third, Fourth Digital Signals
    RECON ->> RECON: Combine Signals (Color Interpolation)
    RECON ->> Analysis: Output High-G Snap-shot Image

3.3. Operational Parameter Expansion: Astronomical Imaging in Deep Space at Sub-Hz Frame Rates

Enabling Description: The imaging method is performed by an astronomical observatory in deep space, focusing on extremely faint celestial objects over extended integration periods. The method involves: converting an output of a red pixel (from a photon-counting detector sensitive to specific emission lines) into a first digital signal using a first analog-to-digital converter (a low-noise, high-resolution sigma-delta ADC with a long integration window, e.g., sampling at 0.1 Hz); converting an output of a blue pixel into a second digital signal using the same first analog-to-digital converter; and similarly for the green channels via a second analog-to-digital converter. Each conversion step represents the accumulated photon counts over minutes or hours. The combining step by the color interpolation circuit involves precise astrometric alignment of multiple long-exposure frames, cosmic ray rejection, and sophisticated noise modeling to produce deep-field color images from extremely sparse photon data, revealing distant galaxies or exoplanets.

sequenceDiagram
    participant PhotonDet as Photon-Counting Detector
    participant SigmaDeltaADC as Low-Noise Sigma-Delta ADC
    participant AstroProc as Astronomical Image Processor (Color Interpolation)

    loop Long Integration Period
        PhotonDet ->> SigmaDeltaADC: Output Red Pixel (Accumulated Analog)
        PhotonDet ->> SigmaDeltaADC: Output Blue Pixel (Accumulated Analog)
        PhotonDet ->> SigmaDeltaADC: Output Green1 Pixel (Accumulated Analog)
        PhotonDet ->> SigmaDeltaADC: Output Green2 Pixel (Accumulated Analog)
    end

    SigmaDeltaADC --(First ADC)--> SigmaDeltaADC: Convert Red (First Digital)
    SigmaDeltaADC --(First ADC)--> SigmaDeltaADC: Convert Blue (Second Digital)
    SigmaDeltaADC --(Second ADC)--> SigmaDeltaADC: Convert Green1 (Third Digital)
    SigmaDeltaADC --(Second ADC)--> SigmaDeltaADC: Convert Green2 (Fourth Digital)

    SigmaDeltaADC ->> AstroProc: Transmit First, Second, Third, Fourth Digital Signals (Sub-Hz)
    AstroProc ->> AstroProc: Combine Signals (Astrometric Alignment, Noise Model, Color Interp)
    AstroProc ->> Observer: Display Deep-Field Astronomical Image

3.4. Cross-Domain Application: Predictive Maintenance in Wind Turbines via Thermal Imaging

Enabling Description: This imaging method is employed for predictive maintenance of wind turbine blades, detecting early signs of structural fatigue or delamination through thermal signatures. The "red pixel" output, "blue pixel" output, "first green pixel" output, and "second green pixel" output correspond to different infrared (IR) spectral bands (e.g., mid-wave IR, long-wave IR, two narrow-band IR channels) captured by a microbolometer array. The method comprises: converting an output of a red pixel (mid-wave IR) into a first digital signal using a first analog-to-digital converter (a thermal ADC optimized for IR sensor characteristics); converting an output of a blue pixel (long-wave IR) into a second digital signal using the same first analog-to-digital converter; and similarly for the narrow-band IR channels via a second analog-to-digital converter. The combining step by the color interpolation circuit is replaced by a thermal anomaly detection algorithm, generating a false-color thermal map that highlights hot spots or inconsistent thermal patterns indicative of impending failure, enabling timely repair.

sequenceDiagram
    participant Microbolometer as Microbolometer Array
    participant ThermalADC as Thermal ADC
    participant TADA as Thermal Anomaly Detection Algorithm

    Microbolometer ->> ThermalADC: Output Mid-Wave IR Pixel (Analog)
    Microbolometer ->> ThermalADC: Output Long-Wave IR Pixel (Analog)
    Microbolometer ->> ThermalADC: Output NB-IR1 Pixel (Analog)
    Microbolometer ->> ThermalADC: Output NB-IR2 Pixel (Analog)

    ThermalADC --(First ADC)--> ThermalADC: Convert Mid-Wave IR (First Digital)
    ThermalADC --(First ADC)--> ThermalADC: Convert Long-Wave IR (Second Digital)
    ThermalADC --(Second ADC)--> ThermalADC: Convert NB-IR1 (Third Digital)
    ThermalADC --(Second ADC)--> ThermalADC: Convert NB-IR2 (Fourth Digital)

    ThermalADC ->> TADA: Transmit First, Second, Third, Fourth Digital Signals
    TADA ->> TADA: Combine Signals (Thermal Anomaly Detection)
    TADA ->> MaintenanceSystem: Output False-Color Thermal Map (Predictive Maintenance Alert)

3.5. Cross-Domain Application: Subterranean Mapping for Mining Operations with Ground-Penetrating Radar

Enabling Description: This imaging method is adapted for subterranean mapping in mining operations, utilizing a ground-penetrating radar (GPR) system. The "red pixel" output, "blue pixel" output, "first green pixel" output, and "second green pixel" output are derived from a multi-frequency GPR antenna array, capturing reflected radar pulses at different penetration depths and frequencies. The method comprises: converting an output of a red pixel (GPR high-frequency/shallow depth) into a first digital signal using a first analog-to-digital converter (a rapid GPR waveform digitizer); converting an output of a blue pixel (GPR low-frequency/deep depth) into a second digital signal using the same first analog-to-digital converter; and similarly for intermediate GPR channels via a second analog-to-digital converter. The combining step by the color interpolation circuit is replaced by a subsurface tomography algorithm, generating a 3D geological map that visualizes rock strata, fault lines, or mineral deposits based on the combined GPR digital signals.

sequenceDiagram
    participant GPR_Array as Multi-Frequency GPR Antenna Array
    participant GPR_WavDig as GPR Waveform Digitizer
    participant SubTomography as Subsurface Tomography Algorithm

    GPR_Array ->> GPR_WavDig: Output HF/Shallow GPR (Analog)
    GPR_Array ->> GPR_WavDig: Output LF/Deep GPR (Analog)
    GPR_Array ->> GPR_WavDig: Output Mid-Freq1 GPR (Analog)
    GPR_Array ->> GPR_WavDig: Output Mid-Freq2 GPR (Analog)

    GPR_WavDig --(First ADC)--> GPR_WavDig: Convert HF/Shallow (First Digital)
    GPR_WavDig --(First ADC)--> GPR_WavDig: Convert LF/Deep (Second Digital)
    GPR_WavDig --(Second ADC)--> GPR_WavDig: Convert Mid-Freq1 (Third Digital)
    GPR_WavDig --(Second ADC)--> GPR_WavDig: Convert Mid-Freq2 (Fourth Digital)

    GPR_WavDig ->> SubTomography: Transmit First, Second, Third, Fourth Digital Signals
    SubTomography ->> SubTomography: Combine Signals (Subsurface Tomography)
    SubTomography ->> Geologist: Display 3D Geological Map

3.6. Cross-Domain Application: Aquatic Habitat Monitoring with Multi-Parameter Sonar Imaging

Enabling Description: This imaging method is applied to aquatic habitat monitoring, using a multi-parameter sonar system to map underwater environments. The "red pixel" output, "blue pixel" output, "first green pixel" output, and "second green pixel" output are derived from different sonar frequencies or beam patterns (e.g., high-frequency for fine detail, low-frequency for penetration, wide-beam for coverage, narrow-beam for precision). The method comprises: converting an output of a red pixel (high-frequency sonar) into a first digital signal using a first analog-to-digital converter (a fast sonar signal processor); converting an output of a blue pixel (low-frequency sonar) into a second digital signal using the same first analog-to-digital converter; and similarly for the other sonar parameters via a second analog-to-digital converter. The combining step by the color interpolation circuit is replaced by an underwater acoustic reconstruction algorithm, generating a composite sonar image that visualizes bathymetry, submerged vegetation, or fish schools, crucial for ecological studies.

sequenceDiagram
    participant SonarArray as Multi-Parameter Sonar Array
    participant SonarProc as Sonar Signal Processor
    participant UARAlgo as Underwater Acoustic Reconstruction Algorithm

    SonarArray ->> SonarProc: Output High-Freq Sonar (Analog)
    SonarArray ->> SonarProc: Output Low-Freq Sonar (Analog)
    SonarArray ->> SonarProc: Output Wide-Beam Sonar (Analog)
    SonarArray ->> SonarProc: Output Narrow-Beam Sonar (Analog)

    SonarProc --(First ADC)--> SonarProc: Convert High-Freq (First Digital)
    SonarProc --(First ADC)--> SonarProc: Convert Low-Freq (Second Digital)
    SonarProc --(Second ADC)--> SonarProc: Convert Wide-Beam (Third Digital)
    SonarProc --(Second ADC)--> SonarProc: Convert Narrow-Beam (Fourth Digital)

    SonarProc ->> UARAlgo: Transmit First, Second, Third, Fourth Digital Signals
    UARAlgo ->> UARAlgo: Combine Signals (Underwater Acoustic Reconstruction)
    UARAlgo ->> MarineBiologist: Display Composite Sonar Image

3.7. Integration with Emerging Tech: AI-Driven Noise Reduction and Super-Resolution Demosaicing

Enabling Description: The imaging method incorporates an on-chip Artificial Intelligence (AI) accelerator to enhance image quality. The initial steps of converting an output of a red pixel via a first analog-to-digital converter, and similarly for blue, first green, and second green pixels, remain. However, the combining step is augmented: the color interpolation circuit now integrates a deep neural network (DNN) trained for both noise reduction and super-resolution demosaicing. The DNN receives the initial digital signals and performs intelligent pixel reconstruction, inferring high-frequency details beyond conventional interpolation and adaptively suppressing various noise types (e.g., shot noise, read noise) based on learned patterns. This AI-driven process combines the first, second, third and fourth digital signals to yield a significantly cleaner and higher-resolution final image.

sequenceDiagram
    participant Pixel as Pixel Array
    participant ADC1 as First ADC
    participant ADC2 as Second ADC
    participant AI_DNN as AI-Enhanced Color Interpolation (DNN)

    Pixel ->> ADC1: Output Red, Blue (Analog)
    Pixel ->> ADC2: Output Green1, Green2 (Analog)

    ADC1 ->> ADC1: Convert Red (First Digital)
    ADC1 ->> ADC1: Convert Blue (Second Digital)
    ADC2 ->> ADC2: Convert Green1 (Third Digital)
    ADC2 ->> ADC2: Convert Green2 (Fourth Digital)

    ADC1 ->> AI_DNN: Transmit First, Second Digital Signals
    ADC2 ->> AI_DNN: Transmit Third, Fourth Digital Signals
    AI_DNN ->> AI_DNN: Perform DNN-based Noise Reduction & Super-Resolution Demosaicing
    AI_DNN ->> Output: Display High-Quality Image

3.8. Integration with Emerging Tech: Real-time Data Streaming to Cloud with Serverless Image Processing

Enabling Description: This imaging method is implemented in a distributed cloud-connected camera system. The steps of converting an output of a red pixel via a first analog-to-digital converter, and similarly for blue, first green, and second green pixels, generate raw digital signals on-device. These raw digital signals are then immediately streamed over a high-bandwidth wireless connection to a cloud computing platform. The combining step, involving the color interpolation circuit, is entirely executed on the cloud using a serverless function architecture (e.g., AWS Lambda, Google Cloud Functions). Upon receiving the four digital signal streams, a serverless function is invoked which performs the color interpolation, applies further image enhancements, and stores the processed image in cloud storage or streams it to end-user applications. This method offloads heavy computation from the edge device, enabling smaller, lower-power camera units.

sequenceDiagram
    participant OnDevice as On-Device Camera
    participant Cloud as Cloud Computing Platform
    participant ServerlessF as Serverless Function (Color Interpolation)
    participant Storage as Cloud Storage

    OnDevice ->> OnDevice: Convert Red (First Digital)
    OnDevice ->> OnDevice: Convert Blue (Second Digital)
    OnDevice ->> OnDevice: Convert Green1 (Third Digital)
    OnDevice ->> OnDevice: Convert Green2 (Fourth Digital)

    OnDevice ->> Cloud: Stream First, Second, Third, Fourth Digital Signals
    Cloud ->> ServerlessF: Invoke Serverless Function
    ServerlessF ->> ServerlessF: Combine Signals (Color Interpolation)
    ServerlessF ->> Storage: Store Processed Image
    ServerlessF ->> Client: Stream Processed Image to Client

3.9. The "Inverse" or Failure Mode: Privacy-Preserving Low-Resolution Mode

Enabling Description: The imaging method includes a "privacy-preserving low-resolution mode" where, to protect subject anonymity, the detail captured is intentionally reduced. In this mode, the method still involves converting an output of a red pixel via a first analog-to-digital converter, and similarly for blue, first green, and second green pixels. However, the ADCs are configured to operate at a significantly reduced bit-depth (e.g., 1-bit or 2-bit per channel) and the pixel outputs are spatially averaged over larger blocks before conversion, effectively downsampling the image. The combining step by the color interpolation circuit then performs a highly blurred or block-based reconstruction using these low-bit-depth, averaged digital signals, intentionally obscuring fine details while preserving general scene composition. This results in a "limited-functionality" image that is sufficient for motion detection or general awareness without identifying individuals.

stateDiagram
    state NormalMode {
        [*] --> HighResolutionImaging
        HighResolutionImaging --> PrivacyMode : Activate Privacy
    }

    state PrivacyMode {
        state "Low-Resolution, Obscured Imaging" {
            [*] --> PixelAveraging : Spatial Averaging of Pixels
            PixelAveraging --> ReducedBitADC : Low Bit-Depth ADC Conversion
            ReducedBitADC --> BlurredInterp : Block-based Color Interpolation
            BlurredInterp --> PrivacyOutput : Obscured Image
        }
        PrivacyMode --> NormalMode : Deactivate Privacy
    }

3.10. The "Inverse" or Failure Mode: Energy Harvesting Diagnostic Scan

Enabling Description: This imaging method incorporates an "energy harvesting diagnostic scan" mode, particularly useful for long-term deployments where continuous power is scarce. Instead of a standard full-frame capture, the method comprises: converting an output of a red pixel by a first analog-to-digital converter (a low-power, single-pixel readout ADC) only when sufficient ambient light energy has been harvested to power that specific conversion. This is done sequentially for selected red, blue, first green, and second green pixels, rather than in parallel for all. The first analog-to-digital converter and second analog-to-digital converter are dynamically reconfigured to sample only a minimal subset of pixels across the array, and their outputs are combined by the color interpolation circuit into a highly sparse, ultra-low-resolution diagnostic image. This image, perhaps just a few pixels, provides basic status (e.g., "is it light or dark?") or detects critical failures (e.g., a completely dead pixel region) while consuming minimal energy, extending operational lifespan.

sequenceDiagram
    participant EnergyHarv as Energy Harvesting Unit
    participant PixelArray as Pixel Array (Subset)
    participant LP_ADC as Low-Power, Single-Pixel ADC
    participant SparseInterp as Sparse Interpolation (Diagnostic)

    loop While Energy Available
        EnergyHarv ->> LP_ADC: Power for Conversion
        LP_ADC ->> PixelArray: Select Red Pixel
        PixelArray ->> LP_ADC: Output Red Pixel (Analog)
        LP_ADC --(First ADC)--> LP_ADC: Convert Red (First Digital)

        LP_ADC ->> PixelArray: Select Blue Pixel
        PixelArray ->> LP_ADC: Output Blue Pixel (Analog)
        LP_ADC --(First ADC)--> LP_ADC: Convert Blue (Second Digital)

        LP_ADC ->> PixelArray: Select Green1 Pixel
        PixelArray ->> LP_ADC: Output Green1 Pixel (Analog)
        LP_ADC --(Second ADC)--> LP_ADC: Convert Green1 (Third Digital)

        LP_ADC ->> PixelArray: Select Green2 Pixel
        PixelArray ->> LP_ADC: Output Green2 Pixel (Analog)
        LP_ADC --(Second ADC)--> LP_ADC: Convert Green2 (Fourth Digital)

        LP_ADC ->> SparseInterp: Transmit Selected Digital Signals
        SparseInterp ->> SparseInterp: Combine (Sparse Diagnostic Image)
        SparseInterp ->> Monitor: Output Diagnostic Image
    end

---

Combination Prior Art Scenarios

Here are at least three scenarios where US patent 6838651 is combined with existing open-source standards to generate further prior art:

1. Combination with V4L2 (Video4Linux2) API and GStreamer Framework:

   • Scenario: A developer implements a driver for an image sensor embodying US6838651's architecture (multi-ADC, color pixels, interpolation) within the Linux kernel, exposing its functionalities (e.g., raw pixel data access, frame rate control, variable ADC power modes) through the V4L2 API. The first and second analog-to-digital converters provide digital signals that are then processed by a color interpolation circuit. This data stream is then integrated into a GStreamer pipeline for further processing, encoding (e.g., into H.264 using x264enc), and streaming over standard network protocols. The V4L2 interface allows control over the "programmable clock generator" and "control" logic (as described in dependent claim 6) for dynamic frame rate adjustments and ADC power management, all exposed through open-source software interfaces.
   • Obviousness Argument: The application of a standard Linux video interface (V4L2) and a widely used multimedia framework (GStreamer) to control and process data from any CMOS image sensor, including one with multiple ADCs and internal color interpolation as described in US6838651, is a straightforward engineering integration. Exposing and controlling the patent's specific features (e.g., multiple ADCs, variable frame rate) through existing open-source APIs renders these control mechanisms and data flow obvious.

2. Combination with JPEG XR (or WebP/AVIF) Image Compression Standard and OpenCV:

   • Scenario: An imaging system implementing the core components of US6838651 (red, blue, green pixels, two ADCs, color interpolation) outputs a raw digital image. This raw image, after combining the first, second, third and fourth digital signals via the color interpolation circuit, is then fed into an open-source implementation of the JPEG XR (or WebP/AVIF) image compression algorithm. Prior to compression, the image data might undergo additional processing, such as noise reduction or sharpening, using functions from the open-source OpenCV library. The combined system produces a highly efficient, compressed image format suitable for web delivery or storage, leveraging the image quality improvements from the multi-ADC architecture while adhering to open compression standards.
   • Obviousness Argument: The application of standard image compression techniques (JPEG XR, WebP, AVIF) and widely available image processing libraries (OpenCV) to the output of any digital image sensor, including those with advanced internal processing like that of US6838651, is a routine implementation. Optimizing the patent's output for efficient storage and transmission using open standards, and leveraging open-source computer vision tools for further enhancement, constitutes an obvious step for a person skilled in the art of digital imaging.

3. Combination with MIPI CSI-2 Interface Standard and the RISC-V Instruction Set Architecture:

   • Scenario: A CMOS image sensor chip, designed according to US6838651's principles, features the red pixel, blue pixel, first green pixel, second green pixel, and their respective analog-to-digital converters. The color interpolation circuit is implemented on-chip, and its output is formatted for transmission over a standard MIPI CSI-2 (Camera Serial Interface 2) physical layer and protocol. Furthermore, the internal control logic for managing the first analog-to-digital converter, second analog-to-digital converter, and the color interpolation circuit (e.g., timing, sequencing, error handling) is implemented on a custom, on-chip microcontroller based on the open-source RISC-V instruction set architecture. This RISC-V core might also run the "programmable clock generator" and "control" logic described in dependent claim 6.
   • Obviousness Argument: Utilizing a standard, open-source camera interface protocol like MIPI CSI-2 for transmitting image data from any modern image sensor is a common design practice. Similarly, employing an open-source instruction set architecture like RISC-V for the on-chip control of digital hardware blocks, including ADCs and image processing units, is an obvious choice for semiconductor designers seeking flexibility, customization, and reduced licensing costs. Integrating the patent's architectural elements with these ubiquitous open standards and architectures constitutes an obvious system-level design.