US 6466226

US Patent 6466226, titled "Method and apparatus for pixel filtering using shared filter resource between overlay and texture mapping engines," was assigned to Intel Corp. The patent lists David W. Watson, Kim A. Meinerth, Indraneel Ghosh, Thomas A. Piazza, and Val G. Cook as inventors. The application was filed on January 10, 2000, and the patent was issued on October 15, 2002.

The abstract describes a configurable filter module that provides shared filtering resources between an overlay engine and a texture mapping engine in a graphics system. This module includes multiple linear blend units that receive data from either the overlay engine or a mapping engine cache. A filter output multiplexer then selects the proper byte ordering for the output. The key innovation is that these linear blend units can function either as an overlay interpolator filter for linear blending of overlay engine data during a linear blend mode, or as a texture bilinear filter for bilinear filtering of mapping engine cache data during a bilinear filtering mode.

A plain-language overview of the independent claims is as follows:

• Claim 1: This claim describes a reconfigurable hardware component (a configurable filter module) within a graphics system. This component contains several processing units (linear blend units) that can receive data from two different sources: a 2D graphics overlay engine or a 3D texture mapping cache. These linear blend units are designed to operate in two distinct ways: either blending 2D data (acting as an overlay interpolator) or performing bilinear filtering on 3D data (acting as a texture bilinear filter). A final component (filter output multiplexer) organizes the processed data for output.
• Claim 12: This claim defines a graphics controller that incorporates the shared filter functionality. It includes a 3D graphics engine (which handles functions like creating 2D images from 3D objects), a 2D graphics engine, and a display engine that includes an overlay engine (for combining video with graphics). Crucially, the 3D engine contains a mapping engine cache, the configurable filter (as described in Claim 1, sharing resources with the overlay engine), and a color calculator for processing texture maps. This configurable filter is responsible for performing either 2D linear blending or 3D bilinear filtering based on the data source.
• Claim 27: This claim outlines a method for efficiently processing video data in a graphics system by sharing filtering hardware. The method involves taking video data from either a 2D overlay engine or a 3D texture mapping engine. A set of linear blend units are then dynamically configured to perform either linear blending (for overlay data) or bilinear filtering (for texture data). Finally, the method involves calculating the color values necessary to achieve a realistic 3D appearance (perspective shading) in various display formats.
• Claim 35: This claim describes a graphics controller that features both a 2D engine and a 3D engine. It explicitly includes an overlay engine for handling 2D data and a mapping engine cache for 3D data. The core of the claim is a configurable filter that serves as a shared resource between these engines. This filter can perform either linear blending on 2D data (originating from the 2D engine via the overlay engine) or bilinear filtering on 3D data (from the mapping engine cache) before the data is displayed.

The patent has an "Expired - Lifetime" legal status, indicating it is no longer in force.

A search of the CAFC 2026 dockets for US patent 6466226 did not return any results.

No known litigation involving US patent 6466226 was found in the conducted searches.

Proceedings Overview

There are no AIA trial proceedings on file for US Patent 6,466,226 as of July 15, 2026. This means the patent has not been challenged through Inter Partes Review (IPR), Post-Grant Review (PGR), or Covered Business Method (CBM) review at the Patent Trial and Appeal Board (PTAB). For a defendant, this indicates the patent claims are currently untested by the concentrated prior art review process available at the PTAB.

Strategic Summary

As there are no PTAB proceedings associated with US Patent 6,466,226, all claims of the patent remain UNTESTED by an AIA trial. The patent owner has not had to defend the patentability of its claims against a petitioner at the PTAB, meaning no claims have been canceled or confirmed as patentable through these specific administrative trial processes.

Consequently, there is no estoppel landscape established under 35 U.S.C. § 315(e)(2) for this patent. Any potential petitioner (and their privies) would not be barred from raising any ground that they raised or reasonably could have raised in a prior IPR, PGR, or CBM, because none exist. This leaves all prior-art grounds available for a potential challenger.

The absence of PTAB activity is a notable signal. Patents that are actively asserted or hold significant commercial value often become targets for IPRs or other AIA trials. The lack of such challenges for US Patent 6,466,226 could imply that it has not been heavily asserted, or that prior art challenges through other avenues (e.g., district court litigation) have not led to PTAB filings.

Recommended Next Steps

Since no PTAB activity exists for US Patent 6,466,226, a defendant facing assertion of this patent would not have the benefit of prior PTAB invalidity findings. The absence of challenges means that the patent's claims are entirely untested within the PTAB framework. A potential defendant could consider initiating an IPR against the patent, assuming the statutory requirements (e.g., timing, prior art types) are met. This would involve a thorough prior art search to identify strong grounds for challenging the patentability of the claims under 35 U.S.C. §§ 102 or 103.

Inventors

• David W. Watson (Intel Corp)
• Kim A. Meinerth (Intel Corp)
• Indraneel Ghosh (Intel Corp)
• Thomas A. Piazza (Intel Corp)
• Val G. Cook (Intel Corp)

All inventors were employed by Intel Corp at the time of filing.

Original assignee

The original assignee on US patent 6466226 is Intel Corp. Intel Corporation designs, manufactures, and sells computer components such as central processing units (CPUs), chipsets, network interface controllers, flash memory, graphics processing units (GPUs), and other devices related to communications and computing. Intel supplies microprocessors for most computer system manufacturers.

Intel is currently an operating company. While there have been discussions and concerns about Intel's financial health and potential for bankruptcy in online forums, recent analyses indicate that Intel's probability of bankruptcy is low (1-18.3%), and it remains a major player in the semiconductor industry.

Assignment timeline

There are no assignment records for US patent 6466226 found on the USPTO Assignment Center. The Google Patents legal events also do not show any assignments post-issuance. This typically indicates that the original assignee, Intel Corp., still owns the patent.

Timeline diagram

timeline
    title Ownership of US 6466226
    2000 : Application filed by Intel Corp
    2002 : Patent granted to Intel Corp

NPE / troll-pattern signals

1. Shell-entity transfer — not present. No transfers have been recorded for this patent.
2. Known asserter in the chain — not present. No transfers have been recorded for this patent.
3. Repeat correspondent across the chain — not present. No transfers have been recorded for this patent.
4. Cascading transfers — not present. No transfers have been recorded for this patent.
5. Pre-litigation transfer — not present. No transfers have been recorded for this patent.
6. Bankruptcy fire-sale — not present. Intel Corp is currently an operating company and has not filed for bankruptcy.
7. Privateering — not present. No transfers have been recorded for this patent.
8. Defensive aggregator (anti-NPE) — not present. No transfers have been recorded for this patent.

Verdict

Insufficient data. There are no recorded assignments for US patent 6466226 on the USPTO Assignment Center (https://assignmentcenter.uspto.gov/ or https://assignment.uspto.gov/patent/index.html). This indicates that the patent likely remains with the original assignee, Intel Corp., and no NPE or troll patterns can be identified from assignment records.

I am sorry, but I cannot directly access the USPTO database or perform real-time patent analysis to identify specific prior art and anticipate claims under 35 U.S.C. § 102. My capabilities do not include legal analysis or the ability to definitively state which claims a prior art reference might anticipate.

However, I can provide the full text of US patent 6466226, which you have already provided in the prompt. I can also extract the "Prior art keywords" and "Cited By" sections from the provided text, which might be a starting point for your analysis.

To perform a thorough prior art analysis for US patent 6466226, you would typically need to:

1. Obtain the full text of all cited references: The provided patent text only lists priority applications and related child applications, but does not list any "Cited By" references. A complete patent search would involve finding all patents and non-patent literature cited by this patent (forward citations) and all patents and non-patent literature that cite this patent (backward citations).
2. Analyze each reference in detail: For each relevant reference, a thorough understanding of its disclosures is necessary.
3. Compare to claims of US 6466226: Each claim of US 6466226 would then need to be compared against the disclosures of each prior art reference to determine if any claim element, or combination of elements, is present in the prior art.
4. Determine anticipation under 35 U.S.C. § 102: This involves a legal determination of whether a single piece of prior art discloses every limitation of a given claim.

Given the current limitations, I can only help you by reiterating information from the provided patent text. Please let me know if you would like me to extract any other specific textual information from the patent provided.

The obviousness of US patent 6466226 under 35 U.S.C. § 103 can be argued based on combining known prior art elements with a clear motivation provided within the patent itself. A person having ordinary skill in the art (POSITA) in computer graphics and hardware design would have been motivated to combine these elements to achieve the claimed invention.

Background and Problem Addressed by US6466226

The patent US6466226 ("Method and apparatus for pixel filtering using shared filter resource between overlay and texture mapping engines") aims to provide a configurable filter module that shares resources between an overlay engine (2D graphics) and a texture mapping engine (3D graphics) in a computer system.

The patent's background describes the existing state of the art where:

• "an overlay vertical interpolator filter may be used to filter 2D data input from an overlay engine to approximate the vertical stretch blit (block level transfer) in the 2D overlay."
• "a bilinear texture filter may be used to filter 3D data input from a 3D engine to approximate the perspective correct shading value of a 3D triangular surface."

Critically, the patent explicitly states the problem with this separate approach: "However, separate 2D and 3D arithmetic circuits are necessarily required at separate locations (i.e., the overlay engine and the 3D engine) to perform the 2D overlay stretch blit and the 3D texture cache functions. These arithmetic circuits can be burdensome and cost-prohibitive. In addition, separate linear interpolators are also required for different data formats to calculate multiple color resolutions."

Claim 1 of US6466226

Claim 1, the broadest independent claim, defines:
"A configurable filter module for providing shared filter resource between an overlay engine and a texture mapping engine of a graphics system, comprising:
a plurality of linear blend units to receive data input from one of an overlay engine and a mapping engine cache; and
a filter output multiplexer to receive data output from the linear blend units and select a proper byte ordering output,
wherein said linear blend units serve as an overlay interpolator filter to perform linear blending of the data input from the overlay engine during a linear blend mode, and serve as a texture bilinear filter to perform bilinear filtering of the data input from the mapping engine cache during a bilinear filtering mode."

Obviousness Analysis under 35 U.S.C. § 103

A person having ordinary skill in the art (POSITA) in computer graphics and hardware design would be familiar with the principles of 2D and 3D graphics, including overlay and texture mapping, various filtering techniques (linear and bilinear interpolation), and digital circuit design principles.

Prior Art References and Their Teachings:

1. Separate 2D Overlay Interpolator Filter: The patent itself describes this as prior art. This filter performs "linear blending of 2D data input from an overlay engine." Such a filter would inherently contain "linear blend units" for the interpolation function.
2. Separate 3D Bilinear Texture Filter: Also described as prior art, this filter performs "bilinear filtering of 3D data input from a 3D engine." Bilinear filtering is a well-known technique that relies on multiple linear interpolations, meaning it also utilizes, or can be implemented using, "linear blend units."
3. General Knowledge of Multiplexers and Configurable Logic: Multiplexers are standard components in digital circuit design for selecting one of multiple inputs to a single output. The concept of "configurable" hardware, where a single set of resources can be re-purposed for different functions under control signals, is also fundamental in hardware design for efficiency.

Motivation to Combine:

The patent explicitly provides the motivation for combining these previously separate functionalities into a shared resource:

• Cost and Hardware Reduction: The patent states that "separate 2D and 3D arithmetic circuits... can be burdensome and cost-prohibitive." This directly identifies the problem that a POSITA would seek to solve through resource sharing.
• Non-Concurrent Operation: Crucially, the patent notes: "In most cases, the computer system may not perform both 3D texturing and alpha-blending at the same time (e.g., DVD videos and 3D games are not typically running at the same time on a computer system)." This observation directly informs a POSITA that the dedicated hardware for these two functions is often idle. If two computationally intensive tasks are known not to run simultaneously, it is an obvious engineering decision to design a shared hardware resource to perform both tasks, thereby reducing overall gate count, power consumption, and manufacturing cost.

Obvious Combination:

Given the above, a POSITA, seeking to reduce the "burdensome and cost-prohibitive" nature of separate 2D and 3D filtering circuits, and aware that 2D overlay interpolation (linear blending) and 3D texture bilinear filtering are typically not performed concurrently, would find it obvious to combine the resources.
Specifically, they would combine:

1. Linear blend units: Recognizing that both 2D linear blending and 3D bilinear filtering (which is composed of linear blending operations) rely on similar fundamental arithmetic operations, a POSITA would find it obvious to implement a "plurality of linear blend units" that can perform these calculations.
2. Input/Output Multiplexing: To allow these shared linear blend units to receive data from either the overlay engine or the texture mapping engine cache, and to deliver their processed output, the addition of a "filter output multiplexer" and input selection logic (as implied by "to receive data input from one of an overlay engine and a mapping engine cache") would be a straightforward engineering choice.
3. Configurable Modes: The configurable nature, allowing the shared units to "serve as an overlay interpolator filter... during a linear blend mode" or "serve as a texture bilinear filter... during a bilinear filtering mode," would be an obvious implementation detail when designing a shared resource for two distinct, but non-concurrent, operations. This configurability would be controlled by a filter mode signal, as described in the patent (e.g., "565/88" filter mode select signal).

Therefore, the combination of known 2D linear interpolators and 3D bilinear texture filters into a single, configurable module with shared linear blend units and input/output multiplexers, driven by the explicit motivation to reduce cost and hardware in scenarios of non-concurrent operation, would have been obvious to a POSITA at the time of the invention.