Invalidity dossier
US 6170051
Apparatus and method for program level parallelism in a VLIW processor
Current assignee: Round Rock Research LLC
Added 9/23/2026, 4:59:02 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 6,170,051 B1
Title: "Apparatus and method for program level parallelism in a VLIW processor"
Source: https://patents.google.com/patent/US6170051/en
Identifiers and dates (per supplied text): Application US08/996,526; filed 1997-12-23; priority date 1997-08-01; granted/publication date 2001-01-02; anticipated expiration 2017-12-23; legal status "Expired – Lifetime." Inventor: Eric M. Dowling. Original assignee: Micron Technology Inc; current assignee listed as Round Rock Research LLC. Note: the "priority to US08/996,526" and "priority to US09/653,641" entries appear in the supplied record exactly as shown.
Field and purpose: The definitions section states the invention "relates to the field of microprocessor architecture," specifically "high performance processors such as digital signal processors that use very long instruction words (VLIW) or employ superscalar architectures."
Plain-language scope (excerpt): The text defines "program level parallelism" as including "task oriented parallelism and multithreading," and explains that in program level parallelism "different tasks are executed on different processors, so that the server handles more users, but no one user's program can finish faster" (sentence truncated in the supplied excerpt). Recurring "prior art keywords" listed are: processor, instruction, functional units, register, register file. Classifications include G06F9/38 and subclasses (concurrent instruction execution, prefetching, instruction issuing/multistreaming, multiple independent parallel functional units), G06F9/30 subclasses (arithmetic instructions, register arrangements/banked or distributed register files), and G06F15/7867 (reconfigurable architecture).
What the excerpt does not establish: The supplied text does not include the claims, the written description body, drawings, or any prior-art references beyond the keyword list, so the specific claimed apparatus/method, its limitations, and its novelty are not verifiable here. The excerpt provides no basis for statements about litigation, ownership validity, patentability, or how the described techniques were implemented. The VLIW/program-level-parallelism terminology is excerpted only partially and should be read against the full source. Assignee listings are expressly noted in the source as possibly inaccurate, and legal status is stated there to be an assumption, not a legal conclusion.
Generated 10/1/2026, 9:43:58 PM
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Litigation summary
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Proceedings on file (0)
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PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
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Obviousness
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Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.