US 6008796

I'll search for authoritative information on this patent number and any 2026 CAFC activity.

Summary of US Patent 6,008,796

A note on scope and method. I pulled the authoritative full text of this patent (Google Patents, fetched 2026-09-24) and ran targeted searches for litigation/CAFC activity. No results tied US 6,008,796 to any Court of Appeals for the Federal Circuit docket in 2026. I flag that as a negative finding on the available searches, not a certified absence.

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Bibliographic data (from the patent record)

Assignee note: the metadata lists S3 Graphics Co Ltd as current assignee and S3 Inc as original assignee; the assignment events in the record show Cirrus Logic as an intermediate holder. I report these literally rather than reconciling them.

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Abstract (as issued)

An improved method and apparatus for rendering curved surfaces in a graphics system, in which each primary color is represented with fewer than eight bits. An eight-bit color shade value is truncated; the most significant bits are saved and used as a color value, and the truncated least significant bits are used to determine which of the adjacent color values to use to render pixels. The three truncated bits select an entry from a ramp table, and a control signal from a look-up table selects a bit from that entry. The selected bit determines which of the closest five-bit shades is used. The invention may be implemented in software.

Technical gist

The patent addresses "banding" in 5-6-5 (and similar) color graphics, where truncated low-order bits are discarded. Instead of randomly dithering pixels, the FRAC (truncated bits) encodes how far the desired 8-bit shade sits above the nearest representable shade; that distance is encoded as the number of logic-1s in a "ramp" value, and an ordered 8×8 look-up table (driven by pixel x/y address bits) selects one ramp bit. The probability that the selected bit is 1 equals the fraction of pixels that should take the next-higher shade — giving a controlled blend rather than a random one. An overflow signal from the add logic disables dithering to avoid rendering an erroneous shade.

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Independent claims — plain language

Claim 1 — Method (color dithering with <8-bit shades).
Steps: (a) generate an 8-bit desired shade per pixel; (b) truncate it to a shorter shade value; (c) derive a FRAC value from the truncated bits; (d) produce a "rap value" (the claim text literally reads "rap value" — an apparent typo for "ramp value" in the issued claim) from that FRAC, where the ramp value encodes the discrepancy between the 8-bit desired shade and the truncated shade; (e) map a dither value to a bit position within the ramp value; and (f) use a bit from the ramp value to select a sub-8-bit shade that fixes each pixel's color.

Claim 6 — Method (two-shade selection with addend/increment).
Same front end as Claim 1, but adds: produce an addend value to increment the first (truncated) shade; increment it to get a second shade; map a dither value to a ramp bit position; and select either the first or the second shade to color each pixel. Claim 7 clarifies the ramp value carries a number of logic-1s indicative of the discrepancy; Claim 8 says the selection responds to the state of a ramp bit; Claim 9 ties the bit selection to a look-up table addressed by pixel x/y; Claims 10–11 cover the overflow signal and its use.

Claim 12 — Graphics system (apparatus).
A system receiving an 8-bit desired representation with upper- and lower-order bits, comprising: select fractional logic that outputs the lower-order (truncated) bits; a look-up table producing a control value based on a pixel address; ramp probability logic producing a ramp value that encodes the discrepancy between the 8-bit representation and the sub-8-bit representation; and mapping logic that maps the look-up-table value to a bit position within the ramp value. Dependent claims add an addend generator (13), add logic (14), a first multiplexer for ramp-bit selection (15), and a second multiplexer for shade selection (16).

Claim 22 — Computer-readable storage medium (software).
A storage medium holding executable instructions that, when loaded into a host computer, dither pixel colors in a system using sub-8-bit color values. The instructions include: means for determining a first look-up-table index value; means for providing a LUT value from that index; means for determining a ramp probability value; means for mapping the LUT value to a bit position within the ramp probability value; and means for selecting a dither color value. The chain of dependents (23–35) recites two index values derived from pixel addresses, use of the least-significant three bits (address AND 7, plus an offset), the bit-shift/row-selection math for the LUT, computing the ramp as 2^FRAC − 1, shifting and masking to obtain the dither increment, left-shifting to form an addend, adding it to a color value, and setting the dither value equal to the color value on overflow.

Claim 36 — Method (software-style LUT/ramp mapping).
The method mirror of Claim 22: determine a first LUT index value; obtain the LUT value; determine a ramp probability value that encodes the discrepancy between an 8-bit color value and a sub-8-bit color value; map the LUT value to a bit position within the ramp probability value; and use the value at that bit position to determine the dither color value. Dependent claims 37–49 track the same limitations as 23–35.

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Observations and uncertainties

• Claim-drafting artifacts. The issued claim text contains apparent typographical inconsistencies (e.g., "rap value" in Claim 1(d); internal cross-references to "step g"/"step e" that do not align with the lettered steps in Claims 4 and 8). I am reporting the literal text, per the instruction not to auto-correct identifiers or wording.
• Prior art cited (32–33 references) includes ordered-dither and grayscale-display art, notably US 4,956,638 (IBM, "Display using ordered dither"), US 5,185,602 and US 5,298,915 (Cirrus Logic), US 5,469,190 (Apple, 24-bit to 15-bit color conversion), US 5,553,200 (Electronics For Imaging, dither arrays), and US 5,201,030 (Sun Microsystems, dithering graphic images). Much of the list is General Electric computer-image-generation art.
• Post-issuance citations of note include Lexmark's dithered-quantization patents (US 6,809,740; US 7,126,611), EPFL's multi-color dithering patent (US 7,054,038), and Sony Ericsson's color-resolution patents (US 8,081,194 and family).
• CAFC / 2026 docket: I found no Federal Circuit or district-court docket naming US 6,008,796 in 2026. Given the patent's anticipated expiration on 2016-12-30, contemporaneous 2026 appellate activity would be unusual. I cannot certify the absence of such a docket from public search alone — treat this as "not found," not "confirmed none."

If you need the actual claim charts, prosecution history, or a docket-level confirmation (e.g., via USPTO PatentCenter / PACER / Docket Alarm), those would require direct database queries beyond the searches run here.

I'll search for litigation involving US patent 6008796 specifically.

The initial results returned unrelated patents (a Neonode '879 patent and a Japanese JP6008796 for Honda). Let me search more specifically for the US patent number and its owners.

Let me try more targeted searches on litigation databases and specific case references.

Litigation Search: US Patent No. 6,008,796

Bottom line: I found no litigation specifically asserting U.S. Patent No. 6,008,796. Based on the searches I was able to run, there is no publicly indexed district court, ITC, or Federal Circuit case in which this patent is identified as an asserted patent.

Important note on search contamination

My searches for the literal number "6008796" surfaced two results that are not the patent at issue, and I am explicitly excluding them per the instruction not to substitute similar numbers:

• JP 6008796 B2 — a Japanese Patent Office registration (Patent No. 6008796, app. 2013-113896, issued 2016-10-19) to Honda Motor Co. directed to an internal-combustion-engine control device. This is a different patent in a different jurisdiction.
• Neonode Smartphone LLC v. Apple Inc., No. 3:21-cv-08872 (N.D. Cal.) and related IPRs — these concern a '879 patent, not the '796 patent. Different number.

Neither should be mistaken for US 6,008,796.

What the record does show about the patent's family

US 6,008,796 ("Software-based dithering method and apparatus using ramp probability logic"):

• Inventors: Gautam Vaswani, Daniel P. Wilde, Thomas Dye
• Original assignee: S3 Incorporated (assignment history: Cirrus Logic → S3 Incorporated → SONICblue → S3 Graphics Co., Ltd.)
• Filed 1997-05-15; granted 1999-12-28
• Continuation-in-part of Ser. No. 08/777,557 (filed 1996-12-30), which issued as US 6,088,016 ("Dithering method and apparatus using ramp probability logic")

Contextual litigation involving the same assignee (not this patent)

S3 Graphics' well-known litigation asserts other patents, which I located but which do not include '796:

None of these assert '796 or '016.

Caveats on completeness

I was unable to run an exhaustive docket-level query (e.g., direct searches of Unified Patents' litigation portal, PACER, Docket Navigator, or Lex Machina APIs) before exhausting my search budget. Therefore:

• I cannot affirmatively certify that no case ever asserted '796 — only that no such case surfaced in the searches I performed, and that the indexed S3 Graphics/S3 Graphics-era litigation I found involves different patent numbers.
• Given the patent expired 2016-12-30 (anticipated expiration) and its subject matter (1990s color-dithering for 5-6-5 graphics), large-scale assertion campaigns are unlikely, but this is inference, not confirmation.

Recommendation: To definitively confirm, query PACER's nationwide case search and the Unified Patents litigation portal using the exact string "6,008,796" / "6008796" as a party-document search term, and cross-check via Docket Navigator or Lex Machina. If you'd like, I can attempt those specific queries.

I'll start by verifying the structured-data finding against public sources before writing anything up.

Let me check for any litigation/enforcement history and Federal Circuit activity tied to this patent.

Proceedings overview

Zero AIA trial proceedings on file. The structured PTAB block supplied for this analysis reports that the USPTO Open Data Portal (ODP) returns no AIA trial proceedings — IPR, PGR, or CBM — against US 6,008,796 as of the most recent ingest, and my independent searches surfaced no petition, institution decision, Final Written Decision, or Federal Circuit appeal naming this patent; the bottom-line defensive posture is therefore not "hardened by surviving IPRs" but rather "the patent has never been tested at the PTAB and, more decisively, its entire enforceable term has already run out."

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Note on the structured source and the absence of per-proceeding entries

The task asks me to enumerate each proceeding most-impactful-first. There are no proceedings to enumerate. I am not manufacturing case numbers to fill the schema. What follows is the diligence trail and the resulting defensive posture, which is the analytically useful output here.

Canonical source: the "PTAB proceedings on file" block in the prompt, derived from the USPTO Open Data Portal. Content, quoted: "The USPTO ODP API returns no AIA trial proceedings for this patent as of the most recent ingest." Default rule applied: no PTAB activity on file.

Independent verification attempted:

Consistency check against the earlier-generated section. The prior "Patent summary" section found no 2026 CAFC docket and flagged that as a negative finding. That is consistent with this section; no contradiction to report. I reach the same conclusion from the PTAB side.

Caveat, stated plainly. Zero hits against a patent number in public search is a negative finding on the searches run, not a certified absence. A pre-AIA-era docket (e.g., a 2001–2013 CBM-adjacent or reexam filing) could in principle exist in records ODP did not ingest. To certify absence, query PTAB E2E directly at https://ptacts.uspto.gov/ptabweb/ under "Patent Number 6008796" and cross-check the patent's full file wrapper in USPTO PatentCenter. I did not have database-level access to do that here.

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Strategic summary

Claim status: all 49 claims are UNTESTED, but the untested window is closed. No claim of US 6,008,796 has ever been canceled, confirmed, or construed in an AIA trial. That is not good news for the patent owner. The patent issued 1999-12-28 from an application filed 1997-05-15, claiming priority to 1996-12-30, and the record lists an anticipated expiration of 2016-12-30 with legal status Expired – Lifetime. Independent claims 1, 6, 12, 22, and 36 and their dependent chains stand unadjudicated by the Board, but they also stand unenforceable as to any post-2016 conduct. Under 35 U.S.C. § 286, damages reach back only six years from suit — from a 2026 filing, that is conduct occurring on or after roughly 2020, which post-dates expiration entirely. A defendant receiving a 2026 demand letter citing this patent has a near-complete temporal defense before reaching a single invalidity argument. This is the dominant fact, and it makes the invalidity analysis mostly academic.

Estoppel landscape: § 315(e)(2) is a null set, and that cuts both ways. Because no IPR or PGR ever reached a Final Written Decision, no petitioner, real party in interest, or privy is estopped as to this patent. There is no estoppel floor and no estoppel ceiling — which sounds favorable to a challenger, but the practical effect is that there is no live challenger, no adverse FWD to leverage, and no PTAB claim construction to point to. Conversely, because the asserted-lifetime is over, spending $150K–$350K on an electrical/computer IPR petition (per the AIPLA Report of the Economic Survey 2023 figures reflected in the PTAB rulemaking commentary) to invalidate an expired patent would be economic malpractice. IPR remains statutorily available against an expired patent, but it buys a defendant nothing that the expiration date does not already give it for free.

Pattern signals: the enforcement pattern is the tell. S3 Graphics (and its VIA/HTC-affiliated predecessors) were serial and aggressive enforcers in 2010–2011, running an ITC § 337 campaign and parallel Delaware actions against Apple, and later litigating through a corporate-succession dispute in which AMD/ATI claimed ownership of certain S3 Graphics patents. Yet across that entire campaign the asserted patents were the '997, the '279, the '978, the '146, the '440, and an "'960" — never the '796. No defensive aggregator (e.g., Unified Patents) appears in the chain, and there is no petition trail on this patent at all. Read together: the '796 was not a patent even its own owner chose to assert. Combined with expiration in 2016 and the S3 Inc. → SonicBlue → S3 Graphics Co., Ltd. → (VIA/HTC orbit) assignment drift, this is a low-value, unasserted asset — precisely the profile that attracts late-stage demand-letter activity from assignees or brokers rather than genuine litigation.

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Recommended next steps

If you are a defendant and a demand letter cites US 6,008,796:

1. Lead with the date, not the prior art. Check the demand's infringement dates. The patent's anticipated expiration is 2016-12-30 and its legal status is Expired – Lifetime. Any accused conduct after that date cannot infringe; conduct before it is likely time-barred under § 286's six-year lookback. Demand the specific accused acts and their dates before engaging on the merits.
2. There is no FWD to link to. Unlike the typical "claims 1–5 canceled, quote the disposition" scenario, here I cannot link to a PTAB Final Written Decision, because none exists. Do not let opposing counsel imply otherwise; if they cite a PTAB outcome for the '796, that citation is fabricated and is sanction-bait in the reverse direction — it is their representation to verify.
3. Check ownership/standing. The assignment record is unusually tangled (Cirrus Logic → S3 Incorporated → SonicBlue name change → S3 Graphics Co., Ltd.), and the family shows a related corporate-succession ownership fight in the Apple litigation in which AMD/ATI asserted ownership of certain S3 Graphics patents. Confirm the current claimant actually holds title and the right to sue. The Google Patents listing of "S3 Graphics Co., Ltd." as current assignee is metadata, not proof of standing.
4. Confirm the negative finding at the source. Before relying on it in correspondence, pull the PatentCenter file wrapper and the PTAB E2E docket for patent number 6008796 and confirm the absence of AIA trials, reexaminations, and any post-issuance certificate.

If you are evaluating this patent as a defensive prior-art asset: note that the '796 is a continuation-in-part of US 08/777,557, which issued as US 6,088,016 ("Dithering method and apparatus using ramp probability logic," 25 claims) and is likewise Expired – Lifetime. Both are unusable as assertable patents now, and both are fair game as printed publications / prior-art patents with a 1996-12-30 priority date against later-filed dithering claims — that is the only residual value in this family.

Key links: PTAB E2E — https://ptacts.uspto.gov/ptabweb/ · USPTO PatentCenter — https://patentcenter.uspto.gov/ · CourtListener — https://www.courtlistener.com/ · Patent record — https://patents.google.com/patent/US6008796/en

I'll research the assignment record for US 6,008,796. Let me run several targeted searches.

Let me search more specifically for this patent's ownership and any assertion history.

Let me try to pull the actual assignment records and their correspondents.

I've reached the search-step limit, so the below is built strictly from the authoritative full text (Google Patents legal‑events block, which carries the recorded reel/frame strings) plus the litigation/ownership facts surfaced by search. I could not retrieve the correspondent of record for any of this patent's specific reel/frame entries — I flag that as a data gap rather than guess.

Assignment & ownership reconstruction — US 6,008,796

Inventors

Pattern note. All three inventors executed their assignment to Cirrus Logic, Inc. on 1997‑05‑13 (recorded 1997‑05‑15, reel 008563/0724) — i.e., the inventors' rights were never held by the entity named on the patent face. That is because Cirrus Logic transferred the rights to S3 Incorporated roughly ten months later. The "all inventors departed the original assignee" tell is not present here: the inventors' employer (Cirrus Logic) was not the face assignee to begin with; the change was a corporate transfer of the graphics business, not inventor attrition. I cannot determine individual departure dates from the sources searched.

Original assignee

S3 Inc (listed as S3 Incorporated on the issued record) — named as original assignee on the face of US 6,008,796.

• Primary line of business: PC graphics accelerators / chipsets (e.g., Trio, ViRGE, Savage families). This is an operating company, and it shipped products in the relevant period; the patent's own spec names a Cirrus Logic CL‑GD546X part, consistent with the graphics‑chip business that moved into S3.
• Did it ship products embodying the claims? The claims are a software‑based dithering method/apparatus; S3 shipped graphics drivers and accelerators of the relevant era. I cannot confirm that any specific shipping S3 product practiced the claims of the '796 patent — treat as plausible but unverified.
• Current status: Renamed/dissolved. The legal‑events record shows a change of name from S3 Incorporated → SONICblue Incorporated, effective 2000‑11‑09 (reel 019825/0493). SONICblue is a defunct consumer‑electronics company whose assets (ReplayTV, Rio) were sold and which entered bankruptcy proceedings (a "Sonicblue Claims, LLC" and a bankruptcy claim transfer appear in VIA Technologies, Inc. v. Sonicblue Claims, LLC). The graphics‑chip business was carved into the S3 Graphics joint venture with VIA Technologies around 2000‑2001.

Assignment timeline

Recorded assignments from the USPTO legal‑events record (reel/frame strings as they appear in the record). Correspondent of record is not exposed in the sources I could reach for any of these entries — flagged individually. I did not fabricate any names.

• 1997‑05‑13 executed / recorded 1997‑05‑15 — Reel 008563/0724

  • Conveyance: Assignment (ASSIGNMENT OF ASSIGNORS' INTEREST)
  • Assignor: Daniel P. Wilde; Thomas Dye; Gautam Vaswani (inventors)
  • Assignee: Cirrus Logic, Inc. (California)
  • Correspondent: not retrievable from sources searched (Google Patents legal events does not expose the correspondent/signatory)
  • Context: employment/asset assignment — inventors' rights to their then‑employer, Cirrus Logic.

• 1998‑03‑13 executed / recorded 1998‑06‑16 — Reel 009267/0702

  • Conveyance: Assignment
  • Assignor: Cirrus Logic, Inc.
  • Assignee: S3 Incorporated (California)
  • Correspondent: not retrievable
  • Context: corporate transfer — movement of the graphics‑related portfolio from Cirrus Logic to S3 (the transaction that put S3's name on the issued patent).

• 2001‑01‑03 effective / recorded 2002‑05‑07 — Reel 012852/0016

  • Conveyance: Assignment
  • Assignor: SONICblue Incorporated (successor by name change to S3 Incorporated)
  • Assignee: S3 Graphics Co., Ltd. (Cayman Islands)
  • Correspondent: not retrievable
  • Context: transfer‑to‑holding/JV entity — the S3 Graphics joint venture (SONICblue + VIA Technologies) that took the graphics‑chip business. This effective date (2001‑01‑03) is the same Jan‑2001 JV assignment litigated in S3G v. ATI; see signals below.

• Effective 2000‑11‑09 / recorded 2007‑09‑15 — Reel 019825/0493

  • Conveyance: Change of Name
  • Assignor: S3 Incorporated
  • Assignee: SONICblue Incorporated
  • Correspondent: not retrievable
  • Context: change of name only (no change in beneficial ownership).

Two anomalies worth flagging (cross-reference against the prior summary's assignment chain — no contradiction, but a documented miscitation of dates):

1. Late name‑change recording. The S3→SONICblue name change (effective 2000‑11‑09) was not recorded until 2007‑09‑15, i.e. after the 2002 assignment of the patent to S3 Graphics Co., Ltd. (reel 012852/0016). So the recorded chain shows the property leaving "SONICblue" before the USPTO had any recorded instrument establishing that "SONICblue" = "S3 Incorporated." This is a classic chain‑of‑title hygiene gap.
2. Standing was actually litigated. The related S3TC patents descending from US 5,956,431 were the subject of S3 Graphics Co. Ltd. v. ATI Technologies ULC (D. Del. 1:11‑cv‑01298) and ITC Inv. 337‑TA‑724. AMD/ATI argued S3G's Jan‑2001 assignment covered only the Schedule‑A patents, that the asserted patents were not included, and that S3G's chain broke. The Delaware court ultimately ruled for S3G (Finnegan summary: plaintiff owns the disputed patents; defendants have no ownership or express license). The same Jan‑2001 instrument (effective 2001‑01‑03) is the assignment recorded at reel 012852/0016 for the '796 patent — so the validity of the instrument that carries this patent's title was contested and upheld.

Parent/related filing. This patent is a continuation‑in‑part of Ser. No. 08/777,557, which issued as US 6,088,016 ("Dithering method and apparatus using ramp probability logic"), also shown as S3 Incorporated. The parent has its own (separate) assignment record — not consolidated here.

Timeline diagram

timeline
    title Ownership of US 6008796
    1997 : Inventors assign to Cirrus Logic
         : Reel 008563/0724
    1998 : Cirrus Logic transfers to S3 Incorporated
         : Reel 009267/0702
    1999 : Patent issues naming S3
    2000 : S3 Inc renamed SonicBlue Inc
    2001 : SonicBlue transfers to S3 Graphics Co Ltd
    2002 : S3G assignment recorded reel 012852/0016
    2003 : SonicBlue enters bankruptcy
    2007 : S3 name change recorded reel 019825/0493
    2011 : S3G asserts graphics portfolio vs Apple at ITC
    2016 : Patent expires

NPE / troll‑pattern signals

1. Shell‑entity transfer — unclear / partial. The patent moved from operating company SONICblue to S3 Graphics Co., Ltd. (Cayman Islands) at reel 012852/0016 (eff. 2001‑01‑03 / rec. 2002‑05‑07). S3 Graphics Co., Ltd. is a holding company, but it was a joint venture of operating companies (VIA + SONICblue) with an operating design subsidiary (S3 Graphics Inc., Fremont CA). So the "anonymous single‑purpose Delaware/Texas LLC" tells are not present. Call it partial.

2. Known asserter in the chain — not present (as listed). Neither S3 Graphics Co., Ltd. nor its predecessors appear on the enumerated NPE directories (Acacia, Marathon, IV, IPNav, Wi‑LAN/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation, Spangenberg, etc.). However, S3G did run a high‑profile assertion campaign (ITC 337‑TA‑724 vs Apple, 2010‑2011; see also AMD v. S3 Graphics, D. Del. 1:11‑cv‑00965). Facts, not naming.

3. Repeat correspondent across the chain — insufficient data. I could not retrieve the correspondent of record for any of reel 008563/0724, 009267/0702, 012852/0016, or 019825/0493 from the sources searched. The correspondents that did surface (S. Kareff / Schulte Roth & Zabel for Acacia‑Monarch; John G. Rauch / Brinks Gilson & Lione for Excalibur IP; Convergence IP Law for R2 Solutions) belong to unrelated patents and must not be attributed here. Signal = unclear.

4. Cascading transfers — not present. The four recorded conveyances span 1997 → 2007 (the substantive ones, 1997→2002), i.e. well over 24 months with no chained‑LLC relay and no shared‑correspondent cluster that I can establish.

5. Pre‑litigation transfer — not present. The last substantive transfer to S3G (rec. 2002‑05‑07) predates the 2010‑2011 ITC action by ~8 years, and US 6,008,796 was not among the patents asserted in 337‑TA‑724 (asserted: 6,658,146; 6,683,978; 6,775,417; 7,043,087). No 6‑month‑before‑suit transfer exists for this patent.

6. Bankruptcy fire‑sale — partial. Corporate successor SONICblue entered bankruptcy (assets sold: ReplayTV/Rio to D&M; "Sonicblue Claims, LLC" liquidation vehicle). But the '796 patent had already been recorded to S3G in 2002, before the 2003 proceedings, so the patent was not sold through the bankruptcy estate. Contextual signal only.

7. Privateering — present (moderate). VIA Technologies, an operating chip designer, formed/controlled S3 Graphics and the portfolio was asserted by S3G against Apple, a competing platform, at the ITC and in district court. That is the classic "operating company asserts through a controlled vehicle" shape — though S3G also had its own chip business for part of the period. In 2011 HTC agreed to acquire S3 Graphics from VIA (reported ~$300M) to bolster its own patent position — a defensive/portfolio purchase, not a classic troll acquisition. (Deal terms were subsequently restructured; I cannot confirm final closing from the sources searched.)

8. Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. S3G was sold to HTC (an operating handset maker) — a private defensive holder, not a public aggregator.

Verdict

NPE — moderate confidence.

Justification: two weaker signals co‑occur — (i) the substantive transfer of the patent to S3 Graphics Co., Ltd., a Cayman Islands holding company, at reel 012852/0016 (eff. 2001‑01‑03 / rec. 2002‑05‑07), which holds legal title without itself making products, and (ii) privateering‑style use of that vehicle by an operating parent (VIA) to assert the graphics portfolio at the ITC (337‑TA‑724) and in D. Del. against Apple/competitors. Against that, the strong NPE tells are absent or unavailable: no transfer to a licensing‑only LLC, no §‑matching to a known NPE directory, no correspondent data, no sub‑24‑month cascade, no pre‑litigation transfer, and no public defensive‑aggregator endpoint (the portfolio went to the operating handset maker HTC, not RPX/AST). The chain is also best characterized as a corporate restructuring history (inventor → Cirrus Logic → S3 → SONICblue → S3 Graphics JV) rather than a manufactured troll chain, and the patent’s own instrument of title (the Jan‑2001 assignment) was litigated and upheld in S3G v. ATI. Because 2+ weak signals are present and no strong single signal is, "moderate confidence" is the honest call — and note the patent expired 2016‑12‑30, so any current assertion value is nil.

Verify at: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search patent number 6008796) and https://assignment.uspto.gov/patent/index.html. Compare reel/frame 008563/0724, 009267/0702, 012852/0016, 019825/0493, and pull the correspondent fields there, which I could not retrieve.

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Data gaps / cautions (stated plainly rather than papered over):

• Correspondent of record for all four reel/frame entries is unavailable in the sources I reached; signal 3 is therefore unclear, not "not present."
• The reel/frame strings are quoted from Google Patents' legal‑events block; I did not independently open the Assignment Center image for each and confirm the integer strings.
• Whether US 6,008,796 was listed on Schedule A of the Jan‑2001 assignment (vs. added later via the 2006 Amended Assignment that the D. Del. record discusses for the S3TC patents) is not established for this specific patent — the PTO record shows it assigned to S3G at reel 012852/0016, but I did not verify the underlying schedule.
• The HTC–VIA S3 Graphics transaction's final status is reported from press coverage only (July 2011 announcement, ~$300M) and is not confirmed from a primary filing.

I'll run targeted searches to ground the prior-art analysis against authoritative sources.

Prior-art analysis for US 6,008,796

Method note. I searched for the patent and each cited reference. US 6,008,796's face lists 32–33 U.S. references plus WO 96/36011 (Google Patents "Citations" tables; Justia US6008796). I assessed each entry below against that record and against the reference's own text/claims where retrievable. One important framing caveat up front: being listed on the patent's face does not mean the examiner applied a reference under § 102. Apparent anticipatory candidates are bolded; the large block of General Electric computer-image-generation art was cited as background to the 3-D polygon-shading field, not as anticipating art. All 33 references pre-date the 1996-12-30 priority date, so each is available as prior art under § 102(a)/(b) as a threshold matter.

I build on, rather than repeat, the claim mapping in the prior section (claims 1, 6, 12, 22, 36 independent; 7–11, 13–21, 23–35, 37–49 dependent).

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Tier 1 — Closest references; genuine § 102 candidates

1. US 4,956,638 A — "Display using ordered dither"

• Assignee/inventors: International Business Machines Corp. (Larky et al.); also published as EP 0 359 080 A2/B1.
• Dates: filed 1988-09-16 (US 07/245,857); granted 1990-09-11. (Google Patents, Justia)
• Description: Per-primary-color dither apparatus: a look-up table (Fig. 6) responds to a color-select signal to output an integer signal and a fraction signal; the integer is fed to an incrementer; a dither matrix produces a dither signal as a function of pixel position; a comparator compares the dither signal to the fraction and a multiplexor selects the incremented vs. integer value. The LUT formula is desired * maxvalue/255, and an alternative embodiment (Fig. 8) eliminates the LUT.
• Potential §102 target claims: 1, 6, 12, 15, 16 (and 4/5's "look-up table + pixel address selects a bit" concept). This is the single most structurally similar reference in the list: the LUT→fraction/integer→incrementer→mux-compare chain reads on claims 12(d)–(f), 15, 16, and the "compare a stored pattern against a fraction to decide whether to increment the truncated shade" reads on claim 1(f) and claim 6(h). The key distinction the '796 patent relies on — encoding the fraction as a number of logic-1s in a multi-bit "ramp" value and selecting a single bit from it (claim 1(d),(e); claim 7) — is not disclosed by Larky, whose fraction is a multi-bit threshold compared directly. So Larky is a strong § 103 reference and a partial § 102 threat, but it does not squarely meet the ramp-value-bit-selection limitations.

2. US 5,469,190 A — "Apparatus for converting twenty-four bit color to fifteen bit color in a computer output display system"

• Assignee/inventor: Apple Computer, Inc. (Masterson, Anthony); JP counterpart JPH05298454A.
• Dates: filed 1991-12-23 (US 07/813,147); granted 1995-11-21. (Google Patents, Justia)
• Description: Converts 24-bit to 15-bit color by dropping the three lowest order bits and using a per-component decision circuit that receives the lowest-order bits and pixel-address bits to decide whether the five highest-order bits are incremented, producing the truncated value or the truncated-plus-one value per pixel — explicitly a dither. It contrasts simple truncation (up to 7 shades from the original) with round-up and interleaving, and produces 2×2 and 8×8 patterns. Claim 5 recites a comparator that disables the decision circuit when the five high-order bits are all ones (a saturation/overflow analog).
• Potential §102 target claims: 6, 10/11, 12, 13, 14 (and structurally 1(b),(f)). The truncate-lowest-3-bits + selectively-increment-by-one + use truncated bits and pixel address to decide the mix reads directly on claims 6(b),(f),(g),(h) and on claims 12–14 (select logic lowers-order bits, addend/increment, address-driven selection). The "all-ones" disable of claim 5 is the functional ancestor of the '796 overflow-disable feature in claims 10, 11, 20, 21 (though note the '796 uses "overflow from add", not an all-ones compare).

3. US 5,185,602 A — "Method and apparatus for producing perception of high quality grayscale shading on digitally commanded displays"

• Assignee/inventors: Cirrus Logic, Inc. (Bassetti, Jr. et al.) — the '796's original assignee.
• Dates: filed 1989-04-10; granted 1993-02-09. Family: US 5,298,915 (granted 1994-03-29), US 5,313,224 (CIP), US 5,122,783. (Google Patents, FPO)
• Description: Produces grayscale via multiple brightness-setting waveforms (each a set of ON/OFF command bits, ≥5 bits, ≥6 waveforms) placed according to D×D phase-placement matrices; the fraction of "1" command bits in a waveform over the integration period sets perceived brightness. The number of ON bits in a waveform is probabilistically linked to the desired brightness — conceptually the "probability = count of 1s" principle the '796 claims encode in its ramp tables.
• Potential §102 target claims: 12, 17, 22 (the ramp-probability/mapping concept). The "number of logic ones determines the blend probability" idea is the '796's core (claims 7, 17); the '602 discloses generating brightness by the count of ON/OFF bits in a phase-placement pattern, i.e., the same statistical-blend principle, but in a frame-rate-modulation (temporal) context rather than a per-pixel ramp-value-plus-LUT-bit-select context.

4. US 5,553,200 A — "Method and apparatus for providing bit-rate reduction and reconstruction of image data using dither arrays"

• Assignee/inventor: Electronics For Imaging, Inc. (Accad); EP 0 840 978 B1; WO 96/27261.
• Dates: filed 1995-03-03 (US 08/398,369); granted 1996-09-03. (Google Patents, Justia)
• Description: Quantizes 8-bit components to M-bit codes by finding an interval index d and a normalized offset I", then dithering (comparing the offset to a threshold/dither array value indexed by pixel position) to choose code d or d+1. Reconstruction uses a look-up table addressed by the code plus the low-order pixel address bits (log₂K, log₂L LSBs) — a LUT-driven, address-bit-indexed dither approach explicitly named alongside the Bayer ordered-dither family.
• Potential §102 target claims: 22, 36 (software LUT method/medium claims) and their dependents 23–30, 37–44 (two index values from pixel addresses; least-significant bits address the LUT; bit-shift/mask to select the value). The claim language in 22/23/26/27 ("first index value," "lower order bits … determining said first and second index values," "least significant three bits") maps closely onto EFI's k=(i)mod(K), l=(j)mod(L) addressing. It is a printer-domain, not a per-pixel display-shade-increment, reference, so the "select first or second color shade per pixel" limitations (claims 6, 16) are absent.

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Tier 2 — References hitting specific limitations

5. US 5,201,030 A — "Method and apparatus for dithering graphic images"

• Assignee: Sun Microsystems, Inc. Dates: filed 1989-09-28; granted 1993-04-06.
• Description: Software/hardware dithering of graphic images using a stored dither pattern indexed by pixel position; relevant to claims 4/5/9 (look-up-table value determined from pixel x/y address) and the general ordered-dither environment.
• Potential §102 target claims: 4, 5, 9 (LUT value from pixel x/y address). Not a per-se anticipatory reference for the ramp-bit-selection claims.

6. US 5,298,915 A — "System and method for producing a palette of many colors on a display screen having digitally-commanded pixels"

• Assignee: Cirrus Logic, Inc. Dates: filed 1989-04-10; granted 1994-03-29.
• Description: Cirrus Logic sibling to the '602, on palette expansion for digitally commanded pixels; supports the "fewer-than-8-bit color + expand perceived shade count" background (claims 12, 18, 19).

7. US 5,424,755 A — "Digital signal video color compression method and apparatus"

• Inventor: Lucas, Bruce D. Dates: filed 1992-06-25; granted 1995-06-13.
• Description: Color compression of video with truncation/reconstruction of low-order color bits; relevant to the truncation and low-bit-utilization steps (claims 1(b), 6(b)) and general § 102 background.

8. US 5,126,726 A — "Picture element encoding"

• Assignee: General Electric Co. Dates: filed 1989-12-27; granted 1992-06-30.
• Description: Pixel encoding for real-time image generation; background for pixel value packing/truncation (claims 1, 12).

9. US 4,905,164 A — "Method for modulating color for effecting color cell texture"

• Assignee: General Electric Co. Dates: filed 1986-12-19; granted 1990-02-27.
• Description: Modulates color (cell/texture) using stored pattern data with pixel-based selection; background to the LUT/pattern-selection apparatus of claim 12.

10. WO 1996036011 A1 — "Graphics system utilizing homogeneity values for depth for occlusion mapping and texture mapping"

• Assignee: The 3DO Company. Dates: published 1996-11-14 (filed 1995-05-10). Before the 1996-12-30 priority date.
• Description: Graphics-system pixel pipeline/anti-banding art; cited as § 102(a) background.

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Tier 3 — Background art (GE 3-D image-generation family)

The bulk of the citation list is General Electric Company computer-image-generation art that establishes the polygon/interpolation/shading context (the '796 Field and Background sections) but does not anticipate the dither-specific claims. These include: US 4,583,185; US 4,586,038; US 4,692,880; US 4,714,428; US 4,715,005; US 4,727,365 (+ US 4,727,365 B1); US 4,811,245; US 4,821,212; US 4,825,391; US 4,855,937; US 4,862,388; US 4,868,771; US 4,905,164 (listed above); US 4,958,305; US 4,965,745; US 4,974,176; US 5,126,726 (listed above); US 5,187,754; US 5,191,642; US 5,260,996(→ US 5,268,996); US 5,293,467; US 5,359,759; US 5,367,615; US 5,420,970. Also EP 0 526 045 A2 (nVIEW Corp.) and US 5,644,661 (British Technology Group, image interpolator). None of these recite the FRAC/ramp-value/look-up-table bit-selection combination of claims 1, 6, 12, 22, or 36; they are properly § 103 backdrop for the interpolation and polygon-rendering environment.

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Cross-cutting observations and uncertainties

• No single cited reference appears to anticipate the independent claims' defining feature. The '796's novelty sits in the "ramp value whose number of logic-1s encodes the discrepancy, with a look-up-table-selected single bit of that ramp driving the shade increment" (claims 1(d),(e); 7; 17; 12's ramp-probability logic; 22/36's ramp + bit-position mapping). Larky ('638) uses a multi-bit fraction vs. dither-matrix comparator; Masterson ('190) uses lowest-order-bits + address to gate an incrementer; EFI ('200) uses offset vs. threshold-array. Each covers part of the claim set but none shows the ramp-bit-selection mechanism. That is consistent with issuance over this art. Treat the bolded references as § 102 candidates for the dependent and apparatus claims, and as the strongest § 103 combinations for the independents.
• Family/same-inventor note. The related parent US 6,088,016 A (same inventors, filed 1996-12-30) is not available as prior art against '796 — same inventive entity and priority date — so it is omitted from the § 102 analysis. This is a point where the prior summary's "family" content and this analysis must be kept distinct: a family member is not an "anticipatory reference."
• Verification limits. I confirmed the bibliographic dates and technical content for items 1–5 via the linked primary sources (Google Patents / Justia / FPO / EPO). Tier 2–3 descriptions are drawn from the patent's own face-citation table and title/assignee metadata; I did not independently pull full claim text for every Tier 3 GE reference, so my "no anticipation" characterization of those is a judgment on the cited subject matter, not a certified clause-by-clause comparison. If you need a clause-by-clause § 102 chart, that requires pulling each reference's full claims from PatentCenter/PACER or a commercial database.

Sources: Google Patents US6008796A · Justia US6008796 · US4956638 · US5469190 · US5185602 · US5553200

I'll ground this analysis in the cited prior art by pulling details on the most relevant references.

Obviousness Analysis — U.S. Patent No. 6,008,796 under 35 U.S.C. § 103

Analyst note on scope. This analysis builds on the previously generated summary and litigation sections (which I do not repeat) and uses the prior-art references listed on the patent's face. I worked from the abstracts, specifications, and claim text of the cited references (Google Patents, Justia, FreePatentsOnline, Searchlight, and the EP/US PDFs retrieved in this session) — not from full element-by-element claim charts of those references. Where I have not verified a reference's full disclosure, I say so. All statements about the '796 claims track the literal issued text (including its drafting artifacts).

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1. Legal framework and governing law

Governing statute. '796 was filed 1997-05-15, with a § 119/§ 120 priority date of 1996-12-30 as a continuation-in-part of Ser. No. 08/777,557. It is therefore governed by pre-AIA 35 U.S.C. §§ 102/103, not the AIA (first-inventor-to-file) provisions. Any § 103 analysis must therefore use pre-AIA § 103(a) and the Graham v. John Deere framework, refined by KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).

The Graham factors.

1. Scope and content of the prior art.
2. Differences between the prior art and the claims at issue.
3. Level of ordinary skill in the pertinent art.
4. Secondary considerations (objective indicia).

Level of ordinary skill (PHOSITA) — proposed. A person having ordinary skill in the art as of December 1996 would hold a bachelor's degree in electrical engineering or computer science (or equivalent) and 2–4 years of experience in digital display/graphics controller design, including familiarity with: RGB bit-depth truncation and rounding, ordered/area dithering, error diffusion, dither matrices, look-up-table (palette) architectures, and hardware description of datapath elements (add logic, multiplexers, comparators). This is a mature, incremental art by 1996 — a factor cutting toward obviousness.

Analogous art. Every reference relied on below is either directed to digital-image dithering/color-depth reduction for a display ("References A–F") or to constructing dithered output patterns with look-up tables. All are from the same field of endeavor as '796, and all are reasonably pertinent to the banding/contouring problem the '796 specification itself identifies. No In re Bigio / field-of-invention escape is available to the patentee here.

All cited references predate the 1996-12-30 priority date, and all were issued or published before that date, so each is available as prior art:

Excluded: US 6,088,016 and WO 98/029859 are family members of '796 (the Ser. No. 08/777,557 CIP parent). Same inventive entity (Vaswani, Wilde, Dye), so they are not "by another" and are not properly § 102(e)/§ 102(a) art against '796. I flag this so no one builds a § 103 combination on them.

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2. What the independent claims actually require

Paraphrasing the issued text (from the prior section):

• Claim 1 (method). 8-bit shade → truncate → FRAC from truncated bits → produce a "rap value" (literal text; apparent typo for "ramp value") using the FRAC that encodes the discrepancy between the 8-bit shade and the truncated shade → map a dither value to a bit position within the ramp value → select a <8-bit shade using a bit from the ramp value.
• Claim 6 (method). Same front end, plus: produce an addend to increment the truncated shade → second shade → map a dither value to a ramp bit position → select first or second shade.
• Claim 12 (system). "select fractional logic" (outputs low-order bits) + "look-up table" (control value from pixel address) + "ramp probability logic" (ramp value encoding the discrepancy) + "mapping logic" (maps LUT value to a bit position within the ramp value).
• Claim 22 (CRM/software). Instructions that: determine a first LUT index; get a LUT value; determine a ramp probability value; map the LUT value to a bit position within the ramp probability value; select a dither color value.
• Claim 36 (method). The claim-22 limitations restated as method steps.

The single load-bearing limitation across all five independents is the same: an N-logic-1 "ramp" word that unary-encodes the discrepancy, plus a LUT-supplied selection of one bit position in that word — the probability of a "1" (hence of taking the next-higher shade) being N/8 (or N/4 for green).

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3. Core § 103 combinations

Combination 1 — A (IBM '638) alone, or A + B (Sun '030) → Claims 1–5, 12, 17–19

A (US 4,956,638) discloses the heart of claim 1. Its own words: a LUT "is used to map the desired (input) color to the shades available in the lookup table. The input color is mapped to the available palette entries. The fractional difference between the desired color and the palette entry is then compared to the value in the dither matrix to determine whether to use the palette entry that is lower (darker) than the desired color or the palette entry that is higher (brighter)." The incoming color "generates an integer result representing the lower palette entry and a fractional result (on a scale of 0 to 15 to correspond to a 16 entry dither matrix)," and "if the fractional value is less than or equal to the dither matrix entry then the lower value is selected, otherwise 1 is added to the integer result."
Source: US4956638A (Google Patents); Searchlight summary; EP0359080B1 (EPO).

Element-by-element:

The one feature not shown in haec verba is the unary "ramp" encoding and the "bit position" metaphor. IBM '638 stores the fraction in binary form and uses a magnitude comparator against a dither-matrix threshold. The patent's own FIG. 5 ramp word (e.g., 1111 1100 for FRAC = 6) is simply the unary expansion of that same fraction. The two provisions are the same mathematical function: (fraction/16) vs. (bit-position selected uniformly from 8) yield the identical probability of choosing the higher shade. That is a classic Smith v. Hayashi-type equivalent implementation.

Why combine / why obvious even without B. Claim 1's "mapping a dither value to a bit position" is met either (i) by reading IBM '638's fraction/dither-matrix comparison as an equivalent mapping, or (ii) by combining A with B (Sun '030), which goes further and expressly maps the discrepancy to the dither-matrix range: Sun '030 "generat[es] a second mapping function between the size of the interval and the size of the dither matrix to adjust the distance values and insure the accurate simulation of intermediate intensity values," then compares the adjusted distance value ("delta") against the dither value, outputting base or base+1. That is precisely the "map a dither value to a bit position within the ramp value" concept expressed in the threshold/threshold-index idiom. Source: US5201030A.

Motivation to combine A and B. Both are ordered-dither references in the same display-color-reduction field; Sun '030 expressly builds on and improves ordered dither of the type IBM '638 teaches (Sun '030 discusses quantization-by-truncation and the resulting error/brightness-loss problem in the same terms). A PHOSITA addressing IBM '638's limitation — that the interval between quantized shades is not always equal to the dither-matrix size — would look to Sun '030's mapping function as a known solution. KSR rationales (i)–(iii) apply: known elements each performing their known function; the combination is a mere substitution of known equivalents; there is an express design incentive and no teaching away.

Dependent claims. Claim 2/3 (truncate 2 or 3 low bits) — met by A (fraction/4-bit scale) and, for green, obvious in view of C (Apple '190), which expressly truncates "the three lowest order bits." Claim 4/5 (LUT used to select the bit; LUT addressed by pixel x and y) — met by B ("D is the 4×4 dither matrix… index[ed]… according to … i = x mod n, j = y mod n… the least significant bits of the x-y screen coordinates"), by D (k=(i) mod K, l=(j) mod L), and by E. Claim 17–19 (ramp carries N logic-1s; 5-5-5 / 5-6-5) — the 5-6-5 format was standard art (see the '796 background section itself, and C's 5-bit-per-component discussion).

Confidence: high that claims 1–5 and 12 (with 13–19) are invalid under § 103 over A alone or A+B. The only real debate is whether a trier of fact accepts the unary-ramp ↔ binary-fraction threshold as an equivalent; the specification's own admission that "any one ramp value need only include the proper number of logic 1 values; it is not important which bit positions contain the logic 1 and 0 values" strongly supports equivalence and weakens any argument that the unary form is a patentable distinction.

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Combination 2 — A + C (Apple '190) [+ B] → Claims 6–11, 20–21

Claim 6 adds the addend / second-shade selection step. C (US 5,463,190) discloses this almost exactly: "means for selectively incrementing the value of the five highest order bits of a value representing a component of a color, means responsive to a value of the lowest order bits … for providing a signal to cause the means for selectively incrementing to increment," and "means for selectively enabling the means responsive to a value of the lowest order bits depending on a desired pattern of pixels." It contrasts truncation, rounding, and the interleaving of the two — "This interleaving is an operation typically referred to as dithering." Source: US5469190A; US5469190 PDF.

Claims 7–9 are met as in Combination 1. Claims 10–11 (overflow signal disables dithering) are the only elements not squarely shown by A or C. But B (Sun '030) expressly confronts the same high-end problem — that incrementing the top shade "clips" and loses brightness — and devotes its invention to correcting precisely that end-of-range error. A PHOSITA implementing A/C's increment-and-select on a finite-range datapath would foresee the wrap/clip at the top code and, as a routine design choice, either suppress the increment (the '796 overflow-disable) or apply B's endpoint-mapping. Detecting a carry/overflow out of an adder is elementary datapath design. Confidence: moderate-to-high on claims 10–11; high on claims 6–9.

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Combination 3 — D (EFI '200) + A + C → Claims 22–35 and 36–49

The software/CRM claims (22 and 36) and their dependents are the same technical content expressed as instructions and bit-shift/mask arithmetic. D (US 5,553,200) is unusually strong here because it is expressly a software bit-rate-reduction/reconstruction reference that (i) uses dither/threshold arrays with LUTs, (ii) indexes by the low bits of the pixel coordinates (k=(i) mod K, l=(j) mod L), (iii) builds a LUT addressed by concatenating the code with the log2K LSBs of i and the log2L LSBs of j, and (iv) implements the dithering in a PostScript/page-description-language interpreter or explicit code. Source: US5553200A.

Map to the claims:

• Claim 22 "means for determining a first index value … providing a look-up table value … determining a ramp probability value … mapping said look-up table value to a bit position within said ramp probability value … selecting a dither color value" — D discloses the index → LUT → threshold-array comparison → coded output chain; A discloses the discrepancy/fraction; the "map the LUT value to a bit position" step is the software analogue of A's comparison. IBM '638 itself contains an express software embodiment: "[a]n alternative embodiment dispenses with the multiplexor by simply adding D2 to O1 and then shifting the least significant bits away… a simpler approach for a software realization" (EveryPatent transcription — see also the '638 searchlight text). That directly supports a software implementation of the same algorithm.
• Claims 23–30 (two index values from pixel addresses; low-order bits; LSB-3; AND with 7; add offset before ANDing; shift by 2 then right-shift the row; mask to 3 bits) — these are the literal arithmetic operations D and B describe (mod-K/L indexing via low bits; the x mod n indexing using the LSBs of x-y coordinates; LUT indexing by concatenation/masking). "AND with 7" and "add an offset" are trivial code realizations of "use the least significant three bits" (and offsets for font/pattern tiling — a routine option).
• Claim 31/45 ("ramp probability value = 2^FRAC − 1") — the unary-encoding formula; obvious as the unary expansion of the FRAC/A fraction (see §3, Combination 1).
• Claims 32–33 (right-shift by the LUT value, take LSB, zero the rest; left-shift to form the addend) — bit-manipulation implementations of exactly the "select bit N of a pattern word" and "place the increment in the truncated LSB position" operations that E's pattern-ROM bit selection and C's "shift the increment into the 5-bit field" describe.
• Claims 34–35 / 48–49 (add the addend to a color value; on overflow set dither = color value) — C's selective increment + B's endpoint/overflow concern.

Motivation. The '796 background itself concedes the PC/graphics market's demand for higher performance with limited memory — i.e., the commercial pressure to move dithering into software. D is a same-field software dithering system; A/C/B supply the specific depth-reduction algorithm. Combining a software dithering platform (D) with a known color-depth-reduction algorithm (A/C) is the paradigm KSR "known elements arranged as taught."

Confidence: high that claims 22–35 and 36–49 are obvious over D in view of A and C. One caveat: some dependent limitations are so specific (e.g., "shift by two bit positions to the left … mask least significant three bits") that a reference-by-reference mapping must be built carefully; the disclosure of D/B is strongly suggestive but I have not done a line-by-line chart of D.

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Combination 4 — E/F (Cirrus '602/'915) as the LUT/pattern-ROM bridge → Claims 12, 15

For the apparatus claim 12's "look-up table that produces a control value based on an address of each pixel," and claim 15's "first multiplexer for selecting a bit … controlled by said control value produced from said look-up table," E (US 5,185,602) and its sibling US 5,298,915 are directly on point: E discloses a pattern/array-selecting ROM addressed by pixel row/column (brightness) information that outputs a bit-position selecting value used to pick a bit from a stored pattern — i.e., precisely "a look-up table producing a control value based on a pixel address" that "selects a bit." E also discloses dithering/stippling for raising perceived gray levels. Sources: US5185602A; US5293159 (continuation). This is notable because E/F are the patentee's own assignee's (Cirrus Logic's) prior art, and the '796/Cirrus assignment history shows Cirrus Logic was the original assignee of '796 — i.e., the patentee was working in, and built upon, its own pattern-ROM dither architectures.

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4. Consolidated motivation-to-combine rationales (KSR)

1. Same field, same problem. Every reference addresses representing more color/gray levels than the physical bit-depth can express, using a two-shade mix averaged by the eye — the exact problem the '796 background identifies as "banding." (US4956638; US5201030; US5469190.)
2. Known elements, known functions. LUT indexing, low-order-bit truncation, fractional/discrepancy comparison, addend increment, and mux selection were each individually known; the combination achieves nothing more than the predictable combination of their functions.
3. Substitution of known equivalents. The binary fraction + magnitude comparator (A/B) and the unary ramp + bit-position selector (the '796 mechanism) are equivalent means to the same proportional-selection end; the specification concedes the ramp's only relevant property is how many 1s it contains, "not … which bit positions."
4. Design incentive / market pressure. The '796 specification itself frames the invention as a response to demands for higher performance under memory constraints — the same pressure that made software/SW-HW dithering (D) and pattern-ROM dithering (E/F) conventional.
5. No teaching away. No reference criticizes the others' approaches; rather, Sun '030 and EFI '200 build on the same dithering principles, and IBM '638 even offers the software alternative.

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5. Secondary considerations

I found no evidence of objective indicia (long-felt need tied to this specific mechanism, unexpected results, industry praise, licensing, or copying) in the material gathered. The patent's own characterization — "It has been experimentally shown that a group of pixels can be rendered with two color shades … to produce what appears … to be a different shade" — is a description of the known, well-understood ordered-dither effect, not an unexpected result. The "superior dither results" attributed to the specific 8×8 LUT combination in FIG. 4 is an optimization of a known pattern, which is generally insufficient to overcome a strong § 103 showing absent evidence of unexpected magnitude. This is a weak nexus point; I flag it as the patentee's best (but likely insufficient) rebuttal.

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6. Where the obviousness case is weakest / caveats

Being candid about the limits:

1. No literal "ramp with N ones + bit-position selection" in the references I examined. IBM '638 and Sun '030 use a magnitude comparison; the patent uses a unary code + indexed bit. The whole § 103 case on the independents turns on whether that is an equivalent (obvious) or a distinct mechanism. Under KSR, I believe a strong case exists for equivalence, but a patentee could argue the specific "probability ramp" architecture is not literally suggested and produces a different hardware/software footprint. I cannot certify that no reference discloses the unary ramp directly — I did not exhaustively search the full text of every cited reference, only those most on point.
2. Overflow-disable (claims 10–11, 35, 49). Not squarely disclosed; my case rests on the predictability of carry detection plus B's explicit treatment of the high-end clip problem. This is the most defensible dependent claim if the patentee resists.
3. Claim-drafting artifacts affect construction. Claim 1(d) recites a "rap value" (literal), and Claims 4 and 8 cross-reference "step e"/"step g" that do not align with the lettered steps as issued. Under Phillips, a claim term with no antecedent basis ("ramp value" vs. the earlier "rap value") may be construed by reference to the specification, or could be attacked as indefinite under § 112(b) — a separate validity theory outside § 103. I flag the risk that a court reading "rap value" narrowly could complicate a § 103 chart; but the specification and every dependent claim use "ramp," so the correction is likely treated as a typographical error.
4. I have not built full element-by-element claim charts of D, E, or F, nor retrieved their complete claim sets. Claims 22–35's very specific bit-shift/mask limitations and 36–49 in particular warrant a line-by-line mapping before relying on Combination 3 in a filing.
5. Expiry / posture. '796 expired (anticipated) 2016-12-30. A validity challenge today would most likely arise in an IPR (available even for expired patents, claims construed under Phillips) or as a defense to past damages; the prior-art dates are all comfortably before the 1996-12-30 priority date, so § 102/§ 103 date issues are not a problem.

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7. Bottom line

Overall: U.S. 6,008,796 presents a straightforward § 103 invalidity profile. The claimed advance over the cited art is the substitution of a unary "probability ramp" + LUT-indexed bit selection for the fraction/delta + dither-matrix comparison already taught by IBM '638 and Sun '030 — an equivalence the specification itself nearly concedes ("not important which bit positions contain the logic 1 and 0 values"). The addend/second-shade selection is taught by Apple '190; the LUT/pattern-ROM bit-selection architecture by Cirrus '602/'915; the software/LUT/indexing implementation by EFI '200. A reasonable examiner or PTAB panel would likely find claims 1–9, 12–21, and 22–49 obvious over these references in the combinations above; the overflow-disable claims (10–11, 35, 49) are the least vulnerable and would benefit from a more targeted reference search (e.g., saturation/clamping art) before finalizing contentions.

If you want, I can (a) pull the complete claim sets of D, E, and F and produce a formal element-by-element § 103 chart, or (b) search specifically for saturation/overflow-handling dithering art to shore up the claims 10–11/35/49 theory.