US 5630148

I'll search for authoritative information on this patent number, including any litigation or CAFC docket activity.

Let me run one more targeted check on litigation/docket activity for this exact number.

US 5,630,148 — Analyst Summary

Sourcing note

The authoritative source used here is the full granted patent text (Google Patents, US5630148A, fetched 2026‑09‑24). My supplementary searches did not return any USPTO PatentCenter record, PACER filing, or CAFC 2026 docket entry specifically naming U.S. Patent No. 5,630,148. I cannot confirm or deny current or recent litigation activity for this exact number beyond what the patent-family record shows (see "Post-grant activity" below). Where I lacked a source, I say so rather than infer.

⚠️ Important disambiguation: One search hit referenced an IPR involving "the '014 patent." That proceeding concerns U.S. Patent No. 8,646,014 B2 — a different patent (10 digits shorter, different number). It must not be conflated with US 5,630,148. I flag this because the abbreviations look similar.

Bibliographic data

Continuity: Filed as a continuation of application Ser. No. 08/261,457, filed Jun. 17, 1994 (now abandoned).

Classification: G06F1/3203, G06F1/324 (power management / lowering clock frequency), G06F1/08 (clock generators with changeable frequency), G06F1/26, G06F11/34, G06F13/42.

Representative prior art cited: US 5,086,387 (IBM); US 5,142,684 (Hand Held Products); US 5,230,074 (IBM); US 5,292,341 (Siemens Pacesetter); US 4,775,935 (Westinghouse). Family citation: US 4,893,271 (Motorola, "Synthesized clock microcomputer with power saving").

Abstract

"A computer system is disclosed comprising a clock generator circuit having a clock speed register and circuitry for generating a processor clock signal at a frequency determined by the clock speed register, wherein the processor executes a performance manager program that writes the clock speed register according to a performance state selected by an application program. The application program selects the performance state to maximize performance during processor intensive functions and to maximize power conservation during interactive functions."

Plain-language overview of the independent claims

Claim 1 — System claim

A computer system built from three cooperating parts:

1. Clock generator circuit containing a clock speed register plus circuitry that produces a processor clock signal whose frequency is set by the contents of that register.
2. Storage means for holding processor instructions.
3. A processor that is (a) coupled to receive the processor clock signal so it is synchronized by it, and (b) coupled to the storage to fetch and execute a performance manager program.

The inventive hook is what the performance manager does: it writes the clock speed register according to a performance state selected by an application program, where that performance state is picked out of a performance state table maintained by the performance manager. In plain terms: the running application asks for a performance level, and a manager program translates that request (via a lookup table) into a clock-frequency register write — letting software directly tune the CPU's speed/power trade-off at runtime.

Claim 9 — Method claim

A method for managing performance and power consumption, comprising the steps of:

1. Generating a processor clock signal at a frequency determined by a clock speed register;
2. Synchronizing the processor with that clock signal; and
3. Writing the clock speed register with a value specified in a performance state table maintained by a performance manager program executed by the processor — the value corresponding to a performance state selected by an application program running on the processor.

Method claim 9 is essentially the process-flow counterpart of system claim 1: same software-selected, table-driven clock-frequency adjustment, expressed as steps.

Key dependent-claim concepts (context, not required): the table stores multiple clock frequencies mapped to performance states (cl. 3, 10); a performance control panel lets the user pick the frequencies for each state (cl. 4, 11); the application issues a system call to step up to a high state at the start of a processor-intensive function (cl. 5, 12) and step back down when it ends (cl. 6, 13); the write occurs by invoking a clock generator driver in BIOS (cl. 7, 14); and claim 15 adds an "accelerate button" on the display that the user clicks to trigger a high-performance state. Storage means is non-volatile memory + memory subsystem (cl. 8).

Notable disclosed embodiments (beyond the claims)

• Three states (high/medium/low) mapped to example frequencies of 25/20/15 MHz; selectable divisors of the crystal oscillator (÷1, ÷2, ÷4, ÷8), and the ability to stop the clock.
• Cursor monitor embodiment: hooks the OS set_cursor call; when an hourglass cursor appears (indicating a processor-intensive operation), it automatically requests the high-performance state and restores the low state when the hourglass is removed.
• Target context: portable/laptop and palmtop systems on battery, with Microsoft Windows named as one OS embodiment.

Post-grant activity (from the family record)

• Legal events: grant (1997), fee payments at year 4 (2000), year 8 (2004), and year 12 (2008) — consistent with the listed "Expired – Lifetime" status and 2014‑06‑17 anticipated expiration.
• International family: EP0765499B1 (granted 2002‑01‑02), WO1995035540A1, JPH10501911A and JP4249763B2, CN1150845A / CN1118760C, TW282525B, DE69524873T2, BR9508040A, AU2903295A.
• Noted as cited by a large number of later power-management/clock-scaling patents (e.g., US 5,996,084, US 5,826,092, US 6,704,877, US 7,770,034), reflecting its role as background art in the CPU frequency/voltage-scaling field.

Confidence and caveats

• High confidence on title, inventor, assignee, application/filing/priority/issue dates, abstract, and claims — these come straight from the granted-text record.
• No confirmation of any 2026 CAFC appeal or docket involving this number; my searches surfaced nothing. This is an absence of evidence, not proof that none exists. A definitive check would require a live search of the CAFC docket (PACER/CM‑ECF) and USPTO PatentCenter/PTAB for the exact string "5,630,148."
• The patent expired in 2014 per the record, so as of the current date (2026) it is not in force — though an expired patent's claims can still matter for intervening-rights and prior-art purposes (and, if subject to a terminal disclaimer/late-fee issues, could theoretically have lapsed earlier; the record shows maintenance fees paid through year 12).

I'll search for litigation records involving US patent 5630148.

Let me search additional litigation databases and specific case sources.

Let me run more targeted searches on litigation databases.

Memorandum — Litigation Search: U.S. Patent No. 5,630,148

Patent identified (interpreted literally as given): U.S. Patent No. 5,630,148 — "Dynamic processor performance and power management in a computer system"; Application No. 08/613,778 (filed 1996‑02‑28 as a continuation of Ser. No. 08/261,457, filed 1994‑06‑17, now abandoned); inventor David Norris; assignee Intel Corp.; granted 1997‑05‑13; statutory/anticipated expiration 2014‑06‑17; Google Patents legal status: "Expired – Lifetime."

Bottom line

No litigation involving U.S. Patent No. 5,630,148 was identified. My searches did not surface any district court, Court of Appeals for the Federal Circuit (CAFC), or ITC proceeding in which U.S. 5,630,148 was asserted, challenged, or placed at issue. There is therefore nothing to report in the requested plaintiff/defendant/jurisdiction/case‑number/outcome format.

Searches performed and what they returned

1. General web search on "US patent 5630148 litigation" — returned zero results.
2. Quoted‑number searches for "5,630,148" / "5630148" combined with litigation terms (patent infringement complaint, defendant, court case, processor power management) — returned only unrelated documents concerning different patents that share the "148" shorthand. Specifically, the hits were:

• Hatch‑Waxman/ANDA cases involving U.S. 12,090,148 and U.S. 7,417,148 (different patents entirely);
• Display Pack, Inc. v. Speculative Product Design, LLC (d/b/a Speck Products), W.D. Mich., involving U.S. 7,931,148 B2 — "Double Hinge Display Package" (different patent, different technology);
• FARO Technologies / ROMER Cimcore dispute over a Cimcore '148 patent concerning articulated‑arm CMMs (different patent);
• various other '148 patents in D. Del. and elsewhere.
  None of these involves U.S. 5,630,148, and I did not treat them as arising from it.

1. Unified Patents portal / RPX Insight / Docket Alarm style searches — results returned Unified Patents, LLC's general IPR/PGR activity and litigation‑document repositories, but no entry referencing 5,630,148. (Unified's published IPR filing lists and "related matters" sections reviewed did not list this patent.)

Consistent with the record: 5,630,148 was cited by later patents (111 "Cited By" entries) and by examiners against later filings, and its family members (EP 0765499 B1, WO 1995/035540 A1, CN 1118760 C, TWI 282525 B, etc.) are noted as expired/ceased. Citation activity, however, is not litigation and does not evidence any suit.

Material caveats (stated as required)

• I could not confirm the absence of litigation through PACER directly, through the CAFC docket, through Docket Navigator or Lex Machina, or through the USPTO Assignment database — those are paywalled or search‑restricted sources; my tool set returned no direct query against them. My conclusion is based on the search results available to me and on the absence of any record in the public indexes that did respond.
• Because I found no case, I am not asserting affirmatively that no suit ever existed. I am reporting that none is known or identifiable from the searches conducted. Any statement that no litigation exists would be an overstatement.
• I have not auto‑corrected any identifier. Where search results referenced other "148" patents (e.g., 12,090,148; 7,417,148; 7,931,148 B2), those are different patents and are expressly excluded.

Suggested next steps for confirmation

1. PACER — party/patent search in the D. Del., E.D. Tex., W.D. Tex., N.D. Cal., C.D. Cal., and D. Mass. dockets where power‑management/processor patents were historically asserted, and a nationwide "patent number" search for 5,630,148.
2. CAFC docket search (cafc.uscourts.gov) for "5630148" as an appealed patent.
3. Docket Navigator / Lex Machina / RPX Insight patent‑number lookups (paywalled).
4. USPTO Assignment / Patent Center for 08/613,778 to detect any assignment (sale to an NPE) that would bear on whether assertion was commercially plausible; note the patent expired 2014‑06‑17, which materially limits any remaining cause of action and damages window (35 U.S.C. § 286).
5. Unified Patents Portal case‑list query by patent number — https://portal.unifiedpatents.com/litigation/caselist — to cross‑check the district court docket, and its PTAB case list for any IPR/PGR against 5,630,148.

If you can confirm which docket index you want treated as authoritative, I can refine the search accordingly.

I'll verify the ODP-derived empty list against public sources before reporting.

The first-pass results are "'563 patent" homonyms (light panels, frequency control). Let me pin the search to the full number.

Searches keep surfacing homonymous "'563"/"'148" patents. Two final targeted checks.

Proceedings overview

Total AIA trial proceedings on file for US 5,630,148: zero (0). Breakdown: 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denied. The USPTO Open Data Portal returns no IPR, PGR, or CBM proceeding naming this patent as the challenged patent, and four targeted web searches (including searches on the full number, the title, and the inventor) surfaced no IPR/PGR/CBM against it. The bottom line for a defendant is therefore unusual and strong: there is no PTAB record to exploit, but you very likely don't need one — the patent expired on 2014-06-17 and cannot be asserted for prospective infringement. The absence of PTAB activity is not a sign of a hardened patent; it is mostly a sign that the 20-year term ran out before the AIA trial regime matured.

Two important caveats before the per-proceeding sections:

1. PGR and CBM are categorically unavailable for this patent. PGR applies only to patents with an effective filing date on or after 2013-03-16 (35 U.S.C. § 321). This patent's priority date is 1994-06-17. CBM review (AIA § 18) sunset for new petitions on 2020-09-16 and in any event requires a "financial product or service" claim — the claims here are directed to processor clock-speed registers and a "performance manager" program (claims 1–15), not financial services.
2. IPR is legally available in the abstract but practically foreclosed by timing. The IPR window runs from 9 months after grant (or after any PGR) and is not limited by the patent's expiration as such; the Board has instituted IPRs on expired patents for back-damages purposes. But there is no petition on file, and § 315(b) would bar any petitioner served with a complaint more than one year earlier.

Proceedings overview (per-proceeding detail)

Because the canonical proceeding list is empty, there is no proceeding for which I can report a petitioner, panel, institution decision, FWD, or settlement. I will not invent one. What follows is the only genuinely relevant PTAB-adjacent data I could verify.

NONE — No AIA trial proceeding against US 5,630,148

• Type: N/A (no IPR / PGR / CBM on file)
• Filed: N/A
• Status: No proceeding on file per the USPTO ODP structured data supplied in this prompt.
• Judge panel: N/A
• Petition grounds: N/A
• Institution decision: N/A
• Final Written Decision: N/A — no claim of this patent has ever been canceled, confirmed, or construed by the Board. Claims 1–15 stand as granted, untested at the PTAB.
• Settlement / termination: N/A
• Appeal: No Federal Circuit appeal of any PTAB decision on this patent exists, because there is no PTAB decision. (VLSI v. OpenSky/Intel, Nos. 2023-2158/-2159, involves a different clock-speed patent — U.S. 7,523,?59 — not this one.)
• Defensive value: A defendant needs no PTAB weapon here. The affirmative defense is temporal: the patent's term expired 2014-06-17 ("Anticipated expiration," Google Patents legal-status field). Pre-expiration conduct (2014 or earlier) is the only exposure, and § 286 damages lookback (six years from filing) means even a 2015-filed complaint may reach only a sliver of pre-expiration sales.

Context — US 5,630,148 in the PTAB record as prior art, not as a challenged patent

This is worth separating out because it is easy to mistake for a proceeding against the patent.

• Verified instance: In IPR2015-01132 (an inter partes review of U.S. Pat. 6,523,123, Phoenix Technologies), US 5,630,148 was filed into the record as Exhibit 2001 (a patent-owner-side exhibit number). I could not confirm from the surfaced text whether the patent owner relied on it affirmatively or whether it was cited for context; I flag that as unresolved. Docket source: https://www.docketalarm.com/cases/PTAB/IPR2015-01132/Inter_Partes_Review_of_U.S._Pat._6523123/.
• Verified instance: US 5,630,148 ("Norris," Ex. 1006 in that record) is a cited combination reference in later PTAB petitions challenging an unrelated clock-management patent (I saw it discussed under a PTAB petition document ID 1558235, in a Belt/Foster/Norris/Alberth obviousness combination against a patent numbered "'417"). Petitioner's expert quote the "Norris" spec and Figures 3a/3b directly: "[a] POSITA would have understood the problem involved, namely, the need to allow the user of the Belt device the ability to change [clock frequency]…" and cited Norris's performance control panel 54 as teaching a user-selectable frequency GUI.
• Defensive value: These appearances cut against the patent owner, not for it. US 5,630,148 is now established in the PTAB record as prior art that describes the user-settable clock-frequency/performance-state architecture — i.e., the patent's own disclosure is being used to read clock-management features onto other people's later patents. If anyone ever threatened this patent, the same file history is a roadmap to the § 102/§ 103 art on its own claims.

(I deliberately am not supplying a "proceeding number" for the '417 petition — the P-TACTS document ID in the search result is a petition-file artifact, not a proceeding number, and I will not manufacture an IPR number from it.)

Strategic summary

Claim status. No claim of US 5,630,148 is canceled, none is confirmed by the Board, and none has been construed in an AIA trial. Independently claim 1 (computer system: clock generator with clock speed register + processor executing a "performance manager program" that writes the register per a performance state selected by an application program, selected from a performance state table), independent claim 9 (the corresponding method), and all dependents (claims 2–8, 10–15) are UNTESTED at the PTAB. If a demand letter cites this patent, you cannot point to a cancellation — but you almost certainly don't have to, because the patent expired 2014-06-17. The realistic posture is: no live infringement exposure; historical exposure only.

Estoppel landscape. § 315(e)(2) estoppel is irrelevant here — there is no final written decision, so no petitioner is estopped, and conversely no defendant inherits a favorable estoppel finding. The full prior-art universe remains available for an invalidity defense or a declaratory-judgment/§ 285 theory: notably the five references cited on the face of the patent (US 5,086,387 Arroyo multi-frequency clock generation; US 5,142,684 Perry power conservation in microprocessor-controlled devices; US 5,230,074 Canova battery-operated computer power management; US 4,775,935 Younick; US 5,292,341 Snell) plus the prolific later art that builds on this disclosure. There is no IPR-based estoppel trap and no forum-selection risk. If you are in litigation over pre-2014 conduct, a 35 U.S.C. § 282 invalidity defense resting on Perry '684 and Canova '074 is the natural path, and the "Norris-as-prior-art" PTAB briefing set gives you ready-made claim-mapping language on the very limitations (performance control panel, performance state table) that distinguish the claims.

Pattern signals. No serial petitioners, no repeat filings, no PTAB appeal history, and no defensive aggregator involvement — I found no Unified Patents, RPX, or similar filing against this patent. The assignee of record is Intel Corporation (original assignee; inventor David Norris of Portland, Oregon), not an NPE, and the family never went to a monetization vehicle. The patent was allowed to lapse at term ("Expired - Lifetime" as of the 2014 anticipated expiration) and, per the Google Patents docket, drew exactly one continuation (Ser. No. 08/261,457, filed 1994-06-17, abandoned). The foreign family (EP 0765499B1, JP 4249763B2, CN 1118760C, TW 282525B, BR 9508040A, AU 2903295A, WO 1995/035540A1) also shows no opposition or revocation activity surfaced in my searches — though an EPO opposition search is outside what I could verify here.

Recommended next steps

• If you are a defendant: Lead with expiration, not with validity. Confirm the term from the primary record at USPTO PatentCenter and the Google Patents page for US5630148A (legal status: "Expired - Lifetime"; anticipated expiration 2014-06-17). Then check the complaint date: under 35 U.S.C. § 286 the damages window is at most six years back from filing, so any complaint filed after 2020-06-17 reaches no infringing period at all. That is a dispositive, inexpensive motion — not an IPR.
• If you nonetheless need an invalidity position (e.g., to defeat a back-damages theory for pre-2014 conduct): there is no FWD to link to, so build the record yourself. Start from the § 102(b) art of record — US 5,142,684 (Perry) and US 5,230,074 (Canova) — and mine the "Norris"-as-prior-art PTAB briefing, which maps this patent's own disclosure of the performance control panel 54 / performance state table 56 onto clock-frequency-selection claim language. Begin at PTAB E2E to pull the petition record.
• If you are looking for a cancellation to cite against a troll: there isn't one, and there won't be. Say so plainly rather than implying a PTAB win: no AIA trial proceeding has ever been filed against US 5,630,148. Here the absence of PTAB activity is not the usual signal that a patent is hardened by prior successful defenses; it reflects a 1994-priority Intel patent that lived out its full term without ever being asserted aggressively enough to attract a petition, and was then cited by others as prior art.
• Verification gap to close if this is deal-critical: I could not run a live PTAB E2E party-name search ("Intel Corporation" as patent owner, or "5,630,148" as the challenged patent) or a CourtListener docket sweep; the tools available returned only web-search results. Treat the zero-count as sourced from the ODP structured block plus corroborating searches, and re-confirm at PTAB E2E and CourtListener before relying on it in a filing.

I'll research the assignment record and any litigation/ownership activity for this patent.

Ownership & Assignment Analysis — US 5,630,148

Sourcing note and a hard disambiguation warning

I was not able to retrieve a live page from USPTO Assignment Center (assignmentcenter.uspto.gov) for this patent within the available tooling — searches returned the granted-text record and third-party mirrors, not the Assignment Center result view. The authoritative record I did hold is the Google Patents "Legal Events" block for US5630148A, which mirrors the USPTO assignment/reassignment data. That block contains four events and none of them is a reassignment:

There is no ASGN/assignment event, no AS (assignee change), no reel/frame, and no correspondent anywhere in the record. My searches for "5630148 assignment," "5630148 reel frame," and Intel/Norris assignment entries surfaced no recorded assignment for this number.

⚠️ Do not confuse this patent with the other "'148 patents" in the search results. The hits I encountered reference entirely different patents: US 5,829,148 (Romer Cimcore / FARO arm litigation), a Medtronic–Axonics charging '148, an AbbVie v. Apotex '148, and US 10,659,885 / 10,820,117 (Taction v. Apple). None of those is US 5,630,148. Similarly, the IPR "'014 patent" (US 8,646,014) flagged in the prior summary is unrelated.

Inventors

Pattern notes: Only a single inventor is named. There is no evidence of inventor departure within 12 months of filing, no assignment-by-inventor recording, and no fire-sale precondition. I cannot determine Mr. Norris's subsequent employment (no source located), so I explicitly decline to infer that he left Intel — an absence of evidence is not a finding here. No unusual inventor-side pattern is present.

Original assignee

• Entity: Intel Corporation (Santa Clara, CA). Original and current assignee on the face of the patent.
• Primary line of business: semiconductor design/manufacture — CPUs and platform silicon. Intel is (and was at filing) a large operating company.
• Did it ship a product embodying the claims? Yes, functionally. The patent's subject matter — a runtime "performance manager" that writes a clock-speed register so software/OS can trade CPU frequency against power — was commercialized by Intel in its mobile line (e.g., mobile Pentium/Intel SpeedStep-era clock-throttling products). This is consistent with the patent's own "portable computer / battery" framing and with Intel's continued citation of it in later power-management patents (e.g., US 5,996,084; US 7,346,787).
• Current status: Operating. Intel remains a going concern as of the current date. (The patent itself is Expired – Lifetime, anticipated expiration 2014-06-17, per the family legal-status record — but note Intel is still the owner of record; expiry is not a transfer.)

No SEC 8-K/10-K disclosure of a transfer of this patent was surfaced. The patent did not move in any of the well-known operating-company fire-sales (Kodak, Nortel, Polaroid).

Assignment timeline

Finding: USPTO Assignment Center shows no recorded post-issuance assignments for US 5,630,148.

The Google Patents legal-events record — the assignment/reassignment data I could actually verify — contains only fee-payment and grant entries, no ASGN conveyance. Searches for a reel/frame, assignor/assignee pair, or correspondent for this number returned nothing.

Per the task rules, I state this plainly and do not fabricate a chain. The practical meaning:

• The only "assignment" in the patent's history is the implicit original assignment of the inventor's rights to Intel at filing — it does not appear as a recorded reassignment in the legal-events block, so no execution date, reel/frame, or correspondent is available to report.
• Because there is no recorded conveyance, there is likewise no correspondent of record (no attorney/firm) to analyze for the repeat-player signal. This is a genuine data gap, not a "cleared" indicator.

If the live Assignment Center does contain a record my tooling could not reach, the only plausible entry would be the original inventor→Intel assignment at/near filing (1994-06-17 or 1996-02-28); nothing in any source I retrieved shows any later link.

Timeline diagram

timeline
    title Ownership of US 5630148
    1994 : Application filed by Intel Corp
         : Inventor David Norris named
    1997 : Patent issued to Intel Corp
    2000 : Maintenance fee paid year 4
    2004 : Maintenance fee paid year 8
    2008 : Maintenance fee paid year 12
    2014 : Patent expired lifetime

Event text kept to simple year labels with no parentheses, slashes, or commas.

NPE / troll-pattern signals

No signal is "present." Several are unclear only in the narrow sense of the data gap for signals 3 and 5 (they presuppose a recorded chain that does not exist).

Verdict

Insufficient data (no records, or only the original assignment).

Justification: The verified record (Google Patents legal events for US5630148A; corroborated by my searches) shows no recorded assignment beyond the original issuance to Intel — only grant and maintenance-fee entries at years 4 (2000-11-10), 8 (2004-11-15), and 12 (2008-11-06). With a chain that never leaves the original operating assignee, none of the eight NPE signals can be affirmatively marked present, and no reel/frame or correspondent exists to cite. This patent therefore presents as an operating-company-owned, never-transferred, now-expired asset — the opposite of an NPE pattern — not because the chain was cleared, but because no post-issuance chain exists at all.

Caveat (stated honestly): I could not open the live Assignment Center result page myself; the conclusion rests on the mirrored legal-events data plus negative search results. To fully confirm, run the exact string search at USPTO Assignment Center — US 5,630,148 (or the legacy assignment.uspto.gov) and check for any ASGN entry. If one exists, it should be only the inventor→Intel original assignment; if the result set is empty, that independently confirms this verdict.

I'll search for the patent and its cited references to ground this analysis.

Let me verify the remaining cited references, including the "X"-category art from the European search report.

Prior-Art Analysis — US 5,630,148

Patent under analysis: US 5,630,148 A — "Dynamic processor performance and power management in a computer system" — David Norris — Intel Corp. — Appl. No. 08/613,778 — filed 1996‑02‑28 — effective prior‑art cutoff: priority date 1994‑06‑17 (continuation of Ser. No. 08/261,457, filed 1994‑06‑17, abandoned).

Method and sourcing note

I built this from the granted front‑page citation lists, which I confirmed against two independent reproductions of the printed patent:

• Google Patents, US5630148A — https://patents.google.com/patent/US5630148/en
• EveryPatent front page (full "References Cited U.S. Patent Documents" table with examiner/inventor/class data) — http://www.everypatent.com/comp/pat5630148.html

The patent carries two distinct citation sets, and conflating them is the main trap here:

The [X] category on set (B) is the strongest available prosecution signal: the EPO examiner treated those two items as the closest art that could stand alone against the family claims — notably stronger than the bare Id. listing of set (A).

⚠️ Two caveats up front: (1) I could not retrieve the full text of US 4,775,935, US 5,292,341, or the Young et al. article within my search budget, so those three descriptions rest on title/abstract/front‑page data and the EP search report only — flagged again below. (2) The task header says "April 26, 2026" while my operating date is 2026‑09‑29 and the previously generated sections used 2026‑09‑24/2026; I note the inconsistency rather than resolve it.

Reference‑by‑reference analysis

A1. US 4,775,935 A — Video merchandising system with variable and adoptive product sequence presentation order

• Inventor / assignee: Yourick / Westinghouse Electric Corp.
• Filed: 1986‑09‑22 · Granted/published: 1988‑10‑04 · US class 364/401 (per front page)
• Description: A video merchandising/point‑of‑sale presentation system that varies and adapts the order in which product information is presented. It is a business‑display / sequencing invention — no processor clock generation, no clock speed register, no power management.
• Potential §102 anticipation: None of claims 1–15. It contains no element of the claimed clock‑generator/register/processor combination. Its presence in the citation list is best explained as general background on adaptive, table‑driven sequencing of a presentation — at most §103 "analogous‑art" dressing, and even that is a stretch. If a rejection were ever premised on this reference alone, it would fail under §102 because it is missing every material limitation.

A2. US 5,086,387 A — Multi‑frequency clock generation with low state coincidence upon latching

• Inventors / assignee: Arroyo et al. / International Business Machines Corp.
• Filed: 1986‑01‑17 · Granted/published: 1992‑02‑04 · US class 395/550
• Description (verified full‑text): A programmable multi‑frequency clock circuit. A clock register is loaded over the processor data bus; its contents select which frequency a clock control circuit takes from a frequency generator, so "the actual frequency of the clock signal output ... is determined by the data contents of the clock register." The processor "may direct the clock control circuit to output a slow clock frequency ... by the processor loading specific data into the clock register," giving "lower power consumption." One register bit is auto‑cleared on an interrupt or DMA request to restore normal (fast) clock, and the circuit is designed so frequency changes still satisfy the CPU's minimum clock high/low times.
• Potential §102 anticipation: Potentially anticipates the clock‑architecture limitations of claims 1 and 9 — specifically "clock generator circuit having a clock speed register and circuitry for generating a processor clock signal at a frequency determined by the clock speed register" and the processor‑writes‑the‑register step. However it does not disclose (i) a performance state selected by an application program, (ii) selection from a performance state table, or (iii) a performance manager program. It therefore does not anticipate claim 1 or claim 9 as a whole, and cannot anticipate dependent claims 2–8, 10–15. Its realistic role is §103 art supplying the "processor‑written clock speed register" limitation (and it pairs naturally with US 5,142,684, below, which supplies the software‑selected speed element).
• Note: this reference and US 5,230,074 share an IBM "Arroyo et al." lineage (US 4,907,150 appears in the '074 front page), consistent with IBM's 1986–1991 clock/power work being the examiner's baseline.

A3. US 5,142,684 A — Power conservation in microprocessor controlled devices — the single most relevant examiner‑cited reference

• Inventors / assignee: Perry et al. / Hand Held Products, Inc.
• Filed: 1989‑06‑23 · Granted/published: 1992‑08‑25 · US class 395/750 · 66 claims
• Description (verified full‑text): A battery‑powered, portable (bar‑code reader) system with a low‑power processor and a high‑power processor. The high‑speed processor "may run at variable clock speeds ... The high speed processor selects its own clock speed based upon the task to be performed, by including a clock speed in each software subroutine which controls a task. The software subroutine associated with a task is thereby executed at its associated clock speed, which may be chosen to be the lowest possible clock speed consistent with the task." The flow diagram shows: application/interrupt software "selects appropriate clock speed for the ... routine about to be executed" → "control code sent ... to variable speed system clock" → clock changes to requested speed → routine executes at up to 10 MHz → on completion, "processor 20 sends a control code to variable speed clock to slow down to slowest speed." Claim 4 recites "identifying one of said plurality of second speeds associated with the activated software routine"; claim 5 recites dropping back to a slow speed after the task; claim 9 repeats that ordering.
• Potential §102 anticipation: This is the best §102 candidate in the entire set and the reference an examiner would anchor on. Element mapping against claim 1 / claim 9:
  • "clock signal at a frequency determined by a clock speed register" → the variable speed system clock driven by a processor control code (a functional, though not literally "register"‑labeled, equivalent);
  • "processor ... synchronized by the clock signal" → yes (the high‑speed CPU is clocked by that variable clock);
  • "value corresponding to a performance state selected by an application program" → substantially met — the speed is selected by the running software routine/task (plural speeds = performance states);
  • "performance state table maintained by a performance manager program" → the weakest link. US 5,142,684 embeds the speed inside each software subroutine rather than in a table maintained by a separate manager program, and it is a two‑processor architecture.
  • "at least a memory" → DRAM/storage present.
• Honest conclusion: US 5,142,684 reasonably anticipates claims 1 and 9 on the software‑selects‑speed concept, but the "performance state table maintained by the performance manager program" limitation leaves a gap that a §102 rejection would likely fail to bridge; expect it instead as the primary §103 reference, combined with US 5,086,387 (register) or US 4,893,271 (program‑controlled synthesizer). It also maps well against claims 5, 6, 12, 13 (step up at the start of a processor‑intensive task; step back down when it ends) and claims 3, 10 (a plurality of speeds/states).

A4. US 5,230,074 A — Battery operated computer power management system

• Inventors / assignee: Canova, Jr. et al. / International Business Machines Corp.
• Filed: 1991‑01‑25 · Granted/published: 1993‑07‑20 · US class 714/14 · (family: EP0496536B1)
• Description (verified full‑text): A laptop with a main processor (80386SX) plus a power‑management processor. It has a clock speed controller selectively settable to one of a plurality of predetermined rates, a user‑actuated switch selecting the rate, a non‑volatile store holding a user‑selectable "energy option" for either high performance or long battery life, and a manual/automatic switch. In automatic mode the system "operat[es] said processor at a high rate when said high performance objective is selected and ... by switching between a high rate and a low rate dependent on system activity." The A/M‑switch handler sets the clock via a clock speed control register (110) — e.g., 20 MHz for high speed and 5 MHz for low speed; the manual path permits 5/10/20 MHz. It also discloses an application‑program "wait on event" call to BIOS during which the processor can be shut off/slept.
• Potential §102 anticipation:
  • Claims 4 and 11 (performance control panel / user selects the clock frequencies for the states): potentially anticipated substantively — the '074 user energy option plus predetermined 5/10/20 MHz rates is the same functional idea (user picks the operating rates). The claimed "performance control panel program" graphical aspect is not literally present, so strict §102 falls short.
  • Claims 5/6/12/13 (step up at function start, step back at end): strong §103 support — "switching between a high rate and a low rate dependent on system activity" is the closest cited disclosure of dynamic step‑up/step‑down, but it is activity‑driven, not application‑system‑call‑driven.
  • Claim 1 / 9: Missing the application‑selected performance state and the performance state table; the selection is by switch/energy option, not by application program. Not anticipated on its own.
  • The "wait on event" BIOS call from an application is the closest cited analogue to the claimed set_performance_state system call (claims 5, 6, 12, 13), and is worth citing expressly.

A5. US 5,292,341 A — Method and system for determining and automatically adjusting the sensor parameters of a rate‑responsive pacemaker

• Inventor / assignee: Snell / Siemens Pacesetter, Inc.
• Filed: 1992‑03‑02 · Granted/published: 1994‑03‑08 · US class 607/30 (cardiac pacing)
• Description (front‑page data only — full text not retrieved): An implantable rate‑responsive pacemaker that determines and automatically adjusts the sensor parameters governing its rate‑response function.
• Potential §102 anticipation: None of claims 1–15. There is no processor clock signal, no clock speed register, no performance state table for a CPU, and no application‑program performance state. It is non‑analogous art. Its likely citation rationale is to show automatic, sensed‑condition‑based adjustment of stored control parameters (a loose thematic parallel to the disclosure's cursor‑monitor embodiment), or possibly as an example of a parameter table indexed to operating states — useful at most for §103 motivation, never for §102 anticipation.
• Note: the '341 postdates the conception‑era activity but still predates the 1994‑06‑17 filing, so it qualifies as prior art under §102(a)/(e) even though it cannot support a §102(b) statutory‑bar theory.

B. Additional prior art cited in family prosecution (EP) — category [X], not on the US front page

B1. US 4,893,271 A — Synthesized clock microcomputer with power saving

• Inventors / assignee: Davis, Little, Herold / Motorola, Inc.
• Filed: 1983‑11‑07 (priority 1983‑11‑07, US 549,954) · Granted/published: 1990‑01‑09 · main IPC G06F 1/04 · (family: EP0162870, WO85/02275)
• Description (verified full‑text): A microcomputer with a programmable clock frequency source — a low‑frequency crystal oscillator, a frequency‑multiplying synthesizer (phase detector / loop filter / VCO / programmable divider), and a clock source selector. Its stated premise is precisely the '148 problem statement: "the clock frequency must necessarily be set high enough to provide the computational power ... required to handle the most demanding task," so the microcomputer "frequently operates at higher clock frequencies than would be required," and "if the clock frequency were under program control, this would provide a more energy efficient microcomputer system." The synthesizer output "can be varied over a wide range of values under direct control by the microcomputer," enabling a >100:1 power‑dissipation range; unused synthesizer elements can be powered down.
• Potential §102 anticipation: Potentially anticipates the "program‑controlled / processor‑controlled variable clock frequency" core of claims 1 and 9, and the "set of clock frequencies" idea of claims 3/10. It does not disclose an application‑program‑selected performance state, a performance state table, a performance manager, a system call, a control panel, or an accelerate button — so claims 1–2 and 9 in full, and claims 4–8, 11–15, are not anticipated. This is the reference the EPO examiner rated [X], making it the most dangerous single item of prior art for the independent claims notwithstanding its absence from the US front page. It should be treated as the primary art to combine with US 5,142,684.

B2. Young, R. et al., "Adaptive Clock Speed Control for Variable Processor Loading," Motorola Technical Developments, vol. 15, 1 May 1992, pp. 43–44

• Type: Non‑patent literature, EPO [X] category (per the EP0765499 search report reproduced at data.epo.org/gpi/EP0765499A4).
• Description: Title and EPO categorization only — I could not retrieve the body text. Its title indicates clock speed adapted to variable processor loading, i.e., dynamic frequency scaling driven by measured/expected CPU demand.
• Potential §102 anticipation: On the title alone it is the closest theme‑match in the entire family citation set to the '148 dynamic step‑up‑on‑load behaviour (and to the cursor‑monitor embodiment), and the EPO treated it as stand‑alone‑relevant [X]. But because I have not read it, I cannot responsibly assert which claims it anticipates. Treat its claim mapping as unverified; it plausibly targets claims 1, 5, 9, 12. Any §102 assertion based on it must await retrieval of the article itself.

Claim‑level §102 exposure summary

Effective cutoff 1994‑06‑17; all listed references predate it, so all are available art. "Anticipates?" reflects whether the reference, taken alone, discloses every limitation of the claim.

Limitations with no counterpart in the cited US art: the performance state table maintained by the performance manager program (cl. 1, 2, 3, 9, 10); the performance control panel program GUI (cl. 4, 11); the accelerate button (cl. 15); and the BIOS clock‑generator‑driver invocation (cl. 7, 14). These are the features that carry the patent's novelty over the examiner‑cited set.

Bottom line

1. Most relevant prior art overall: US 4,893,271 (Motorola) and the Young et al. Motorola Technical Developments note — both rated [X] by the EPO on the family member EP0765499, and both more on‑point than anything the US examiner listed. Neither appears on the US front page.
2. Most relevant US‑examined reference: US 5,142,684 (Perry/Hand Held Products) — its "software subroutine selects its own clock speed ... lowest possible clock speed consistent with the task" disclosure is the nearest thing to claim 1's application‑selected performance state.
3. Supporting references: US 5,086,387 supplies the processor‑written clock speed register; US 5,230,074 supplies user‑selectable energy options, multiple predetermined clock rates, activity‑dependent high/low switching, and an application "wait on event" BIOS call.
4. Non‑analogous citations: US 4,775,935 (video merchandising) and US 5,292,341 (pacemaker) do not anticipate any of claims 1–15; they are background/context citations only. They appear on the printed patent's "References Cited" list as examiner citations and should not be over‑read as §102 threats.

Caveats: (a) I did not retrieve full texts for US 4,775,935, US 5,292,341, or the Young et al. article, so those three entries are title/front‑page/EP‑search‑report based; (b) the US printed patent carries no Id./X/Y relevance codes — only the EP search report does — so US‑side relevance rankings here are my analytical judgment, not an examiner's stated characterization; (c) claims 1 and 9 are the only independent claims, and no cited reference reads on them in full.

I'll ground this analysis in the actual cited prior art. Let me pull details on the key references from the patent page's Prior Art section.

Obviousness Analysis — U.S. Patent No. 5,630,148 under 35 U.S.C. § 103

Builds on the prior "Patent summary" and "Litigation summary" sections (no litigation identified; patent expired 2014‑06‑17). Nothing in this analysis contradicts those sections. All analysis below is limited to the references appearing in the Prior Art (Citations) section of the US5630148 page, marked "† Cited by examiner," plus the single family-cited reference US 4,893,271 that the family record lists under "Family Cites Families."

1. Framework and the person of ordinary skill

Governing law. Obviousness is assessed under the Graham v. John Deere factors — (1) scope/content of the prior art, (2) differences between prior art and claims, (3) level of ordinary skill, and (4) secondary considerations — applied against the flexible KSR Int'l v. Teleflex rationales (predictable combination of known elements; substitution of a known technique; use of a known technique to improve a similar device; market/design incentive).

Hypothetical POSITA (as of the 1994‑06‑17 priority date). A person having ordinary skill would hold a B.S. in electrical engineering or computer science (or equivalent) and roughly 2–4 years of experience in computer-system power/clock management, with working familiarity with: programmable clock dividers/PLL synthesizers; processor clock-register interfaces; battery-powered portable-computer design; and the then-current OS/BIOS power-management framework (e.g., the BIOS interrupt/driver model and the emerging APM-style API). This is a modest skill level — all of the disclosed hardware (register-programmable clock, dividers, lookup tables, system calls) was conventional by 1994.

Secondary reference caution. Two of the five examiner citations are not technically on point and are not relied on below: US 4,775,935 (Westinghouse, video merchandising/adaptive sequence) and US 5,292,341 (Siemens Pacesetter, rate-responsive pacemaker sensor parameters). They are non-analogous art for the clock-frequency-management problem. The analysis instead turns on the three clock/power references: US 5,086,387, US 5,142,684, and US 5,230,074, plus the family cite US 4,893,271.

2. Scope of the three material prior-art references (as sourced)

3. Primary ground: Claims 1 and 9 obvious over US 5,142,684 in view of US 5,086,387 and US 4,893,271

3.1 Element mapping (Claim 1 / Claim 9)

3.2 Why the combination is proper (motivation)

• Same field, same problem, same solution family. '684, '271, and '087/'074 all expressly target processor power conservation by varying clock frequency in battery-powered or portable systems. '271's stated object — "provide a variable clock frequency source for a microcomputer, the output frequency of which can be varied in accordance with the computational requirements" — is the same objective as '148. Combining references that address the identical problem is the paradigm case of proper motivation.
• '684 supplies the two-level software selection. '684's disclosure that the application/task routine selects the clock speed and that a control code is then sent to the variable-speed clock is the direct functional precursor to '148's "application selects a performance state → manager writes the register." The only structural difference is that '148 interposes a manager program and a table between the application request and the register write.
• '387 supplies register-level programmability plus automatic restoration. '387 already teaches a processor-addressable clock register that selects one of several clock frequencies and that is automatically restored to normal on an event — squarely meeting claim 1's "writes the clock speed register" and claim 6/13's "restore … as the application ends a processor-intensive function."
• '271 supplies program-control of the frequency source itself, confirming that making the clock frequency a function of program instructions (rather than a fixed crystal) was known and beneficial — reinforcing the "predictable combination."

3.3 KSR rationales articulated

1. Predictable combination of known elements: register-programmable clock ('387/'271) + application/task-driven speed selection ('684/'271) → merely juxtaposed to yield their expected combined result (higher speed for demanding tasks, lower speed otherwise).
2. Substitution of a known technique: replacing '684's per-subroutine embedded clock-speed value with a central table lookup of predefined performance states ('074's stored set of predetermined rates) is the substitution of one known data-deployment technique for another, with predictable results.
3. Known technique to improve a similar device: using a lookup table (a ubiquitous programming construct), maintained by a supervisory routine, to map a requested state to a register value improves the device in the same way the references already did.
4. Design incentive / market pressure: battery life was the dominant design constraint of the 1993–1994 laptop/palmtop market, giving a strong reason to combine any available clock-management teachings.

Conclusion (Ground 1): Claims 1 and 9 would have been prima facie obvious over '684 + '387 + '271, and a fortiori over the same combination further in view of '074.

4. Alternative/stronger ground: add US 5,230,074 for the "predetermined state" and "automatic" limitations

'074 independently supplies several limitations that make the primary ground stronger:

• "plurality of predetermined rates" + stored options → maps to the claimed set of performance states and the performance state table (claim 3/10).
• automatic, activity-dependent switching between a high rate and a low rate → maps to claim 6/13's automatic step-down at the end of a processor-intensive function, and anticipates the patent's own cursor-monitor alternative embodiment (hourglass → high state) as an automated variant.
• user-actuated switch + non-volatile storage of the energy option → maps to the performance control panel of claims 4/11.

Thus '074 + '684 + '387 (+ '271) is the strongest combination, and '074 supplies nearly every dependent-claim concept as well.

5. Dependent-claim chart

Note the near-symmetric structure of claims 5/6 and 12/13 against '684's own flow (select-before-routine / slow-down-after-routine), which is a notably tight mapping and is the single most damaging item for the dependent claims.

6. Counter-points (why a Patent Owner might argue non-obviousness)

For completeness — a competent Patent Owner would press these, though I assess each as likely insufficient under KSR:

1. The two-level software abstraction is the point of novelty. '148 is arguably the first to interpose a single performance-manager program maintaining a performance-state table, invoked by an application via system call, and to route the register write through a BIOS clock-generator driver. None of '387, '684, '271, or '074 is squarely a multi-application, table-driven mediation layer. Rebuttal: it is a predictable software-architecture refinement of '684's "application picks speed → control code to clock," and the claimed table is an ordinary lookup structure; KSR cautions against finding novelty in a predictable implementation of a known function.
2. '684 uses two processors / embeds speed in each subroutine. Rebuttal: '684 also describes a single processor selecting its own speed, and the claimed "table" is a mere alternative storage locus for the same data.
3. '387's register write is not "according to an application-selected performance state." Rebuttal: '684 and '271 supply precisely that program/application-driven control, supplying the missing limitation — the classic "secondary reference supplies the gap" rationale.

Secondary considerations (Graham factor 4): The record on this page contains no evidence of unexpected results, industry praise, long-felt need overcome, or copying tied to these claims; the "Cited By" volume (111 entries) shows the patent became pervasive background art, which is evidence of the field's trajectory rather than of non-obviousness. Absent such evidence, the objective-indicia factor does not weigh heavily against the prima facie case.

7. Overall conclusion

• Claims 1 and 9: likely obvious over US 5,142,684 + US 5,086,387 + US 4,893,271; obviousness is still clearer when US 5,230,074 is added for the predetermined-state/table limitation.
• Claims 3, 5, 6, 7, 8, 10, 12, 13, 14: likely obvious over the same combination (with '074 and '684 supplying the specific dependent features).
• Claims 4, 11, 15, 16: obvious as routine UI/design-choice implementations of '074's user-selectable rate in the claimed Windows environment, though these are the claims on which a Patent Owner would most plausibly resist, since the GUI "control panel" and "accelerate button" are not literately disclosed in the cited art.
• Weakest link in the prima facie case: the "performance state table maintained by the performance manager program" limitation and the manager-as-mediator architecture. The strongest defense of validity would rest there; it is a modest but non-frivolous position.

8. Confidence and caveats

• High confidence in the content mappings for US 5,086,387 (register 30 / control 40 / generator 50; auto-restore on interrupt), US 5,142,684 (application/task-selected clock speed; slow-down at routine completion), and US 4,893,271 (program-controlled frequency source) — these are directly quoted from the sources retrieved.
• Moderate confidence on the precise fit of US 5,230,074 as a "performance state table maintained by a performance manager": '074 stores the user-selected speed/energy option in non-volatile storage and a control routine reads it out, which functions as a state table, but '074 does not use that phrase or describe a discrete manager program mediating application system calls. I flag this as an analogy, not an identity.
• US 4,893,271 enters this analysis as the family-cited reference (listed under "Family Cites Families"), not as one of the five examiner citations; its use is appropriate because it predates the priority date and is on point.
• I did not rely on any of the 111 "Cited By" references (they postdate the 1994‑06‑17 priority date and cannot be §102/§103 prior art against this patent), nor on any materials outside the patent page's Prior Art section except where noted for background (e.g., the APM framework's general availability), and I have not auto-corrected any patent number.
• This is a technical obviousness assessment, not a legal opinion; claim-by-claim invalidity would require the full prosecution histories of the family members (EP 0765499 B1 file wrapper, etc.) and any applicant statements distinguishing these very references.