Invalidity dossier
US 5377320
Method and apparatus for the rendering of trimmed nurb surfaces
Current assignee: Sun Microsystems Inc
Added 9/23/2026, 12:50:26 PM
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Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview: US 5,377,320 A
Title: Method and apparatus for the rendering of trimmed NURB surfaces
Assignee: Sun Microsystems, Inc. (original assignee; assignment recorded 1992-11-27). Inventors: Salim S. Abi-Ezzi and Srikanth Subramaniam.
Key dates (as listed): Priority/filing date 1992-09-30 (application US07/953,971); granted/publication date 1994-12-27; anticipated expiration 2012-09-30. Legal status listed as "Expired – Lifetime." Related filings: EP93305983A (EP0590765B1), DE69322575T, JP24624093A (JP3344597B2). Classification: G06T17/20 (three-dimensional modelling; finite element generation/tessellation).
Purpose: To render trimmed NURBS (non-uniform rational b-spline) surfaces — surfaces with trimming loops defining the relevant portions — quickly and efficiently on a computer graphics display, addressing the problem that such rendering is "quite complex and time consuming."
Plain-language scope: A graphics pipeline processes a trimmed NURBS primitive through (1) a compilation step, then (2) a two-phase traversal step, then (3) display. At compilation, the trimmed NURBS is broken into monotone v-regions that remain valid across subsequent views and renderings and are independent of tessellation step size, so the compiled form survives heavy modeling/viewing transformation changes. Much processing complexity is absorbed at compilation, minimizing tessellation complexity at traversal. The traversal phases may run in parallel. Details described include trimming-loop conventions (left-hand rule; overlapping knot-line segments treated as pivoted left), classifying v-regions into nine types, casting horizontal lines to dissect monotone chains (binary search; root-solving for Bezier curves), triangulation of monotone polygons using an adaptation of the "O(n) algorithm" by Garey et al., "stitching strips" to plug gaps between patches of different step sizes, and lighting via Gouraud or Phong shading. A co-processor (FPU + memory + VLSI) tessellates, lights, and scan-converts triangles into a frame buffer.
Source: https://patents.google.com/patent/US5377320/en
What the excerpt does not establish: The full claim text is not included, so the precise legal scope of the claims cannot be confirmed. The above reflects the abstract and description excerpt only; omitted description text and any figures/embodiments are not addressed. No determination is made regarding prior art, validity, or enforceability.
Generated 10/1/2026, 9:53:27 PM
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