US 4891781

I'll search for authoritative information on US 4891781, including any 2026 CAFC activity.

Now let me check for any litigation or CAFC 2026 docket activity involving this patent.

US 4,891,781 — "Modulo Arithmetic Processor Chip"

Identifier note (strict reading): I analyzed exactly US 4,891,781 (7 digits, as printed in the patent itself as "4,891,781"). I did not substitute the similarly-numbered patents that surface in searches (e.g., US 5,210,710, a later Omura/Cylink continuation; US 7,916,781, Caltech's patent asserted in Caltech v. Apple/Broadcom; US 4,201,770-family Hellman patents). One search hit returned an unrelated "4891781" (a Minnesota PUC receptor ID) — not this patent.

1. Bibliographic data

Sources: https://patents.google.com/patent/US4891781/en · https://patentimages.storage.googleapis.com/bb/29/58/849243e0052fb5/US4891781.pdf · https://portal.unifiedpatents.com/patents/patent/US-4891781-A · http://data.epo.org/publication-server/rest/v1.2/patents/EP0281303NWA3/document.html

Cited prior art (patents): US 4,200,770 (Hellman), US 4,405,829 (Rivest – RSA), US 4,218,582 (Hellman), US 4,424,414 (Hellman), US 4,587,627 (Omura), plus Galois-field work by Berlekamp, Marver, and others; non-patent citations include Diffie & Hellman, "New Directions in Cryptography" (IEEE Trans. Info. Theory, Nov. 1976).

2. Abstract (verbatim)

"The present invention provides for a processor chip for computing addition, multiplication, and exponentiation in a Galois Field of integers modulo a prime number p, GF(p). The invention includes twelve registers for storing n-bit integers, a full adder for shifting left and adding data stored in two of the registers. A feedback register is included for storing a n-bit number and means for generating a feedback number is provided, wherein the feedback number is generated from a prime number, p. Also included are modulo means for reducing data bits stored in the registers modulo a prime number p."

3. Plain-language overview of the independent claims

The 44 claims fall into five families. Independent claims are: 1, 2, 8, 11, 12, 15, 16, 19, 22, 23, 26, 29, 32, 33, 36–44.

Family A — "ring of integers" apparatus (claims 1–7)

Dependents: 3 (adds feedback/modulo means to claim 2), 4 (adds exponentiation via a series of multiplications), 5 (adds an overflow counter), 6, 7.

Family B — Adder chip with base/carry split (claims 8–14)

Dependents: 9–10 (full/half adders under claim 8), 13 (full adders under claim 12), 14 (multiplexer control under claim 13).

Family C — Multiplier chip, plain registers (claims 15–21)

Dependents: 17–18 (full/half adders under 16), 20–21 (full/half adders under 19).

Family D — Multiplier chip with base/carry split and F1–F4 (claims 22–35)

Dependents: 24–25 (under 23), 27–28 (under 26), 30–31 (under 29), 34–35 (under 33) — adding full-adder and multiplexer limitations.

Family E — Method claims (claims 36–44)

4. Litigation / CAFC 2026 docket findings

No CAFC 2026 docket or 2026 litigation involving US 4,891,781 was found.

• The patent's Google Patents record shows status "Expired – Lifetime," anticipated expiration 2007-03-04, i.e., it passed out of enforceable term roughly 19 years before the current date. Unified Patents likewise shows an expiration date of 2007-03-03.
• The only 2026 Federal Circuit material returned in my searches was unrelated: the Contour IP Holding LLC v. GoPro, Inc. docketing notice (Fed. Cir. No. 2026-2012, notice dated July 8, 2026) and the Caltech/Broadcom appellate brief concerning Caltech's '781 patent (a different patent number). Neither involves US 4,891,781.
• Searches for "4891781" in litigation contexts surfaced only: (a) the SafeNet/Deutsche Bank first-lien and second-lien security-agreement schedules (2007) listing "MODULO ARITHMETIC PROCESSOR CHIP – 4891781" among collateral; (b) an EPO/Japanese search-report citation of US 4,891,781 (together with JP 63-282777 and EP 281303) in a later WO application's prior-art table; and (c) the Google Patents citation graph (cited by, among others, US 5,210,710, US 5,261,001, US 5,274,707, US 5,513,133).

Uncertainty: My docket check relied on general web search of public sources (Google Patents, Unified Patents, CourtListener/Justia material surfaced in results, news/legal-press). I could not directly query PACER, the CAFC electronic docket, or Docket Navigator in this session, so I cannot give a categorical "never litigated" answer; I can only state that no 2026 CAFC appeal or pending 2026 case involving this patent is visible in the sources searched, which is consistent with an expired 1990 patent whose maximum term ended in 2007.

5. Other uncertainty / drafting flags (read literally, no auto-correction)

• Filing/priority date discrepancy: Google Patents gives filing 1988-12-22 and priority 1987-03-04; Unified Patents gives 1988-12-21 and 1987-03-03. The specification itself says the application is a continuation of Ser. No. 07/021,066 (filed 1987-03-04) and Ser. No. 07/142,328 (filed 1988-01-04).
• EP 0281303 priority reference reads "04.03.1987 US 21660" — a five-digit number that likely corresponds to Ser. No. 021,066, but I am not auto-correcting it.
• Claim 41 is captioned as an apparatus ("A modulo arithmetic processor chip …") yet recites "the steps, performed by said modulo arithmetic processor chip" — a mixed apparatus/method form preserved literally.
• Claim 26 references "said accumulator means" without antecedent basis (it introduces "accumulator-base means" and "accumulator-carry means") and omits any second-partial-reduction means — likely a prosecution/drafting artifact, reported as printed.
• Inventor/assignee spelling: the patent prints the inventor once as "Omura" and the cited 1986 reference by "Omura et al." (US 4,587,627). Google Patents spells the inventor "Jimmy K. Omura"; the Rivest patent is cited in the specification as "Revest et al." — a literal typo in the patent, not corrected here.

I'll search litigation databases and court records for US patent 4891781.

Let me dig deeper into litigation-specific databases and search by the patent's owner history.

Let me search court records and litigation databases specifically for this patent number.

Litigation Search Report — U.S. Patent No. 4,891,781

Patent: U.S. 4,891,781 — "Modulo arithmetic processor chip"
Inventor: Jimmy K. Omura
Original assignee: Cylink Corp. (current assignee of record: Thales DIS CPL USA, Inc.)
Priority date: March 4, 1987 | Filed: Dec. 22, 1988 | Granted: Jan. 2, 1990
Status: Expired – Lifetime (anticipated expiration March 4, 2007)

Bottom line

I was unable to identify any litigation — past or pending — that asserts, challenges, or otherwise involves U.S. Patent No. 4,891,781 specifically. No case naming this patent as an asserted patent appeared in the sources I searched. If such a case exists, it is not surfaced by the publicly searchable litigation records I was able to reach.

What I searched and what I found

Important disambiguation — Cylink litigation NOT about 4,891,781

My searches surfaced several Cylink-related cases. To avoid any confusion, none of these involve U.S. 4,891,781:

1. Cylink Corp. v. Claus P. Schnorr, Civil Action No. 95-2121 (JR), U.S. District Court for the District of Columbia, decided Sept. 25, 1996 (939 F. Supp. 39).

• Plaintiff: Cylink Corporation. Defendant: Claus P. Schnorr.
• Subject patent: U.S. 4,995,082 (the Schnorr patent — digital signatures), not 4,891,781.
• Posture: Cylink sought a declaratory judgment of non-infringement. The court granted Schnorr's motion to dismiss for lack of an actual controversy (no justiciable declaratory-judgment jurisdiction).
• Source: https://www.courtlistener.com/opinion/[1511666](/patent/1511666)/cylink-corp-v-schnorr/

1. The Cylink / RSA Data Security (PKP) dispute (mid-1990s) concerned RSA licensing and public-key patents, not 4,891,781. Contemporaneous reporting (Cypherpunks list, Aug. 1, 1994) describes the Caro-Kann/Cylink vs. RSA-Data-Security conflict. This is background only and is not a case asserting the '781 patent.

2. US 5,210,710 — "Modulo arithmetic processor chip" — is a related but separate Cylink/Omura patent (same family, listed on the '781 Google Patents page as citing it). If you are looking for litigation over the modular-arithmetic processor technology, the '710 patent is a distinct asset and should be searched separately; I did not confirm any case on it either.

Caveats on completeness

• Public patent-litigation aggregators (Unified Patents, Google Patents litigation data) are not exhaustive for older district-court cases that were never indexed or that were filed in the 1990s, and PACER full dockets require paid access not available to me here.
• Because this patent expired on March 4, 2007, any infringement suit would have had to be filed on or before that date. I found no such filing.
• Given the above, I cannot state affirmatively that litigation exists, and I also cannot rule out an un-indexed 1990s case with certainty. I am expressly flagging this limitation rather than filling the gap with a guess.

Recommended next steps to confirm a negative

If you require a definitive clearance on this point:

1. PACER — run a party search for "Cylink" and "SafeNet" across all district courts (1988–2007 window), then pull dockets to check asserted patents.
2. Lex Machina / Docket Navigator / Derwent LitAlert — patent-specific litigation databases that index by patent number; search 4,891,781.
3. USPTO Patent Assignment / litigation records and the Federal Circuit docket, since any district-court judgment involving this patent would likely have produced an appeal.
4. Request confirmations from Thales DIS CPL USA, Inc. (current assignee of record) or its counsel regarding enforcement history.

No litigation involving U.S. 4,891,781 could be identified in the available public records.

I'll verify the structured data with targeted searches before writing the report.

Proceedings overview

Zero AIA trial proceedings are on file against US 4,891,781 — no IPRs, no PGRs, no CBMs, no derivative proceedings — a total count of 0 active / 0 invalidated / 0 sustained / 0 settled / 0 institution-denied. The canonical "PTAB proceedings on file" block (USPTO Open Data Portal) returns no AIA trial records for this patent, and independent searching (PTAB petitions portal, Unified Patents patent page, docket aggregators) surfaced no petition, institution decision, Final Written Decision, or Federal Circuit appeal. The bottom-line defensive posture is "no PTAB ammunition exists because no PTAB shots were ever fired — and none can be, going forward, because the patent is dead." A defendant facing a demand letter today holds an unusually strong position, but the strength comes from expiry, not from IPR outcomes: there are no canceled claims to point to, and equally no surviving claims to worry about.

Proceedings

No proceedings to report

There is nothing to itemize. For the record, here is why the universe is empty, field by field:

Note on a related but distinct channel (flagged, not scored): the AIA-trial block does not cover ex parte reexamination or the (pre-2018) inter partes reexamination, which existed long before the AIA. I found no reexamination certificate referenced in the sources I could reach, but I could not query the USPTO reexamination database directly in this session, so I state this as an unverified negative, not a confirmed one. If a reexam certificate were ever issued, it would appear in PatentCenter for 4,891,781.

Also flagged as unverified: the foreign family member EP 0281303 A2/A3 (Cylink) could in principle have drawn an EPO opposition — that is a European proceeding, not a PTAB proceeding, and I could not confirm or exclude one from the sources reachable here. It is outside the scope of this report but is the one plausible place a real adversarial challenge to this family would sit.

Strategic summary

Claim status: 44 of 44 claims UNTESTED at the PTAB — but all 44 are expired. No claim of US 4,891,781 has ever been canceled, confirmed, or even construed by the Board; there is no IPR certificate, no FWD, no statutory disclaimer on file in this proceeding context. Standing alone, that would be a warning to a defendant: the whole claim set — including the independent apparatus claims 1, 2, 8, 11, 12, 15, 16, 19, 22, 23, 26, 29, 32, 33 and the method claims 36–44 — remains textually intact and has never been narrowed by an administrative tribunal. But that warning is neutralized by the 2007-03-04 expiration. A patent that expired in 2007 cannot support a live infringement claim: damages reach only pre-expiration infringement, and the § 286 six-year lookback window closed in 2013. So the correct reading is not "hardened patent with 44 live claims" but "silent patent with 44 moot claims." The absence of any IPR is best explained by the same fact that explains the absence of any litigation: nobody asserted this patent while it was alive, and no rational petitioner spends IPR money on a patent with no revenue stream to attack.

Estoppel landscape: empty — § 315(e)(2) estops nobody. Because no IPR ever reached a Final Written Decision, there is no IPR estoppel against any party or privy. Likewise, no § 325(e)(2) PGR estoppel. For a defendant currently facing assertion, that means the entire prior-art field remains open — there is no "raised or reasonably could have been raised" bar, and no PTAB record to cut against you at the district-court level (no petitioner admission, no Board claim construction, no adverse credibility findings). Concretely: every ground in the previously generated prior-art analysis — the GF(2ᵐ) hardware multipliers (US 4,037,093; 4,162,480; 4,251,875; 4,538,240; 4,574,361; 4,587,627), the public-key method patents (US 4,200,770; 4,218,582; 4,405,829; 4,424,414; 4,567,600), and the RSA-chip non-patent literature (Barrett; Sedlak & Golze; Rankine; Kochanski; Rivest; Orton et al.) — remains fully available in a district court, and the same-inventor Omura references (US 4,587,627 and US 4,567,600) remain un-adjudicated for § 102(e)/double-patenting purposes. The prior-art section's flag that the file wrapper was never reviewed matters more here, not less: with no IPR record, the only validity history on this patent is the original 1987–1989 prosecution, which no one has ever supplemented or challenged.

Pattern signals: the null pattern is itself the signal. No petitioner filed against this patent — not once, not by a defensive aggregator, not by an operating competitor. Unified Patents has no proceeding and no litigation entries on its page for US-4891781-A; there is no evidence of Unified, RPX, AST, LOT, or OIN in the chain (consistent with the assignment report, which found the chain terminates at an operating security vendor via SafeNet → Gemalto → Thales). There is no repeat-petitioner pattern, because there is no petitioner at all. There is no patent-owner appeal pattern, because the owner never had a Board loss to appeal — and no CAFC appeal of any FWD exists. This is the profile of a defensive, internal-use, or never-monetized patent, which matches the prior sections' conclusion that the ownership chain is non-asserting and that the patent was never asserted in any located litigation.

Recommended next steps

1. Do not build an IPR-based defense strategy around outcomes that do not exist. There is no FWD to link to, no canceled claim to quote, and no estoppel to invoke. If a demand letter cites this patent, the dispositive argument is expiry, not invalidity: US 4,891,781 expired 2007-03-04 (anticipated; Unified Patents: 2007-03-03), so pre-suit damages under 35 U.S.C. § 286 are time-barred and prospective relief is impossible.
2. Confirm the negative directly at the source. Run the patent number through the USPTO PTAB E2E / PTAB End-to-End system and the USPTO Open Data Portal (ODP) trials API to reproduce the zero-count result, and pull the PatentCenter file wrapper for 4,891,781 to confirm (a) no reexamination certificate, (b) the prosecution history the prior-art section flagged as unretrieved, and (c) whether any terminal disclaimer or certificate of correction exists.
   • PTAB E2E: https://ptab.uspto.gov/ (search Patent No. 4,891,781 under "Patent Number")
   • PTAB decisions archive: https://www.uspto.gov/patents/ptab/decisions
   • CourtListener (confirm no CAFC appeal): https://www.courtlistener.com/?q=%224%2C891%2C781%22
3. Check the foreign family member for the only plausible adversarial challenge. EP 0281303 (Cylink; priority US 21,660) is the one family asset that could have drawn an EPO opposition. That is not a PTAB matter, but if diligence requires the complete adversarial history of this technology family, query the EPO Register and the EPO Opposition database for EP 0281303. I could not confirm one way or the other here.
4. Treat "no PTAB activity" as consistent with — not proof of — non-assertion. The litigation section already reached a qualified negative on assertion. The PTAB record adds corroboration: well-asserted patents almost invariably attract IPRs; this one attracted none, over the entire ~14-year window (2012-09-16 to today) in which IPRs have existed while the patent remained citable in briefs. The two findings reinforce each other.

Constraint honored: no proceeding numbers have been invented, because there are none to report. Where I could not verify (reexamination, EP opposition), I have said so rather than filling the gap.

I'll research the assignment/ownership record for US 4,891,781, building on the prior sections. Let me search the assignment databases and related sources.

Let me dig deeper into the specific assignment records, reel/frame numbers, and the correspondent details.

Let me try to pin down the specific reel/frame numbers and correspondent details for the recorded assignments.

Assignment / Ownership Analysis — U.S. Patent No. 4,891,781

"Modulo arithmetic processor chip" | Inventor: Jimmy K. Omura | Original assignee: Cylink Corp.
Priority 1987-03-04 · Filed 1988-12-22 · Granted 1990-01-02 · Expired 2007-03-04 · 44 claims

Scope note and building on prior sections. This section assumes the two earlier sections (patent summary and litigation/PTAB findings) and does not repeat them. One fact from those sections drives everything below: no litigation and no PTAB proceeding has ever involved this patent, so there is no "pre-litigation transfer" event to anchor. I also flag upfront a material data limitation: I could not retrieve the reel/frame numbers or the correspondent-of-record fields from USPTO Assignment Center in this session (the tool hit its search ceiling before the Assignment Center record could be parsed). The conveyance types and recording dates below are taken from the Google Patents legal-events block, which does not expose reel/frame or correspondent. Those two fields — the exact fields your task says are "the most useful tell" — are therefore unverified here and are called out as such rather than guessed.

Inventors

Notes and patterns:

• Single-inventor patent. There is no co-inventor, so no "all inventors departed within 12 months" pattern can exist here. There is no evidence Omura left Cylink at or near filing — he is the named inventor on the same-assignee continuation US 5,210,710 (filed 1990-10-17, ~2.5 years after this filing), which is itself evidence of continued association with Cylink.
• Inventor overlaps with the prior art of record. This is worth flagging because it colors the prosecution history (analyzed in the prior-art section) and the "who owned this technology" question:
  • Omura is a named inventor on two of the 22 cited references: US 4,587,627 ("Computational method and apparatus for finite field arithmetic," Massey & Omura, Omnet Associates, issued 1986-05-06) and US 4,567,600 ("Method and apparatus for maintaining the privacy of digital messages…," Massey & Omura, issued 1986-01-28).
  • Co-founder Elwyn Berlekamp is the named inventor on cited reference US 4,162,480 ("Galois field computer," Cyclotomics, Inc.). Cyclotomics was Berlekamp's own company.
  • So the cited prior art includes work by the inventor and by his Cylink co-founder. The '781 patent was filed after those references issued, in the same technical space.

Original assignee

Cylink Corporation (address of record on the issued patent and later assignment documents: Sunnyvale/Santa Clara, CA; Google Patents prints the assignee as "Cylink Corp").

Assignment timeline

Important: the assignment record for this patent is not empty — there are four recorded post-issuance events shown in the Google Patents legal-events block (one security interest, one merger, two liens). What is missing from my retrieval is the reel/frame and correspondent for each, which are the fields Assignment Center exposes but Google Patents does not. I am not fabricating those fields.

Downstream corporate succession (reported as current assignee, but with no assignment event I could retrieve): Google Patents lists the Current Assignee as "Thales DIS CPL USA Inc", while itself disclaiming accuracy ("The listed assignees may be inaccurate"). The reported chain is:

SafeNet → Gemalto (Gemalto acquired SafeNet in 2015) → Thales (Thales acquired Gemalto in 2019; Thales DIS CPL USA is the U.S. identity in that group).

I could not retrieve a recorded USPTO assignment documenting the SafeNet→Gemalto→Thales steps on this patent's abstract of title. It is possible (a) those transfers were recorded in bulk under a different reel/frame or (b) Google's "current assignee" is a corporate-family inference (it maps parent companies) rather than a recorded assignment. Flagged as unresolved.

Related foreign-family ownership datapoint: the Japanese family member surfaced in a third-party search report as JP 63-282777 A, published 1988-11-18, listed with applicants "Ricoh Co., Ltd., Cylink Corp." (alongside EP 0281303 A and US 4,891,781 A). Read literally, this suggests the Japanese counterpart was filed with Ricoh and Cylink as co-applicants — a foreign ownership divergence from the U.S. record. I flag it rather than resolve it; the search-report grouping may also simply be listing the family, so treat the co-applicant reading as unconfirmed.

Timeline diagram

timeline
    title Ownership of US 4891781
    1983 : Cylink founded by Berlekamp and Omura
    1987 : Parent application filed
    1988 : Continuation application filed
    1990 : Patent issued to Cylink Corp
    2001 : Security interest granted to Silicon Valley Bank
    2003 : Cylink acquired by SafeNet
    2007 : Merger of Cylink into SafeNet recorded
         : First and second liens to Deutsche Bank
    2015 : SafeNet acquired by Gemalto
    2019 : Gemalto acquired by Thales

NPE / troll-pattern signals

Signal tally: 0 of 8 NPE signals present. One securitization cluster (signal 4) is present but is a lender-collateral pattern, not an NPE pattern. Two fields (reel/frame, correspondent) that would harden the negative are unverified.

Verdict

Defensive / non-asserting.

The recorded chain is a straight operating-company ownership line with a financing overlay — Cylink Corp. (original assignee, operating) → SafeNet, Inc. (by merger, recorded 2007-04-05) → Deutsche Bank Trust Company Americas as collateral agent (first lien 2007-04-16; second lien 2007-04-19) → reported corporate successor Thales DIS CPL USA Inc. — with no licensing-only shell, no known asserter, and no assertion event on this patent. I am choosing "Defensive / non-asserting" on substance (never asserted; owned throughout by operating companies; the asset has been fully neutralized by its 2007-03-04 expiration), and I explicitly note the template caveat: this chain does not terminate at a named defensive aggregator (RPX/AST/LOT/Unified/OIN), so the label fits the "non-asserting" half of the definition but not the "terminates at an aggregator" parenthetical. If strict literal template matching is required, the formal fallback is Insufficient data, because the two fields most probative of an NPE pattern — reel/frame and correspondent of record — could not be retrieved for any link.

An important cross-reference note for the reader: the earlier litigation section reached "no litigation" and the PTAB section reached "zero AIA trials." This assignment analysis is consistent with both — a chain of operating companies that never sold the patent to an NPE, and a patent that expired in 2007 with no post-grant challenge, is exactly the profile of an unasserted, expired corporate asset, not a troll vehicle. The one thing that could change this picture (a repeat-player correspondent on those four 2007 recordings) is precisely the field I could not verify.

Verification links and next steps to close the gap

• USPTO Assignment Center (search by "4891781"): https://assignmentcenter.uspto.gov/ and the legacy interface https://assignment.uspto.gov/patent/index.html
• Retrieve, for each of the four recordings, the reel/frame + execution date + correspondent — pull the "Assignment Abstract of Title" for application 07/289,124 and check whether a single attorney/firm filed the 2007-04-05 merger and the 2007-04-16/19 liens (they likely share corporate/financing counsel — expected in a take-private, and not by itself an NPE signal).
• Confirm the SafeNet→Gemalto→Thales recordation. If no assignment appears on this patent's abstract of title, verify via Thales/Gemalto's USPTO bulk recordings whether the transfer was recorded; Google's "current assignee" may be a corporate-family inference.
• Resolve the JP 63-282777 co-applicant question (Ricoh / Cylink) if foreign ownership is in scope.
• Cross-check Unified Patents and RPX directories for any of the five named entities as asserters — none appeared in my searches, consistent with the non-asserting verdict.

Constraint compliance: no assignment was fabricated. The four recorded events are reported as surfaced by Google Patents legal events; reel/frame and correspondent fields are reported as not retrieved rather than invented, and every entity in the chain is named from a source rather than inferred from naming alone.

I'll research the cited prior art for US 4,891,781. Let me gather authoritative details on the key references.

Prior Art Analysis — U.S. Patent No. 4,891,781

Patent: "Modulo arithmetic processor chip" · Inventor: Jimmy K. Omura · Original assignee: Cylink Corp.
Priority: 1987-03-04 · Filed: 1988-12-22 · Granted: 1990-01-02 · Status: Expired (2007)
Source of record: https://patents.google.com/patent/US4891781/en (full text, claims, and citation tables supplied above)

Scope note (strict, literal reading)

I analyzed exactly US 4,891,781. I did not substitute any similarly numbered patent. Note two near-collisions the search results produce and that I am expressly not using:

• US 5,210,710 — a different Omura/Cylink patent, same title ("Modulo arithmetic processor chip"), which appears in the '781 "Cited By" table. It is a separate asset and is treated below only as a double-patenting/§ 103 candidate, never as a § 102 reference to itself.
• US 7,916,781 — Caltech's patent (asserted in Caltech v. Apple/Broadcom). Unrelated number.
• The search hits for "4891781" that return a Minnesota PUC receptor ID / a "Prime Curios" page / a Soviet thermos-siphon document are false positives — not this patent.

The 22 U.S. patent citations and the non-patent citations below are taken verbatim from the '781 patent's own citation tables (the authoritative text in the user message), supplemented by Google Patents / EPO / FreePatentsOnline records for the descriptions. Dates are the priority and publication dates printed in the citation table.

1. Framework for the § 102 question

Every one of the 22 cited patents published more than one year before the '781 priority date (1987-03-04) — the youngest, US 4,697,248, issued 1987-09-29 after the priority date, so it is § 102(a)/(e) art at best; the rest are § 102(b) art. That is not, however, the hard part. The hard part is element coverage.

The '781 independent claims require a specific combination of:

1. an integer-modular (GF(p) / "ring of integers modulo p") datapath, not a characteristic-2 field;
2. a feedback number F = 2ⁿ − p (the "two's complement of p," i.e. 2ⁿ mod p) held in a feedback register;
3. base/carry (A₁/A₂, B₁/B₂, C₁/C₂) register pairs and a time-shared full-adder array that shifts-and-adds; and
4. reduction of the accumulator modulo p, with overflow index I mapped to F₁, F₂, F₃, F₄.

No cited reference discloses all of these. Accordingly, the honest § 102 conclusion is that none of the 22 cited patents anticipates any independent claim of the '781 patent as a whole, and most are § 103 (obviousness) references, not § 102 references. I flag the few places where a reference comes closest, and I identify the claims each reference is most relevant to, which is what a § 102/§ 103 mapping actually turns on.

2. The cited prior art, reference by reference

Group A — Public-key cryptographic method patents (motivational art; § 103 only)

Why Group A matters at all: the '781 specification itself adopts this frame ("cryptographic systems transmitting a computationally secure cryptogram… described in … U.S. Pat. No. 4,200,770 to Hellman et al., U.S. Pat. No. 4,405,829 to Revest [Rivest] et al., U.S. Pat. No. 4,218,582…, and U.S. Pat. No. 4,424,414…"), and states that "none of these patents teach how to build a processor chip… for implementing their broad inventive concepts." That is the applicant's own admission that the novelty sits in the hardware realization. It makes these four patents § 103 backdrop, not § 102 anticipators.

Group B — GF(2ᵐ) finite-field arithmetic hardware (the closest art; § 102/§ 103 backbone)

The Group-B takeaway: the cited set is dominated by GF(2ᵐ) hardware (Berlekamp, Gregg, Sperry, Toshiba, IBM). These share the general idea of a dedicated finite-field datapath but operate in a fundamentally different algebraic structure (polynomial arithmetic, XOR, no carries) and use a different reduction mechanism (mod g(x)) from the '781's integer-modular F = 2ⁿ − p feedback. That structural divergence is what defeats § 102 and confines these to § 103.

Group C — Same-inventor / common-entity references (highest practical relevance)

Data point: the EPO search report for US 4,587,627 lists US 4,037,093 (Gregg) and US 4,162,480 (Berlekamp) as cited art — confirming that the Omura/Massey line itself sits on top of the Gregg/Berlekamp GF(2ᵐ) hardware, which is why the '781 examiner pulled the same references forward.

Group D — Block-cipher / cryptographic-hardware patents (peripheral; § 103 context only)

US 3,522,374 (Ciphering unit, Int. Standard Electric, 1966-06-17/1970-07-28); US 3,657,476 (Cryptography, H. Aiken, 1970-01-23/1972-04-18); US 3,781,472 (Digital data ciphering technique, Datotek, 1971-04-15/1973-12-25); US 3,796,830 (Recirculating block cipher, IBM, 1971-11-02/1974-03-12); US 3,798,359 (Block cipher, IBM, 1971-06-30/1974-03-19); US 3,868,631 (Digital cryptographic system, Datotek, 1972-10-20/1975-02-25); US 3,876,832 (Digital cryptographic system, B. O. Morgan, 1972-10-20/1975-04-08); US 3,958,081 (Block cipher for data security, IBM, 1975-02-24/1976-05-18); US 3,962,539 (Product block cipher, IBM, 1975-02-24/1976-06-08); US 3,979,558 (Signaling system, Bell Telephone Labs, 1944-06-30/1976-09-07).

Description: classical symmetric block-cipher / ciphering-unit hardware (Feistel-style substitution–permutation engines, key generators, recirculating block ciphers). These are the patents the '781 specification dismisses as "the conventional cryptographic solution … requires the prior possession of a common secret key."

§ 102 relevance: none. They disclose neither finite-field modular arithmetic, nor shift-and-add multiplier datapaths, nor feedback-number reduction. They are, at most, general background establishing that cryptographic engines were known to be built as dedicated hardware — which is § 103 context, not anticipation.

3. Non-patent citations (printed publications; § 102(b) art)

The '781 patent cites (as printed) — among others:

• Abbruscato, C. R., "Data Encryption Equipment," IEEE Communications Magazine, vol. 22, No. 9, Sep. 1984.
• Barney, Clifford, "Cypher Chip Makes Key Distribution a Snap," Electronics, Aug. 7, 1986. — contemporaneous press coverage of a public-key cipher chip; directly bears on the state of the hardware art at the priority date (§ 103).
• Barrett, Paul, "Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor," Computer Security Ltd., Aug. 1986. — the canonical RSA-on-a-DSP implementation paper; the most relevant § 103 NPL for "modular exponentiation in hardware."
• Beth, T., Cook, B. M., Gollmann, D., "Architectures for Exponentiation in GF(…)" — survey of finite-field exponentiation architectures; § 103 for claim 4 / exponentiation claims.
• Plus the standard references Diffie & Hellman, "New Directions in Cryptography," IEEE Trans. Info. Theory, Nov. 1976 and Rivest, Shamir & Adleman (1978) cited in the family members (EP 0281303 / EP 0085130 / EP 0080528).

§ 102 effect: these NPL items describe algorithms and software implementations, not the claimed register/adder chip. They cannot anticipate an apparatus claim, but Barrett and Beth et al. are strong § 103 references for the "implement GF(p) exponentiation in dedicated silicon" motivation.

4. Ranked conclusion — most relevant prior art

Bottom line: the single most relevant prior art for US 4,891,781 is US 4,587,627 (Massey & Omura), followed closely by US 4,567,600 (Massey & Omura) — both same-inventor GF(2ᵐ) arithmetic-hardware patents — then the Berlekamp GF1 computer (US 4,162,480) and Gregg's GF(2ᵐ) matrix multiplier (US 4,037,093). The RSA patent (US 4,405,829) and the Hellman patents supply the purpose (§ 103), and the block-cipher patents supply only background.

No cited reference discloses the full combination required by any '781 independent claim — specifically the integer (GF(p)) datapath with a feedback number F = 2ⁿ − p, base/carry register pairs, a time-shared full-adder, and overflow-index I → {F₁,F₂,F₃,F₄} reduction. On the cited art alone, the case against the independent claims is an obviousness case, not an anticipation case.

5. Caveats and flags (read literally; no auto-correction)

1. Same-inventor / § 103(c) and double-patenting. US 4,587,627 and US 4,567,600 list J. K. Omura as a co-inventor. A reference naming the same inventive entity is not "by another" under § 102(a)/(e), and their status as § 102(b) art depends on the controlling date (grant 1986-05-06 / 1986-01-28 vs. priority 1987-03-04 vs. filing 1988-12-22). I flag this rather than resolve it, because it turns on the § 120 benefit chain (parent Ser. No. 07/021,066, filed 1987-03-04; Ser. No. 07/142,328, filed 1988-01-04). The sibling US 5,210,710 is an obviousness-type double-patenting candidate to examine separately.
2. US 4,697,248 (Sony) post-dates the '781 priority date (1987-09-29 vs. 1987-03-04) and therefore is not § 102(b) art; treat as non-prior-art unless a § 102(e) date is established.
3. Anticipation vs. obviousness. Where I say "bears on claim N," I mean § 103 relevance unless the reference discloses every element — which, on the records reviewed, none does for an independent claim.
4. Not reviewed: the actual file wrapper / examiner's citations and rejections for US 4,891,781 (Google Patents shows the citation list but not the office actions). As flagged in the previously generated sections, the prosecution history has not been retrieved; any Grounds of Rejection the examiner actually made would be the definitive statement of which references were treated as § 102 vs. § 103 art. Confirm via PatentCenter.
5. Dates are as printed in the '781 citation tables; where Google/Unified differ by one day (as in the '781 filing/priority dates), I have used the patent's own printed table for the citations and flagged that the '781's own dates carry a 1-day indexing discrepancy.

Sources: Google Patents US4891781 (citation tables, claims, specification); https://patents.google.com/patent/US4587627A/en ; https://patents.google.com/patent/US4567600A/en ; https://patents.google.com/patent/US4037093A/en ; https://patents.google.com/patent/US4162480 ; EP 0080528 / EP 0085130 (EPO); FreePatentsOnline US4587627.

I'll ground a few specifics on the key references before building the § 103 combinations, since the strength of an obviousness case turns on exactly what each reference discloses and what the art already knew.

Let me pin down the non-patent literature cited on the face of the patent and the sibling Cylink/Omura patent, since those matter for both the motivation-to-combine and double-patenting strands.

Obviousness Analysis — U.S. Patent No. 4,891,781 under 35 U.S.C. § 103

Patent: "Modulo arithmetic processor chip" · Inventor: Jimmy K. Omura · Assignee: Cylink Corp. (orig.)
Priority: 1987-03-04 · Filed: 1988-12-22 · Granted: 1990-01-02 · Expired: 2007-03-04 · 44 claims
Governing law: pre-AIA § 103 (priority well before 2013-03-16). The KSR flexible-rationale framework nonetheless applies to any obviousness determination made today.

Builds on, does not repeat, the Prior Art section. That section established the element-coverage conclusion I adopt here as the premise: no single cited reference discloses the full combination of any independent claim, so this is a § 103 case, not a § 102 case. This section supplies the combinations and the motivations to combine.

Metadata contradiction flagged: the task header states "Current Date: April 26, 2026," whereas the earlier sections and the patent fetch are dated 2026-09-28. Immaterial to the analysis; reported as printed rather than harmonized.

1. The § 103 framework applied

Under Graham v. John Deere, 383 U.S. 1 (1966), and KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007), the inquiry is: (1) scope and content of the prior art; (2) differences between the prior art and the claims; (3) level of ordinary skill; (4) secondary considerations. KSR supplies the rationales that may supply the "motivation": known-method combination yielding predictable results; simple substitution of a known element; use of a known technique to improve a similar device in the same way; application of a known technique to a known device ready for improvement; "obvious to try"; and design incentives/market forces. The Federal Circuit's pre-KSR strict TSM requirement no longer controls.

Exhaustion of the § 102 question (adopted from the Prior Art section): the 22 on-face cited patents are § 102(b) art except US 4,697,248 (issued 1987-09-29, after the 1987-03-04 priority — § 102(a)/(e) at best). The prior-art section found the cited set to be motivational (Hellman/RSA method patents) or structurally adjacent but algebraically different (GF(2ᵐ) hardware). That asymmetry — same problem, different algebraic structure — is the classic § 103 setup.

2. Level of ordinary skill in the art (PHOSITA), as of March 1987

A person holding an M.S. (or Ph.D.) in electrical engineering or computer science, or a B.S. with 3–5 years' experience, in digital logic design for cryptographic and error-control arithmetic, who is:

• familiar with bit-serial "shift-and-add" multipliers (standard since at least the 1950s–60s) and with carry-save / redundant-carry accumulator techniques for suppressing carry propagation;
• familiar with finite-field arithmetic hardware — GF(2ᵐ) multipliers of the Massey–Omura, Berlekamp, and Gregg types (all in the cited art);
• aware of the public-key arithmetic problem (Diffie–Hellman/RSA modular exponentiation) and of the contemporaneous literature on implementing it in hardware — including Barrett (Aug. 1986), which is on the face of this very patent, and Beth, Cook & Gollmann, "Architectures for Exponentiation in GF(2ⁿ)," CRYPTO '86, LNCS 263, pp. 302–310 (also on the face);
• aware of Montgomery, "Modular multiplication without trial division," Math. Comp. 44(170):519–521 (April 1985) — the standard technique for eliminating costly division during modular reduction by precomputing a modulus-dependent constant. (Identified in this session; not an on-face citation.) [https://www.ams.org/journals/mcom/1985-44-170/S0025-5718-1985-0777282-X/]

That is a highly relevant, very narrow PHOSITA. That cuts both ways: it makes the idea of dedicated modular-arithmetic silicon obvious, but it also makes fine architectural distinctions more likely to be found obvious, because the artisan knows the whole toolbox.

3. The differences the combinations must bridge

From the Prior Art section, distilled to the four elements that actually separate the '781 claims from the art:

Critically, the specification itself concedes E2/E3's status. It states that "a partial reduction at each stage can be performed using the relationship in Eq. (1)," and that "the above alternative representations for A, B, and C are not unique, [so] there is some freedom to choose representations that are easy to implement." Those are applicant admissions that the asserted contribution is an optimization choice within a known design space — strong § 103 ammunition.

4. Ground A — Claim 1 (and dependents 4, 5; method analogs)

Combination: US 4,587,627 (Massey & Omura) + US 4,162,480 (Berlekamp) + US 4,405,829 (Rivest/Shamir/Adleman) + Barrett, CRYPTO '86 (optionally + Montgomery 1985).

Motivation to combine (KSR rationales (A), (B), (C), (F), (G)):

1. Same field of endeavor / same problem (MPEP 2141.01(a)). '627 and '600 (both Omura's own) exist to compute fast finite-field multiply/exponentiation for cryptography. '829/'770/'414 state the cryptographic purpose. The '781's stated object — "to provide a processor chip for performing an exponentiation operation in a rapid manner" — is that same purpose. The artisan looking to build RSA/Diffie–Hellman hardware is the same artisan who reads '627.
2. Known technique improving a similar device in the same way. '627 already teaches the architectural recipe the '781 uses: two shift registers + shared, time-shared logic + shift-and-square to exponentiate. Porting that recipe from GF(2ᵐ) to GF(p) changes the reduction rule, not the recipe.
3. Simple substitution + predictable result. Once the datapath is an integer accumulator, the reduction obligation is unavoidable: a n-bit accumulator that overflows produces a 2ⁿ term, and in GF(p) 2ⁿ ≡ F (mod p) where F = 2ⁿ − p. That identity is elementary and appears verbatim in the '781 specification (Eq. 1). Substituting the precomputed constant F for the 2ⁿ term is the same kind of move Montgomery and Barrett teach (precompute a modulus-derived constant; replace a division/reduction with an addition).
4. Design incentive / market forces. Barrett's paper reports a full RSA implementation on a single DSP and reports times "below one second … on second generation parts." That is the express competitive pressure pushing a 1986–87 artisan toward dedicated modular silicon. KSR endorses exactly this: "design incentives and other market forces."

Against Ground A: the GF(2ᵐ) → GF(p) step is not purely mechanical; carry-less and carry-propagating arithmetic differ. This is the strongest available nonobviousness argument, and it is weakened by the fact that the cited set also contains integer-oriented art (RSA '829) and that the '781's own base/carry scheme is a standard carry-save trick.

5. Ground B — Claim 2 (and 3, 6, 7)

Claim 2 is an adder reciting X/Y/A₁/A₂/B₁/B₂/C₁/C₂ registers, control means, and a full adder that adds B into C on the control bit. It does not recite the feedback register, the feedback-number generator, or the modulo means (those arrive only via dependent claim 3).

Combination: US 4,162,480 (Berlekamp) in view of US 4,037,093 (Gregg).

This is the weakest claim in the patent. What it recites is, in substance, a carry-save accumulator with a partitioned base/carry register file and control logic — a textbook adder structure. Berlekamp supplies the "dedicated finite-field arithmetic unit with register file, hardwired arithmetic logic, and control" teaching; Gregg supplies the "serial shift-and-add with gated partial products" teaching. There is no asserted mechanism here that is not a generic adder. Claim 2 is closer to a § 102 problem (anticipation by a suitable carry-save accumulator reference) than to § 103, and at minimum falls to a two-reference combination with a trivial motivation (both references address the same end: fast finite-field arithmetic).

6. Ground C — Claims 8, 9, 10, 12, 13, 14, 36, 38, 44 (the "single-F" adder family)

Combination: Montgomery (1985) + US 4,162,480 (Berlekamp) + Rivest '829, optionally + Willoner & Chen, "An algorithm for modular exponentiation," Proc. 5th IEEE Symp. Comput. Arith., pp. 135–138 (1981) and Blakley, "A computer algorithm for calculating the product AB modulo M," IEEE Trans. Comput. C-32:497–500 (1983).

What the claims add over claim 2: F = 2ⁿ − p stored in feedback means; an overflow counter; fetching F into the B register and adding it back when overflow occurs; and mod-p reduction when C > p. That is the entire content of the difference.

Motivation:

• Montgomery 1985 teaches the genus of what these claims recite: represent residues so that "addition and subtraction algorithms are unchanged," precompute a modulus-derived constant (N′), and fold the modular reduction into the accumulation loop rather than performing a division. Claims 8/12/44's "add F back when the accumulator overflows, then reduce if C ≥ p" is a species of that genus — indeed Montgomery's REDC ends with exactly the final conditional subtraction ("if t ≥ N then return t − N else return t") that claims 8/12/44 recite as "reducing … when C is greater than p."
• Blakley 1983 and Willoner & Chen 1981 show that modular multiplication/exponentiation algorithms designed for hardware accumulation — including overflow handling — were squarely in the 1981–83 literature.
• The KSR "obvious to try" rationale applies with unusual force: there were a finite number of identified, predictable ways to reduce an overflowing accumulator mod p (do the division; use Barrett's reciprocal; use Montgomery's N-residue form; or substitute 2ⁿ ≡ F). Choosing one of them is not invention.

7. Ground D — Claims 11, 37 (the F₁–F₄ / overflow-index family)

Combination: Ground C references + US 4,037,093 (Gregg) (for the parallel two-step full-adder summation of base and carry bits), or simply Ground C + the specification's own admissions and the general knowledge of precomputed multiples of a modulus.

What claim 11 adds: F₂ = 2F₁ mod p, F₃ = 3F₁ mod p, F₄ = 4F₁ mod p; a two-stage full-adder summation (base+base, then carry); and selecting F₁–F₄ according to overflow index I ∈ {1,2,3,4}.

Motivation — this is the most easily dispatched "extra" element in the patent:

1. The '781 specification gives the recipe away: "Recall that we have the feedback term … F₂ can be obtained from F₁ by a simple shift … F₃ and F₄, however, may require a mod p reduction. Only F₁, F₃, and F₄ are stored in registers. F₃ and F₄ are computed using the flow diagram of FIG. 9." The claim's F₁–F₄ are thus three doublings/additions of a value already known — arithmetic, not architecture.
2. The problem is one of counting, not inventing. Where a first- and second-bit-position component can each produce overflow, the maximum overflow is 2 or 4; a lookup table indexed by a small counter is the definitional solution. A one-to-four-entry table adds no patentable weight under KSR's "familiar elements according to known methods."
3. Precomputing small multiples of the modulus is pervasive in modular multiplication (Booth recoding of a multiplier/modulus; Montgomery's N′; Barrett's μ) — an artisan would reach for it reflexively.

8. Ground E — Claims 15, 16, 17, 18, 40 (multiplier; single-F)

Combination: US 4,587,627 (Massey & Omura) + Montgomery 1985 + Barrett, CRYPTO '86 + US 4,405,829.

Claim 15's asserted advance: (i) a first partial reduction — add F to B when B's MSB shifts left out of the register (keeping B to n bits); (ii) shift-and-add accumulation keyed to the LSB of A; (iii) an overflow counter I; (iv) a second partial reduction — at completion, multiply I by F and add the product back into C; (v) final mod-p reduction.

Motivation:

• The first/second partial reductions are the same single idea applied at the two places an overflow can arise. The specification admits it: "a partial reduction at each stage can be performed using the relationship in Eq. (1). This partial reduction allows representing all integers by n binary symbols." Keeping every register to n bits was the design constraint; a 2ⁿ term leaks out at exactly two points — when B is left-shifted, and in the accumulated overflow counter. An artisan who has decided (as the specification concedes) to do partial reduction at each stage would apply it in both places.
• Accumulating overflows in a counter and correcting once at the end is the standard double-precision accumulation pattern. The '781 spec even justifies it on effort grounds: "the counter value I is at most a 14-bit integer, and the shift and add cycles associated with adding IF₁ … is short compared to the original shift and add cycle."
• Barrett independently teaches precisely the "defer the reduction, then apply a scaled correction" structure (longmult → longmod, with the reduction result "always in the range 0 to 3M − 1 … at most two further subtractions").
• Claim 16 (identical minus the first partial reduction) and claim 19 (identical minus the overflow compensation) are the intermediate variants. Under KSR's "obvious to try," where a known improvement has optional components, claiming each subset is not a separate invention — the artisan would select the subset that fits the area/speed budget. Claims 16 and 19 are, structurally, claims to a fraction of claim 15's elements, which the case law treats as more obvious, not less.

9. Ground F — Claims 22, 23, 26, 29, 32, 33, 34, 35, 42, 43 (base/carry multiplier family)

Core combination: US 4,587,627 (Massey & Omura) + US 4,162,480 (Berlekamp) + Montgomery 1985 + Barrett + Rivest '829, with Gregg '093 for the parallel full-adder summation.

Claim 29 (the simplest member) recites only: base/carry registers for A and B; a single F₁ = 2ⁿ − p; base/carry full-adder accumulation; overflow means; final mod-p reduction. This is Montgomery's REDC algorithm implemented with carry-save registers driven by a shift-add loop. Two references, one motivation (avoid serial carry propagation while doing modular accumulation), predictable result. Strong § 103; arguably § 102 over a suitable carry-save modular-multiplier reference.

Claims 23 and 33 (no first partial reduction) and claims 26 (no second partial reduction / no overflow compensation) are again the subtractive variants, each individually weaker.

Claim 22 and claim 32 (the full feature sets) are the hardest, requiring the F₁–F₄ table (Ground D) and both partial-reduction stages (Ground E) on top of the base/carry architecture. The motivation is cumulative but coherent: it is one engineering objective — keep every register to n bits while pipelining a base/carry multiplier — and the claims are the union of the techniques that objective drives.

10. Consolidated mapping and relative strength

11. Secondary considerations — what exists

Under Graham factor (4), nothing on the record I have supports nonobviousness:

• Commercial success: Cylink was a genuine operating company and sold encryptor hardware (per the Assignment section), but no evidence ties commercial success to the claimed chip architecture rather than to the public-key products generally. No nexus evidence is on the record.
• Long-felt need / failure of others: the technology was being actively pursued by many groups (Barrett; Beth/Cook/Gollmann; the GF(2ᵐ) hardware lineages) — which undercuts "failure of others."
• Copying: no evidence located.
• Unexpected results: none identified; the specification presents the results as engineering tradeoffs ("this is a design choice," "there is some freedom to choose representations").
• Praise/skepticism of experts: none located.

The patent's prosecution history remains unreviewed (a gap flagged in both prior sections). The paper trail — which references the examiner actually cited as § 102 versus § 103, and any Grounds of Rejection — would be the definitive statement of how the Office viewed these combinations, and should be pulled from PatentCenter.

12. Where the § 103 case is weakest — and the two structural escape hatches

1. Non-analogous art. The strongest possible rebuttal is that the GF(2ᵐ) coding/error-control hardware in the cited set is non-analogous to an integer-modular cryptographic processor. I assess this as likely to fail: (a) Berlekamp '480 and Massey–Omura '627/'600 were already aimed at cryptographic applications ('600 is expressly a "privacy of digital messages" patent), placing them in the same field of endeavor; and (b) under KSR, similarity of the problem (fast finite-field arithmetic in dedicated silicon) suffices even across fields. The prior-art section's finding that US 4,201,770-family and RSA '829 are on the face — cryptographic method patents — reinforces the shared field.
2. § 103(c) / common ownership (pre-AIA). The prior-art section flagged that US 4,587,627 and US 4,567,600 name Omura as a co-inventor and were assigned to Omnet Associates, not Cylink. Because the co-invented references have a different inventive entity (Massey + Omura) than the '781 (Omura alone), they are "by another" and available under § 102(a)/(e)/§ 103 — and because Omnet ≠ Cylink, the pre-AIA § 103(c) safe harbor for "commonly owned" subject matter would not automatically disqualify them. Unless a common-ownership/obligation-to-assign relationship existed at the time of invention, the applicant's own foundational work is § 103 art against him. This should be verified against the assignment records (already flagged as partially unretrieved in the Assignment section).
3. Double patenting is a separate track, not § 103. US 5,210,710 ("Modulo arithmetic processor chip," same title, same inventor, Cylink) is an obviousness-type double-patenting candidate over the '781, not a § 103 reference against it.

13. Bottom line

• No claim is anticipatable on a single reference; the Prior Art section's conclusion on that point is reaffirmed.
• Every independent claim is vulnerable under § 103. The strongest grounds are the simplest claims — 2, 8, 12, 29, 36, 38, 44 and their near neighbours — where the asserted advance reduces to applying a known modular-reduction technique (Montgomery/Barrett) with known carry-save/hardware-multiplier structure (Berlekamp/Gregg/Massey–Omura) to a known problem (fast RSA/Diffie–Hellman arithmetic).
• The pivot elements are E2 (the F = 2ⁿ − p feedback register) and E4 (the F₁–F₄ overflow table). Neither is disclosed on-face, but each is (a) admitted in the specification as an implementation choice, (b) mathematically trivial (2ⁿ ≡ 2ⁿ − p; Fₖ = kF₁ mod p), and (c) of a kind the contemporaneous art (Montgomery 1985; Barrett 1986) already used. Those elements are therefore motivation-bridged, not disclosure-bridged — which is precisely what § 103 permits post-KSR.
• The claims with the most colourable nonobviousness story are 22, 32, 42, and 43 — the full-feature base/carry multiplier claims combining F₁–F₄ and both partial-reduction stages. Even these fall to a four-reference combination, but the motivation chain is longer and more contestable.

Practical caveat: because the patent expired 2007-03-04 and was never litigated and never subjected to an AIA trial (per the prior sections), this analysis is retrospective and non-accusatory — there is no live validity contest and no § 315(e)(2) estoppel shaping it. Its practical value is defensive and portfolio-oriented: (i) the '781's specification disclosures are themselves citable prior art against later-filed patents, and (ii) the analysis shows what a challenger would have argued had a case ever been brought.

14. Verification steps to firm up the negatives

1. USPTO PatentCenter — file wrapper for 07/289,124 / US 4,891,781. Retrieve the examiner's citations and any Grounds of Rejection, to confirm whether the Gregg/Berlekamp/Omura references were applied as § 102 or § 103 art (the prior-art section flagged the file wrapper as never reviewed).
2. Verify the on-face non-patent citations' dates and content — particularly Beth, Cook & Gollmann, CRYPTO '86, LNCS 263:302–310 (confirmed: https://rd.springer.com/search?dc.creator=T.+Beth) and Barrett, CRYPTO '86, LNCS 263:311–326 (https://doi.org/10.1007/3-540-47721-7_24) — to confirm each predates or is contemporaneous with the 1987-03-04 priority.
3. Confirm the additional art identified in this session (Montgomery, Math. Comp. 44(170):519–521 (1985); Brickell, CRYPTO '82, pp. 51–60 (1983); Blakley, IEEE Trans. Comput. C-32:497–500 (1983); Willoner & Chen, Proc. 5th IEEE Symp. Comput. Arith., pp. 135–138 (1981)), which I located bibliographically via https://cs.uwaterloo.ca/~shallit/bib/arithmetic.bib but did not retrieve in full text. Flag: that bibliography lists Head, "Multiplication modulo n," BIT 20 with an internally inconsistent year field ("1960"); treat that entry as unverified.
4. Confirm the § 103(c) point — whether any common ownership or obligation-to-assign linked Omnet Associates and Cylink at the 1987 invention date, which determines whether the Massey–Omura references are disqualified under pre-AIA § 103(c).
5. Note (not prior art): Takagi (1991) and Takagi & Yajima (1992) on redundant-representation modular multiplication surfaced in this session but post-date the '781 priority by four to five years and are therefore not available against these claims; cited here only to confirm that the redundant-representation approach matured shortly afterward.

No reference, date, or claim number has been fabricated. Where I could not verify a source directly (the file wrapper; the additional 1981–83 algorithm references; the § 103(c) ownership relationship), I have said so rather than filling the gap.