US 4124889

I'll run targeted searches for this specific patent number, then summarize.

Let me search for the claim text and any litigation records specifically tied to this number.

Let me try two more targeted searches for the claim text and any current litigation.

Search results summary

Searches performed (April 26, 2026):

• USPTO / Google Patents full text for "US4124889"
• CAFC 2026 dockets and general litigation queries for "4124889" / "4,124,889"
• Aggregator records (uspto.report, RPX, radaris)

Litigation finding: I found no CAFC 2026 docket activity and no infringement case tied to patent 4,124,889. The only Computer Automation litigation surfaced was AMF, Inc. v. Computer Automation, Inc., 532 F. Supp. 1335 (S.D. Ohio 1982) (CourtListener), which concerned Manex 1000 point‑of‑sale systems and venue/contract issues — not a patent suit over this number. Given the patent expired in 1995, this is unsurprising. I cannot affirmatively state that no 2026 CAFC docket exists; I simply found none.

Bibliographic data — US 4,124,889

Related family (noted, since it can cause confusion):

• US 4,124,888 — "Peripheral‑unit controller apparatus," same inventors, issued the same day (1978‑11‑07), apparently a companion case directed to the controller/microengine itself.
• US 4,315,160 — also titled "Distributed input/output controller system" (Kaufman, Washburn, Stapinski; App. No. 35,263, filed 1979‑05‑01, continuation of Ser. No. 715,174 filed 1976‑08‑17, abandoned). It expressly refers to "No. 4,124,889" as one of "Applicants' Prior Applications," and adds a direct‑memory‑access (DMA) multiplexer.
• Google Patents shows a 1976‑01‑09 priority link to application US05/647,762 (which produced US 4,100,601). I could not verify from an authoritative source that this is a formal priority claim in the '889 patent rather than a database cross‑link — treat that relationship as uncertain.

Abstract

The abstract as indexed by aggregators (consistent with the specification text I retrieved):

"A distributed input/output system is disclosed for controlling numerous peripheral devices and the transfer of data signals and control signals between those devices and a general purpose digital computer. The control system described includes a multiplexer which can accommodate as many as eight input/output devices under the control of separate programmable microcoded peripheral‑unit controllers. Each controller is adapted to be located at or on an individual peripheral device and each is connected to the multiplexer by an identical ribbon cable that is employed to carry both signals and power. Each controller employs a substantially identical microengine, that is, a microcoded processor, currently of five integrated circuit chips. The peripheral‑unit controllers may be configured somewhat differently depending upon whether the peripheral device utilizes data signals in parallel or in series. Data may be transferred directly between a computer memory unit and the peripheral devices without requiring the use of any computer working registers and without requiring subroutines to preserve an ongoing main program."

(Source: radaris inventor index, uspto.report. The Google Patents page I fetched begins at the "Definitions"/description section and does not display the abstract text itself.)

Plain-language overview — and a candid caveat on the claims

Important limitation: the authoritative Google Patents text I retrieved contains the front matter, classification, and full description, but the claims section was not included in the retrieved text, and no search returned the verbatim claim set for 4,124,889. I therefore cannot quote or faithfully number the independent claims. What follows is an inference from the specification and from the companion patent US 4,124,888, and should be treated as such — not as claim language.

Based on the disclosure, the independent claims most likely fall into these buckets:

1. Distributed I/O system architecture (the likely principal independent claim). A general‑purpose digital computer (central processor, main memory, power supply, buses) connected through a common multiplexer to a plurality of controllers — one per peripheral device — where each controller is physically located at or adjacent its own peripheral device, connected to the multiplexer by identical buses, and each contains a substantially identical microengine (a microprogrammed processor). The point of novelty is the distribution of intelligence away from the computer chassis and the standardizing of the interconnect.

2. The microengine / microprogrammed controller. A programmable subunit built from a controller memory (ROM) unit, a ROM program counter, a branch‑address multiplexer, a data selector, and an exclusive‑OR select inverter, where instruction words are selected in dependence on (a) status signals from the peripheral device and (b) a control signal (e.g., the command signal CMD) from the multiplexer, and where counts are either incremented or loaded from an internal branch address or an external branch address from the computer. This is where the "five integrated circuit chips" resides. (The companion patent US 4,124,888 appears to claim this microengine structure explicitly — its claims recite the multiplexer/data‑selector/controller‑memory combination almost verbatim.)

3. Signal transfer / control method claims. Issuing data‑service interrupt and end‑of‑block (EOB) interrupt signals from the controller; prioritizing simultaneous interrupts; and distinguishing a nominal‑duration command signal (250 ns) from a double‑duration command signal (500 ns) as the indicator that the transfer count has reached zero — i.e., a single line encodes end‑of‑block by pulse width.

Key disclosed mechanics useful for understanding the claims:

• Up to four multiplexers, each serving eight controllers; address bus selects multiplexer (AB04–AB07) and controller (AB01–AB03); AB00 is a function bit distinguishing data from control terms.
• Controllers use tri‑state transceivers (e.g., National Semiconductor DM 8835) with receiver‑disable (RDC) and transmitter‑disable (TDC) lines.
• Two controller families: parallel (PPUC) and general‑purpose (GPPUC) controllers, plus serial (SPUC) controllers using a UART and mode register (SMR); the parallel/general‑purpose control signals are driven directly out of the ROMs without interposed buffer registers.
• ROM capacity is 2 × 256‑bit ROMs = 32 sixteen‑bit words, and a jumper (JPPUC) or mode flip‑flop selects one of two 16‑word instruction sets so one controller board can serve either of two device types.
• Cable lengths: IOB up to ~10 ft (one source says 10½ ft), PUIC ~2 ft or less — which the patent argues eliminates the need for per‑device special cable terminations.

Confidence and uncertainty statement

• High confidence: patent number, title, inventors, assignee, application number, filing date, issue date, expiration, and the disclosure content (I have the authoritative full description text).
• Medium confidence: the abstract wording (aggregator‑sourced, but consistent with the spec).
• Low confidence / explicitly uncertain: the exact independent claim language, their number, and their number of independent claims. I did not obtain the claims section. The "overview" above is inferential. If you need the actual claims, the reliable route is the USPTO PatentCenter/PatFT full‑text record for US 4,124,889 or the granted‑patent PDF (the image set on Google Patents), both of which I could not fully retrieve in this session.
• No 2026 CAFC docket activity was found; I cannot prove a negative for docket databases I did not query directly.

I'll search for litigation involving US patent 4124889.

Let me try more targeted searches on litigation databases.

Let me run a few more targeted searches for this specific patent number.

Results: Litigation Search for U.S. Patent No. 4,124,889

Bottom line: I found no litigation specifically involving U.S. Patent No. 4,124,889. No district court case, CAFC appeal, or PTAB proceeding in which this patent was asserted, challenged, or otherwise at issue appeared in my searches. I cannot report plaintiff(s), defendant(s), jurisdiction, case number, filing date, or outcome for a case on this patent because I did not identify any such case.

What the patent is (for identification, so you can confirm we're not conflating numbers)

• Title: "Distributed input/output controller system"
• Patent No.: US 4,124,889
• Application No.: US 05/644,412
• Inventors: Phillip A. Kaufman (Irvine, CA); Jerry R. Washburn (Alhambra, CA)
• Original/current assignee: Computer Automation, Inc. (Irvine, CA)
• Filing date / priority date: December 24, 1975
• Grant date: November 7, 1978
• Legal status: Expired – Lifetime; anticipated expiration December 24, 1995 (per the Google Patents record)
• Related priority: a separate application, US 05/647,762 (Jan. 9, 1976), issued as US 4,100,601

Source: https://patents.google.com/patent/US4124889/en

Important caution — do not confuse this patent with "'889" cases

My searches repeatedly surfaced cases involving different patents that happen to be abbreviated "'889":

• A CAFC matter referencing "the '889 patent" is actually U.S. Patent No. 11,395,889 (an ANDA/pharmaceutical case) — a completely different patent, issued 2022.
• Numerous Unified Patents IPRs and "889" references in PTAB filings relate to unrelated patents.

None of these involve US 4,124,889. Per your strict rule, I am interpreting the number literally and am not attributing these results to 4,124,889.

Cases that are about the assignee (Computer Automation, Inc.) but NOT this patent

To be thorough, I note these cases involve the patent's owner, Computer Automation, Inc., but they are not patent-infringement actions on 4,124,889:

1. AMF, Inc. v. Computer Automation, Inc. — U.S. District Court, S.D. Ohio (Dayton). Case No. C-3-81-223; reported at 532 F. Supp. 1335 (1982). A breach-of-contract/product-liability and venue-transfer dispute (Manex 1000 point-of-sale systems). Not a patent case. Source: https://www.plainsite.org/dockets/1zwf5xke0/ohio-southern-district-court/amf-inc-v-computer-automation-inc/
2. Computer Associates International, Inc. v. Computer Automation, Inc. — U.S. District Court, S.D.N.Y.; 678 F. Supp. 424 (1987). Trademark / unfair-competition / contract dispute over the "CA" mark. Not a patent case. Source: https://www.courtlistener.com/opinion/[1474925](/patent/1474925)/computer-assoc-intern-v-computer-automation/

Search coverage and limitations (stated for candor)

• I searched general web sources and references to the litigation aggregators you named (Unified Patents portal, PACER, CAFC, CourtListener).
• I was unable to complete a direct, exhaustive query of the PACER/Unified Patents litigation case-list portals for this docket — those portals generally require interactive/authenticated queries, and I hit a search-step limit before exhausting them.
• The patent's term expired December 24, 1995. Any assertion litigation would therefore most likely date from roughly 1978–1995, and older district court records (especially pre-1990) are only patchily indexed in the free databases I could reach. So the absence of a hit is meaningful but not conclusive proof that no suit was ever filed.

Recommendation

If you need a definitive answer (e.g., for a validity/ownership opinion or a clearance matter):

1. Run a docket search directly on PACER and on commercial databases (Docket Navigator, LexisNexis Patent Litigation, Derwent LitAlert / Clarivate), which index older and settled patent suits more completely than free sources.
2. Confirm via the USPTO Patent Assignment records (the "reassignment" entries dated 1985, 1986, and 1990 for Computer Automation, Inc.) whether the patent was ever transferred to an entity that subsequently enforced it.
3. Check CAFC records under the assignee/lienholder names (e.g., M.H. Whittier Corp., Glenbrook Partners) for any appeal referencing this patent.

I'd rather flag that I could not confirm a case than report a case number I cannot substantiate.

Proceedings overview

Zero AIA trial proceedings are on file for US 4,124,889 — the structured USPTO Open Data Portal block in this prompt returns no IPR, PGR, or CBM for the patent, web search surfaced no proceeding number tied to this patent (only unrelated "889" false positives), and the absence is structural rather than accidental: the patent issued 1978-11-07 and, per its Google Patents record, reached anticipated expiration on 1995-12-24 — roughly seventeen years before the AIA created the IPR/PGR/CBM regimes on 2012-09-16. Breakdown by status is therefore 0 active / 0 claims invalidated / 0 claims sustained / 0 settled / 0 institution denials. The defensive posture this gives a defendant is unusual and favorable in one narrow way: there is no PTAB tribunal ruling to fight over, but also nothing to lean on — the reason you won't find an IPR is not that the patent is "hardened," it's that the patent is dead and unassertable. Any demand letter invoking US 4,124,889 today is citing a patent whose term ended in 1995; the correct response is a demand for proof of standing and a live infringement theory, not a validity attack.

No proceedings to enumerate

There is no case caption, panel, institution decision, Final Written Decision, settlement, or appeal to report, and I will not manufacture one. The requested per-proceeding template is empty by operation of fact, not omission.

Strategic summary

Claim status: entirely untested, and functionally irrelevant. No claim of 4,124,889 has ever been construed by the PTAB, canceled, or confirmed in an AIA trial. I do not have verified claim text for this patent in the record provided to me (the supplied full text is the specification and figure description; the claim set is not reproduced), so I will not paraphrase or guess at claim numbering. For a defendant, the practical point is not which claims survive — none were challenged — but that the patent's statutory term expired on 1995-12-24, meaning there is no ongoing direct infringement and no injunctive exposure. Past damages would be confined to acts within the six-year lookback from a hypothetical complaint (35 U.S.C. § 286), all of which necessarily predate 1995. The security-interest reassignments on the face of the record (First National Bank of Chicago, 1985-04-18; M. H. Whittier Corp. and six other assignees, 1990-01-23) are a signature of Computer Automation's financial distress in that era, not of any patent-enforcement campaign.

Estoppel landscape: § 315(e)(2) is a non-issue, because no petitioner exists. There is no IPR/PGR petitioner in privity with anyone from whom estoppel could flow, so no prior-art ground is foreclosed by statute. A defendant is free to raise any § 102/§ 103/§ 112 defense in district court — though with the term expired, prior-art invalidity is litigation theater rather than the main event. Note the limits of the tools: PGR is unavailable (the application's effective filing date of 1975-12-24 precedes the AIA's 2013-03-16 cutoff for post-grant review under 35 U.S.C. §§ 321–329); CBM is both sunset (no petitions after 2020-09-16) and inapplicable on subject matter — the patent claims a distributed input/output controller architecture, not a "financial product or service"; and IPR remains theoretically available under 35 U.S.C. § 311 because IPR is not filing-date limited, but § 315(b)'s one-year bar and the complete absence of commercial incentive make it a dead letter. The Board has instituted on expired patents where a live dispute justified it; nothing here would.

Pattern signals: none, and no defensive aggregator in the chain. There is no repeat petitioner, no PTAB appeal history, no Unified Patents or similar entity in the record, and no Federal Circuit docket number to report for this patent. My searches returned only unrelated patents that share the "889" string — the Apple/Samsung design patent D504,889 (Federal Circuit 2012 preliminary-injunction appeals), HyperPhrase's 5,903,889 (N.D. Cal. / Fed. Cir., HyperPhrase Techs. v. Google), and the LFRT process patent litigated in LNP Engineering Plastics v. Miller Waste Mills, 275 F.3d 1347 (Fed. Cir. 2001). None of these involve US 4,124,889, and I flag them precisely because a defendant's own search will surface them and produce a false impression of an active litigation history around this patent. Also note the related Computer Automation filing US 4,100,601 (priority to application 05/647,762, filed 1976-01-09, per the same record) — a different patent with its own separate (and, as far as I can confirm, equally quiet) history.

Recommended next steps

1. Treat the "no PTAB activity" finding as a signal about the patent's commercial life, not its strength. The prompt's own framing is right: well-asserted patents eventually attract IPRs — 4,124,889 has attracted none in thirteen-plus years of AIA availability (2012-09-16 forward), because it expired in 1995 and its owner of record was dismembered by secured lenders in 1990. No public record I found shows enforcement litigation asserting this patent. If a demand letter or complaint cites it, the burden is on the sender to explain what live right they hold and what post-1995 acts they accuse. I state plainly: no PTAB activity exists.

2. Do not brief invalidity as your lead argument. Challenge standing, ownership after the 1985 and 1990 assignments, and the absence of any infringing act within the § 286 damages window. An expired patent can only ground past damages for acts during its term.

3. Independently verify, since I am relying on the structured block plus search, not on a live PTAB API pull of my own. Run the patent number directly against:

• PTAB E2E / PTAB public search — https://ptacts.uspto.gov/ptabweb/ (search by patent number 4124889)
• USPTO Patent Center for the full file history, terminal disclaimer, and any certificate of reexamination or expiration — https://patentcenter.uspto.gov
• CourtListener / RECAP full-text search for "4,124,889" and for assignee "Computer Automation" — https://www.courtlistener.com/?q=%224%2C124%2C889%22

If any of those returns a proceeding number I could not surface, the analysis above changes materially and I would want the docket number before opining further. Because there is no FWD to link, there is no claim-level disposition to quote — and you should be suspicious of any secondary source that supplies one.

I'll research the assignment record and corporate history before building the chain.

Assignment & Ownership Analysis — US 4,124,889

Important sourcing caveat up front. This patent's assignment history is reachable only in part from the sources I could actually open in this session. Google Patents' "Reassignment" legal-events table (mirroring the USPTO assignment record) is the authoritative text I have, and it does not expose reel/frame numbers or the correspondent of record. I was unable to retrieve those two fields — no Assignment Center record detail, no reel/frame, no attorney name, for any link in this chain. Per the operating rules I am not inventing them. Every reel/frame and correspondent slot below is marked [NOT RETRIEVED] and should be re-pulled interactively at https://assignmentcenter.uspto.gov/ (search patent number 4124889) before this is relied on for litigation or diligence purposes.

Inventors

Notes / patterns:

• I found no evidence of either inventor departing the original assignee within 12 months of filing, or of any inventor-side assignment outside the corporate chain. That specific "pre-fire-sale inventor exodus" tell is therefore unclear — not affirmatively absent, simply not evidenced in the records I could reach.
• The patent is a member of a two-application family at Computer Automation: US 4,124,889 (filed 1975-12-24) and US 4,100,601 (priority link 1976-01-09, per the Google Patents event table). Family-member co-filing is the kind of detail that matters for the correspondent check, because the same outside counsel typically recorded both — worth pulling when you get Assignment Center access.
• Do not conflate this patent with Computer Automation's famous assertion patent. The 1973-filed "memory address allocation system" patent that IBM paid a $100,000 advance royalty on in 1987 (Electronic Business, 1988-04-01) is a different patent covering memory allocation / third-party memory lockout. US 4,124,889 claims a distributed I/O controller architecture and was not the IBM royalty vehicle.

Original assignee

Computer Automation, Inc. — named on the face of the issued patent; Google Patents' "Current Assignee" field still reads Computer Automation Inc and "Original Assignee" reads Computer Automation Inc.

• Did they ship a product embodying the claims? Yes — well corroborated. The patent describes the "distributed input/output system" (DIOS): a multiplexer plus microcoded peripheral-unit controllers physically distributed to each peripheral. Computer Automation's contemporaneous product literature markets exactly this: the Auerbach Guide to Minicomputers (1976–77 Winter) describes the Naked Milli / LSI-3/05 with a "distributed I/O subsystem option" that "supports the concept of quick and easy interfacing," running against the LSI-2/LSI-4 Naked Mini lines. The spec's own FIG. 2 embodiment maps onto that product context.
• Primary line of business: minicomputer manufacturer, OEM-channel oriented (PDC 404/808, Alpha 8/16, LSI-1/2/3/4 "Naked Mini," Naked Milli), later pivoting to automatic test equipment ("Marathon Automatic Test Systems"). Founded 1968 (Wikipedia; LA Times says 1967) by David H. Methvin.
• Current status: dissolved / defunct (1992) — no successor operating the patent. Corporate offices moved Newport Beach → Boulder (1981) → Irvine (1985) → Richardson, Texas (1990). The LA Times (1990-05-17) documented active distress: a $4M sale of the ATE business to Technology Marketing Inc. fell through in Nov 1989; the company said it would only service existing ATE customers; Q3 1990 revenue of $993,000 versus a 1984 peak of $41M; stock at $1.50 versus $17 in early 1987. Wikipedia/DBpedia record extinction year 1992.
• I did not verify a formal Chapter 7/11 filing. "Dissolved while distressed" is supported; "bankruptcy proceeding with a docketed patent sale" is not evidenced in what I retrieved.

Assignment timeline

One-line answer to the core question: no recorded transfer of title ever left Computer Automation. The USPTO/Google Patents record for this patent contains three non-issuance events, and all three are liens and a lien release, i.e., financing instruments — not conveyances of ownership.

1. 1985-04-18 — Reel [NOT RETRIEVED]

• Conveyance: SECURITY INTEREST (see record for details)
• Assignor: COMPUTER AUTOMATION, INC.
• Assignee: FIRST NATIONAL BANK OF CHICAGO, THE
• Correspondent: [NOT RETRIEVED — not exposed by the Google Patents legal-events feed; requires Assignment Center interaction]
• Context: Securitization — the company pledges its patent estate as collateral for secured financing. No title passes.

2. 1986-05-12 — Reel [NOT RETRIEVED]

• Conveyance: RELEASED BY SECURED PARTY (see record for details)
• Assignor: FIRST NATIONAL BANK OF CHICAGO, THE
• Assignee: recorded literally as "BANK AND COMPUTER AUTOMATION, INC. (COMPANY)" — flag: this assignee string appears garbled/concatenated in the source feed. Interpreted literally, as required; the evident effect is a release running back to Computer Automation, i.e., the 1985 lien was satisfied. Confirm the exact assignee string on the Assignment Center record.
• Correspondent: [NOT RETRIEVED]
• Context: Securitization unwind — lender releases its collateral interest; title was never with the bank.

3. 1990-01-23 — Reel [NOT RETRIEVED]

• Conveyance: SECURITY INTEREST (see record for details)
• Assignor: COMPUTER AUTOMATION, INC., A CORP. OF DE (note the Delaware incorporation designation — the original assignee of record on the 1978 patent was the California entity; whether this reflects a reincorporation is a question for the Assignment Center record and Delaware/Texas corporate filings)
• Assignee (as recorded, multiple parties): M. H. WHITTIER CORP. — "(see record for the remaining six (6) assignees)" — GLENBROOK PARTNERS, A NV LTD. PARTNERSHIP; J. F. SHEA CO. INC., NOMINEE 1989-37; R&W VENTURES I, A CA LTD. PARTNERSHIP; TIMKEN, WILLIAM R.; R&W VENTURES II, A CA LTD. PARTNERSHIP
• Correspondent: [NOT RETRIEVED]
• Context: Securitization — a seven-lender collateral pool (merchant-bank / venture / nominee vehicles, not patent acquirers) takes a blanket security interest in Computer Automation's IP roughly two years before the company's 1992 dissolution. Ties to the documented 1989–1990 liquidity crisis. Again: collateral, not assignment.

4. 1995-12-24 — Anticipated expiration (no assignment)

• Google Patents marks the patent "Expired - Lifetime." Twenty-year term from the 1975-12-24 filing (longer than 17-from-issue, 1995-11-07). The patent has been unenforceable for over three decades.

Also noted (not an assignment): the 1976-01-09 "Priority to US05/647,762" event → US 4,100,601, a family member. Family relationship only.

Net effect: the only conveyance of title in this patent's history is the original assignment to Computer Automation, Inc. at filing. There is no post-issuance assignment, no transfer to any IP-holding or licensing entity, and no chain to a defensive aggregator. Reel/frame and correspondent data for the three lien records must still be pulled to complete the record.

Timeline diagram

timeline
    title Ownership of US 4124889
    1975 : Filed by Computer Automation
    1978 : Patent issued
    1985 : Security lien to First National Bank
    1986 : Lien released
    1990 : Security lien to Whittier lender group
    1995 : Patent expired

(Title never changes hands across this timeline — the 1985/1990 nodes are collateral pledges and the 1986 node is their release.)

NPE / troll-pattern signals

1. Shell-entity transfer — NOT PRESENT.
No record moves title from Computer Automation to any entity with an "IP / Patents / Licensing / Holdings / Ventures" suffix, or to any single-purpose LLC. The two acquisition-side conveyances in the chain are typed SECURITY INTEREST (1985-04-18; 1990-01-23) and the third is typed RELEASED BY SECURED PARTY (1986-05-12). Google Patents' "Current Assignee" still reads Computer Automation Inc. Venture-sounding names (R&W Ventures I/II, Glenbrook Partners, J.F. Shea Co. Inc. Nominee 1989-37) appear here as secured creditors, and a nominee vehicle keyed to a financing ("Nominee 1989-37") is a lending-structure tell, not a patent-holding tell. Naming alone is not a finding — the conveyance type on the record is what defeats this signal here.

2. Known asserter in the chain — NOT PRESENT.
None of the recorded parties — First National Bank of Chicago; M. H. Whittier Corp.; Glenbrook Partners; J. F. Shea Co. Inc. Nominee 1989-37; R&W Ventures I or II; William R. Timken — appears on the NPE rosters supplied (Acacia, Marathon, IV, IPNav, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, Spangenberg entities). Caveat: I could not query the RPX and Unified Patents asserter directories in this session, so this is a match-against-provided-list result, not a full directory sweep.

3. Repeat correspondent across the chain — UNCLEAR / NOT DETERMINABLE.
No correspondent of record was exposed by the source I could reach, for any of the three recordings. This is the single most important gap in this analysis: when you pull the Assignment Center records, capture the correspondent on all three reel/frame entries and on family member US 4,100,601. If the same attorney/firm recorded the 1985 lien, the 1986 release, and the 1990 lender-pool lien, that is a normal secured-finance practice pattern (one firm handling a company's credit facilities) rather than an NPE tell — but it cannot be called either way without the names.

4. Cascading transfers — NOT PRESENT.
Three events across five years (1985 → 1986 → 1990), with the first two forming a matched lien/lien-release pair (~13 months apart). There are no consecutive transfers through chained LLCs, no sub-24-month relay, and no shared-principal assignee sequence.

5. Pre-litigation transfer — NOT PRESENT / NOT APPLICABLE.
No infringement suit naming this patent surfaced, and the patent expired 1995-12-24. The last recorded event (1990-01-23) precedes expiry by ~5.9 years and does not enable assertion. There is no suit to be "pre-litigation" to.

6. Bankruptcy fire-sale — UNCLEAR.
Supporting facts: severe financial distress documented in 1990 (LA Times 1990-05-17: collapsed ATE divestiture, $993K quarterly revenue, $1.50 stock) and corporate extinction in 1992 (Wikipedia/DBpedia). What is missing is any evidence of a Chapter 7/11 filing or of patents being sold through a bankruptcy estate — I found no docket, no 363 sale, no notice. Critically, the 1990 instrument is typed SECURITY INTEREST, i.e., pre-petition collateral, not a sale. I will not upgrade this to "present" on company failure alone.

7. Privateering — NOT PRESENT.
No operating-company-to-NPE transfer, and no SEC-filing or press coverage of Computer Automation sponsoring an assertion campaign through a third party. The one assertion-adjacent episode I located — the 1987 IBM $100,000 advance royalty on Computer Automation's memory address allocation patent, with the company's president openly discussing royalties from PS/2 clone makers (Electronic Business, 1988-04-01) — is direct operating-company licensing of a different patent, the opposite of privateering.

8. Defensive aggregator — NOT PRESENT.
The chain does not terminate at RPX, AST, LOT Network, Unified Patents, or OIN. It terminates at the original operating assignee, by expiration.

Additional reality check: because the term ran out on 1995-12-24, this asset has had zero assertion value for ~30 years. Any "NPE" framing is foreclosed by expiration regardless of the corporate history.

Verdict

Insufficient data — as to NPE characterization, and specifically: no NPE chain exists.

The complete recorded title history is the original assignment to Computer Automation, Inc. at filing plus three lien-type events — a SECURITY INTEREST recorded 1985-04-18, its RELEASE recorded 1986-05-12, and a seven-lender SECURITY INTEREST recorded 1990-01-23 (M. H. Whittier Corp. et al.). None of these conveys ownership; Google Patents' "Current Assignee" is unchanged, and the patent expired 1995-12-24. The failure to recover reel/frame numbers and correspondents for those three recordings is the one factual gap, and it does not change the verdict, because a correspondent pattern is only probative when there is a title transfer to chart — here there is none. For verification and to close the gap: https://assignmentcenter.uspto.gov/ (search 4124889), cross-checked at https://assignment.uspto.gov/patent/index.html, plus EDGAR full-text search of Computer Automation's 1989–1990 10-K/8-K for the Whittier/Glenbrook/Shea/R&W financing description.

Confidence and limitations

• High confidence: inventor names; assignee of record; filing/issue/expiry dates; the three conveyance types and their parties (verbatim from the Google Patents legal-events feed at https://patents.google.com/patent/US4124889/en); Computer Automation's 1992 extinction and its 1970s–80s product line.
• Low confidence / unresolved: all reel/frame numbers; all correspondents; whether the 1986 assignee string "BANK AND COMPUTER AUTOMATION, INC. (COMPANY)" is an artifact or the recorded name; whether the 1990 assignor's "A CORP. OF DE" reflects a reincorporation; whether any 1989–1992 bankruptcy proceeding existed; SEC filing specifics; RPX/Unified directory matches.

I'll research US patent 4124889 and its prior art citations. Let me search.

Let me get the complete citation list from the patent's front page.

I need the front-page "References Cited" data for 4124889 specifically. Let me search more precisely.

I hit my tool-call limit before I could fully verify every entry against the USPTO front page, so I'm going to give you what I was able to retrieve, clearly separated by confidence level. I will not invent entries I could not see.

1. Patent identification (confirmed)

I am treating 4124889 literally and have excluded hits for similar-sounding numbers (e.g., US4124888, US4313160) from the "identification" line, though they appear below as related/family art.

2. Important caveat on completeness

I could not retrieve a fully verified, authoritative examiner "References Cited" block from the USPTO front page of 4,124,889 within the steps available. The patent's claim text was also truncated in the source material (the fetched description cuts off at the clock-generator discussion and does not include the numbered claims). Because I cannot see the express claim language, any § 102 mapping below must be treated as provisional. I have flagged each entry accordingly and will state explicitly where I am inferring.

Where I say "confirmed," it means I saw the identifier in a retrieved document; where I say "reported," it means a secondary source listed it and I could not cross-check the primary front page.

3. Prior art cited by / associated with 4,124,889

The Google Patents "Citations" table returned for this family showed a list of U.S. patent documents, three of which I could read verbatim. These are the classic "autonomous I/O control" references:

3.1 US 3,274,561 — confirmed

• Citation: US 3,274,561 A, "Data processor input/output control system."
• Assignee/inventor: Burroughs Corp.
• Filing date: 1962-11-30
• Publication date: 1966-09-20
• Brief description: An early I/O control system in which a separate controller mediates transfer between the processor and a peripheral, relieving the CPU of step-by-step transfer control.
• § 102 potential: This is the closest functional ancestor to the independent concept of "a controller that manages I/O." If any claim of 4,124,889 were read broadly as "a control unit interposed between a CPU and a peripheral," this reference is the strongest § 102 candidate. However, it predates microprocessors, microcoded ROM controllers, and the distributed/multiplexer architecture, so it almost certainly cannot anticipate any independent claim that recites the multiplexer + plurality of remotely located microcoded controllers + common cable structure. Realistic posture: § 103 (obviousness), not § 102.

3.2 US 3,283,308 — confirmed

• Citation: US 3,283,308 A, "Data processing system with autonomous input-output control."
• Assignee/inventor: Beckman Instruments, Inc.
• Filing date: 1963-06-10
• Publication date: 1966-11-01
• Brief description: A data-processing system in which the I/O control operates autonomously rather than under continuous CPU supervision.
• § 102 potential: Directly on point for the "independently operating controller" concept. This is arguably the most legally dangerous reference for the broadest claim(s) because the title itself recites "autonomous input-output control" — the very advantage 4,124,889 touts in its "Background/Objects" (reducing CPU overhead, not requiring the CPU to monitor each transfer). If a claim of 4,124,889 is drafted as an apparatus for autonomous I/O control without the specific microcode/multiplexer/distribution limitations, US 3,283,308 is the strongest § 102 candidate. For claims reciting the distributed-positioning and microprogrammed-ROM limitations, it is again more likely § 103.

3.3 US 3,407,387 — confirmed (dates partial)

• Citation: US 3,407,387 (title not returned in the retrieved snippet).
• Filing date: 1965-03-01
• Publication date: 1968-10-22
• Brief description: A 1960s data-processing/I/O control patent in the same family of foundational interrupt/channel art.
• § 102 potential: Cannot be assessed for element-by-element anticipation because I do not have its disclosure text or its title. It sits in the same era and technical space. Treat as secondary art / § 103 candidate pending verification.

Items 4–8 of the reproduced "Citations" list were not returned in readable form in my searches. I therefore cannot name them without fabricating. If you have the front page PDF, the complete examiner list is what should be mapped; based on the pattern, expect additional mid-1960s to early-1970s I/O channel and interrupt-scan references.

4. References I saw but that are NOT prior art to 4,124,889

The task is specifically about citations for 4124889. To avoid an easy and common error, note that the following appeared in retrieved "Cited By" (forward-citation) tables — i.e., they post-date 4,124,889 and cite it, so they are not anticipatory art:

Note on the three filed-but-later-published U.S. cases (3,949,371; 3,972,023; 4,047,158): these were filed before 1975-12-24 and published after, so under pre-AIA § 102(e) they are potentially available as prior art only if their disclosures actually support the elements at issue. They appear in the retrieved citation table in a way that is ambiguous as to whether they are "citations of" or "cited by" 4,124,889; please verify direction against the front page before relying on them.

5. Related family documents (context, not prior art)

These are the same-family continuations/CIPs and are the reason identical specification text appears across patents — do not mistake them for prior art:

• US 4,124,888 — "Peripheral-unit controller apparatus," Kaufman/Washburn, filed 1975-12-24 (same day; sibling).
• US 4,100,601 — priority to application 05/647,762 (1976-01-09).
• US 4,313,160 — "Distributed input/output controller system," Kaufman/Washburn/Stapinski, filed 1979-05-01 (continuation; adds direct-memory-access multiplexer and ALU). Its own cited references (US 3,588,831; 3,702,462; 3,728,693; 4,003,033; 4,016,548; 4,017,093; 4,017,839; 4,020,472; 4,025,906; 4,040,028; 4,103,328; 4,104,718; 4,110,822; plus NPL: Westgate, The Design & Application of Microprocessor Systems, pp. 52–55, 1977; Electronics, Apr. 1976, p. 81) belong to the 4,313,160 prosecution, not to the 4,124,889 prosecution — another easy trap.
• US 4,245,300 expressly cross-references application Ser. No. 35,263 (the 4,313,160 ancestor) as describing the remote I/O controllers.

6. Overall § 102 assessment (provisional)

On the material I could actually see:

1. No confirmed reference anticipates all elements of 4,124,889's likely independent claims. The distinguishing combination — a multiplexer at the host feeding a plurality of physically distributed, microcoded (ROM-based) peripheral-unit controllers, each co-located with its peripheral and joined by a short (≤ ~2 ft) interface cable with identical ribbon cabling carrying both signal and power — was not shown in the 1960s references (US 3,274,561, US 3,283,308, US 3,407,387).
2. Strongest § 102 exposure: the broadest claims whose scope is essentially "autonomous I/O control" (US 3,283,308) or "controller interposed between processor and peripheral" (US 3,274,561).
3. Strongest § 103 exposure: the combination of the above 1960s autonomous-I/O art with the mid-1970s bus-structure/microprocessor art (DE 2,539,929; US 3,972,023; US 4,047,158) and the NPL sources on microprocessor system design.

7. What I could not confirm (stated explicitly rather than guessed)

• The complete, numbered claim set of 4,124,889, so claim-by-claim § 102 mapping is provisional.
• Citations 4–8 of the front page (I only read three verbatim).
• The direction of several entries (whether US 3,949,371 / 3,972,023 / 4,047,158 / DE 2,539,929 are "cited by" 4,124,889 or "citing" it).

To finalize this properly, pull the 4,124,889 front page from USPTO Patent Center (or the Google Patents "Citations" panel for US4124889A) and its complete claim listing. With the exact "U.S. Patent Documents" block and the claims text, I can produce a true element-by-element § 102/§ 103 chart. I would rather flag that gap than present fabricated citations or a fabricated claim map.

I'll start by trying to retrieve the actual prior-art citations for this patent, since the page text I was given lists only "Prior art keywords" (unit, peripheral, data, signal, signals) and does not include the citation tables.

Good leads. Let me try to pull the actual citation list for US4124889 and the claim text, which were not included in the page text I was given.

The citation list still isn't surfacing directly. Let me try targeted routes to the patent's front-page references and claims.

Bottom line up front

I could not perform a defensible, claim‑by‑claim § 103 analysis of US 4,124,889, for two hard evidentiary reasons that I need to state before anything else:

1. The "Prior Art section" you asked me to use is not present in the material I was given. The supplied Google Patents text (https://patents.google.com/patent/US4124889/en) contains a classification block, a narrative prior‑art discussion inside the specification, and a "Prior art keywords" field (unit, peripheral, data, signal, signals). It contains no citation table — no "Patent Citations," no "References Cited," no examiner citations. Search results indicate US 4,124,889 has a "Patent Citations (25)" table, but I was unable to retrieve its contents.
2. The supplied text does not contain the claims. The fetch ends mid‑description ("the clock generator GEN …"). I have no claim language for this patent, and I will not invent it. Every identifier below is reproduced literally as retrieved, including apparent OCR noise.

So what follows is a framework‑level § 103 analysis keyed to the features the specification itself asserts as the invention, not a limitation‑by‑limitation claim chart. I flag confidence at each step.

1. The patent's own admissions of prior art (usable as prior art)

The specification contains express admissions that are themselves § 103 evidence regardless of the citation table:

• "Prior art device‑controllers are generally sources of inefficiency which substantially raises overhead of computer operations … results from a lack of independent control capability in the device controller."
• "the prior central processor unit … must be actively involved in every step of a process which involves the input/output device."
• "One way of reducing the complexity and cost … is to combine all the common control functions in one controller and then share the controller on a time‑multiplexed basis … Such a combined controller is normally referred to as a multiplexer," with "some additional device‑control functions … allocated to dedicated input/output adapter units."
• "multiplexer‑adapter unit combinations of the prior art are extremely complex and costly."

This is significant under Graham v. John Deere, 383 U.S. 1 (1966): the inventors themselves frame the invention as an improvement within the known multiplexer‑plus‑adapter architecture. That reduces the "differences between the prior art and the claims" to the specific placement and microcoding choices, not to the architectural concept.

2. Candidate prior art I could actually identify — with provenance caveats

The only enumerated reference list I retrieved is the front page [56] field of US 4,313,160, a later‑filed continuation (filed May 1, 1979) by the same inventive entity. Source: https://patentimages.storage.googleapis.com/44/71/7a/faf0ebbda4abf4/US4313160.pdf

Three cautions you must carry forward:

• This is US 4,313,160's list, not US 4,124,889's. I have no evidence the two lists are identical, and I will not assume they are.
• The two NPL items are dated 1976–1977 — after US 4,124,889's 1975‑12‑24 filing date. They therefore cannot be § 102(a) or § 102(b) prior art against it on their face. At most they bear on the level of ordinary skill, and even that is time‑sensitive. Their presence on the '160 list is itself evidence that the two lists differ.
• Seven of the patent references issued in 1977–1978. Their issue dates fall after the 1975‑12‑24 critical date, so they would have to qualify as § 102(e) art (i.e., their own filing dates must precede) to be available. I could not verify their filing dates. Until that is checked, treat them as candidate art only.

3. The claim‑mapping problem

A § 103 conclusion requires: (a) the scope and content of the prior art; (b) the differences between the prior art and the claims; (c) the level of ordinary skill; and (d) secondary considerations. I lack (b) entirely. The best I can do is map the disclosed inventive features the specification presents as the point of novelty, from its own "objects" section:

• F1 — Multiplexer (on one PCB, up to 16 plugs / eight IOB cables) interfacing the CPU's control, address and data buses, with a plurality of peripheral‑unit controllers (PUCs) over "identical ribbon cable that is employed to carry both signals and power."
• F2 — Each PUC located "at or near" its peripheral device, with a device cable of "two feet or less," thereby obviating "special termination requirements."
• F3 — A "substantially identical microengine unit" (MEU) in every controller, "currently of five integrated circuit chips," built from commercially available TTL parts (TI 74188A ROM, 74161 counter, 74151A selector, 74157 mux, 7486 XOR).
• F4 — The controller "manages a sequence of device operations" so the CPU "need not monitor the transfer of each term"; direct memory↔peripheral transfer using buffer pointers and transfer counts = "automatic input/output operation."
• F5 — Two sets of microcode in the same ROM pair, selected by jumper/switch/flip‑flop (ROM E1/E2 pin strapping), letting one controller serve two device types.
• F6 — Controller‑generated data‑service and end‑of‑block interrupts, prioritized (data‑service > EOB) in the MUX, vectored to "known preselected memory cells," with a PRIN/PROT priority chain across multiplexers.
• F7 — A CMD signal of nominal 250 ns vs. double‑duration 500 ns used to signal that the transfer count reached zero.
• F8 — Tri‑state transceivers (DM 8835) with a common transmitter‑disable and receiver‑disable line, so "only one transmitter per data signal is employed" yet data reaches many controllers.
• F9 — Priority reordered by physically re‑plugging the IOB connectors (FIG. 2).
• F10 — Serial PUC variant with a UART, a per‑controller jumper‑selected baud clock on the MUX, RS‑232 level conversion, and a 4‑bit mode register.

4. Combinations that would support obviousness, and the motivation for each

(Confidence noted; all require prior art verification for the specific references.)

Combination A — Known multiplexer/channel architecture + known microprocessor‑based peripheral controller.
Take a time‑multiplexed I/O channel of the type the patent admits was known ("multiplexer‑adapter combinations") and combine it with the then‑notorious teaching, expressly relied on by examiners in this era, that a general‑purpose microprocessor or microprogrammed sequencer can replace hard‑wired adapter logic. Motivation: the specification's own statement that prior adapters were "complex and costly" and that "inefficiency results from a lack of independent control capability." KSR, 550 U.S. 398, 417 (2007) ("if a technique has been used to improve one device, and a person of ordinary skill … would recognize that it would improve similar devices in the same way, using the technique is obvious"). The Westgate text and the April 1976 Electronics special issue (as level‑of‑skill evidence, not art) confirm microprogrammed I/O controllers were routine. Maps to F1, F3, F4.

Combination B — Known remote/multi‑drop I/O distribution + known controller‑at‑the‑device placement.
Remote‑terminal and data‑communications practice already placed line adapters/controllers at the terminal end of a serial link, precisely because long parallel cables are noisy. Motivation: predictable cost/engineering result — shorter device cables, common cabling, no per‑device termination. This is a classic KSR "predictable variation … of a known technique." Maps to F1, F2, F10. (F2's "no special termination" advantage is the flag most vulnerable to characterization as an expected result, since it is stated in the specification as a consequence of a 2‑foot cable rather than as structure.)

Combination C — Known interrupt priority chaining/vectoring + microprogrammed controller.
Daisy‑chained PRIN/PROT priority chains and vectored interrupts were standard in minicomputer I/O of the era (the patent's own Table I describes the scheme in generic terms, and the priority chain is described as also running "through controllers of peripheral devices that are connected directly to the computer unit"). Motivation: KSR — "the combination of familiar elements according to known methods … when it does no more than yield predictable results"; the two‑tier priority (device order, then data‑service over EOB) is simple rank ordering. Maps to F6.

Combination D — Off‑the‑shelf ROM pin‑strapping / memory banking + known dual‑purpose adapter.
Using a spare address line on a ROM to select one of two 16‑word pages is elementary addressing. Motivation: meet the express prior‑art requirement of "controller inflexibility" at no added part cost. Maps to F5.

Combination E — Pulse‑width discrimination + known transfer‑count logic.
Pre‑existing CPU designs distinguished control operations by strobe width/length. Combined with the admitted prior practice of the CPU maintaining a transfer count (the specification itself says "the central processor unit CPU of the computer unit CU will keep an accounting … by checking the transfer count"), extending a strobe from 250 ns to 500 ns is a design choice between two known signalling conventions. Maps to F7.

Combination F — Known tri‑state bus practice.
Tri‑state transceivers with common enable lines were a stocked commodity in 1975 (the patent's own DM 8835 is a commercial part cited as such — The TTL Data Book for Design Engineers, 1st ed. 1973). Motivation: bus contention avoidance. This is close to per‑se; expect no patentable weight. Maps to F8.

Combination G — Serial variant: known UART + known RS‑232 + jumper‑selected clock.
The specification expressly describes the UART as performing a conventional parallel‑to‑serial 8‑to‑11‑bit conversion and the level conversion as conforming to "standards established by Electronic Industries Association" (RS‑232). Jumper‑selectable clock taps on a common board are routine. Maps to F10.

5. The most dangerous references are not third‑party art

Note the family relationships the search results confirm:

• US 4,124,888 — "Peripheral‑Unit Controller Apparatus," filed the same day (application 5/644,341; US 4,124,889 is 5/644,412). Same inventive entity.
• US 4,100,601 — "Multiplexer for a Distributed Input/Output Controller," filed 1976‑01‑09 (Ser. No. 647,762).
• US 4,245,300 and US 4,313,160, both later continuations by overlapping inventors, and both of which describe the system as "Applicants' Prior Applications."

Two consequences:

• Because US 4,124,888 is same‑day and same‑entity, it is neither "by another" nor earlier‑filed, so it is not § 102(e)/§ 103 prior art against US 4,124,889. The real risk there is obviousness‑type double patenting, which is an equitable doctrine resolved by terminal disclaimer, not § 103.
• US 4,313,160's disclosure that the DMA system "extends" the '889 system, and that its multiplexer "is fully compatible with controllers that can also be used with an indirect‑memory‑access multiplexer," is excellent evidence that the incremental advances across this family were regarded by the inventors themselves as design continuations, i.e., predictable improvements — a point an obviousness challenger would exploit.

6. Secondary considerations

The patent claims as advantages: lower cost, avoidance of special cable terminations, controller flexibility via dual microcode, and removal of the CPU from per‑term monitoring. These are stated as results, not as unexpected properties. Under KSR, "the mere existence of … advantages … cannot protect" a predictable combination, and where the specification simply asserts cost reduction from using "inexpensive, commercially available, integrated‑circuit devices," that is close to the "use of a known component for its intended purpose." I found no evidence in the record I reviewed of unexpected results, long‑felt need, licensing, or commercial success. Note also that the patent expired on 1995‑12‑24 (anticipated expiration per the Google Patents record), so any § 103 opinion now serves defensive, historical, or valuation purposes rather than infringement defence.

7. What I would need to make this rigorous

1. The actual claim set of US 4,124,889 (all independent claims plus dependents). Without it, no limitation‑by‑limitation chart is possible, and my feature mapping (F1–F10) is merely an inference from the specification's objects.
2. The actual "Patent Citations (25)" table from US 4,124,889's front page, ideally from the USPTO PatentCenter/Global Dossier or the patentimages PDF — not US 4,313,160's.
3. Filing dates (and any foreign priority dates) for US 4,003,033; 4,016,548; 4,017,093; 4,017,839; 4,020,472; 4,025,906; 4,040,028; 4,103,328; 4,104,718; 4,110,822, to test § 102(e) availability against the 1975‑12‑24 critical date.
4. Corrected bibliographic data for the OCR‑mangled entries, especially "3,588,831 (Figure of at.)" and the two 1977 references attributed to "Calle."

Confidence summary: High confidence that the combination claims of this patent (multiplexer + microprogrammed controllers located at the peripherals + ROM‑selected dual microcode + two‑tier interrupt priority) are vulnerable to a § 103 challenge built on the patent's own admissions plus routine microprogrammed I/O controller art. Low confidence in any specific reference‑number‑to‑limitation mapping, because I could not verify the citation list or read the claims. I would not sign a formal invalidity opinion on the present record.