Patent 12271636

Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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Here is an analysis of the most relevant prior art for US Patent 12271636, based on the provided patent text and a search of its citations on Google Patents.

US Patent 12271636, titled "Analytics, algorithm architecture, and data processing system and method," has a priority date of 2019-02-06. The patent describes a distributed hardware architecture with compute nodes, programmable logic components (e.g., FPGAs), and a pipeline for executing algorithms, often in cooperation with Flash memory.

For the purpose of identifying prior art that potentially anticipates claims under 35 U.S.C. § 102, independent prior art references (i.e., those not sharing a common inventive entity and priority date) are most critical. Several of the patents cited by the examiner and applicant are continuation applications or otherwise related family members sharing the same inventors and priority claims as US12271636. These family members generally serve as disclosures of related subject matter within the patent family, rather than independent anticipatory prior art under 35 U.S.C. § 102.

Most Relevant Independent Prior Art Citations:

1. US8793467B2

  • Full Citation: US8793467B2 to Brogan et al., titled "System and method for flash storage as an extension to a main memory of a host computer," published July 29, 2014.

  • Publication/Filing Date: Publication: 2014-07-29; Filing: 2013-09-03 (claims priority to earlier applications, but 2013-09-03 is the filing date for this specific patent).

  • Brief Description: This patent discloses a system and method where flash memory acts as an extension to a host computer's main memory. A flash memory controller manages read/write access directly through a PCIe interface, bypassing the host operating system. The controller translates logical addresses to physical addresses and handles operations like garbage collection, wear leveling, and ECC.

  • Potential Anticipation (35 U.S.C. § 102):

    • Claims 4, 8, 12 (Flash memory as a data store): US8793467B2 clearly discloses the use of Flash memory as a data store in a computing system for high-performance data access.
    • General concepts of high-performance memory access: The system's direct access via PCIe and bypassing the OS for improved performance aligns with the broader objective of high throughput in US12271636.

    However, US8793467B2 does not appear to anticipate the core inventive concepts of US12271636 related to a distributed processing architecture featuring a pipeline of serially coupled compute nodes for algorithm execution, each node comprising a programmable logic component (e.g., FPGA) configured to execute algorithms, or a distinct management node to coordinate and terminate algorithm execution in such a pipeline. Specifically, it does not anticipate:

    • The distributed pipeline architecture for algorithm execution (Claims 1, 6, 10).
    • The use of programmable logic components within each node for executing algorithms (Claims 1, 5, 6, 7, 9, 10, 11, 13).
    • The concept of additional compute nodes operating without storing intermediate results in their local memory (Claims 2, 10).

2. US9804860B2

  • Full Citation: US9804860B2 to Hemmady et al., titled "Data storage system for providing a non-volatile memory as a byte-addressable memory," published October 31, 2017.

  • Publication/Filing Date: Publication: 2017-10-31; Filing: 2015-02-18.

  • Brief Description: This patent describes a non-volatile memory system, including a memory device (e.g., Flash), a memory controller, and a host interface. The system allows the host to interact with the non-volatile memory as if it were a byte-addressable memory, with the memory controller configured to process commands and memory operations in this manner.

  • Potential Anticipation (35 U.S.C. § 102):

    • Claims 4, 8, 12 (Flash memory as a data store): Similar to US8793467B2, this patent explicitly teaches the use of non-volatile memory, such as Flash, with a memory controller for data storage.
    • Memory controller functionality: It describes a memory controller managing interactions with the non-volatile memory.

    However, US9804860B2 does not disclose the distributed pipeline architecture or the algorithm execution aspects central to US12271636. It does not anticipate:

    • A pipeline of serially coupled compute nodes for executing an algorithm (Claims 1, 6, 10).
    • Programmable logic components within nodes dedicated to algorithm execution (Claims 1, 5, 6, 7, 9, 10, 11, 13).
    • The coordination by a management node in a distributed pipeline.
    • The specific data flow optimization where intermediate results are not stored in the local memory of downstream nodes.

Related Family Members (Not Anticipatory Prior Art under 35 U.S.C. § 102 due to common priority):

The following citations share common inventorship and Fermat International Inc. as assignee, and have filing dates that are either the same as or later than the priority date of US12271636 (2019-02-06). They are likely continuation applications, divisionals, or related patents within the same family, covering related aspects of the same invention. As such, they are typically not considered anticipatory prior art under 35 U.S.C. § 102 for the distinct claims of US12271636.

  • US10635489B1

    • Full Citation: US10635489B1 to Bismuth et al., titled "Distributed programmable data processing system and method for flash storage," published April 28, 2020.
    • Publication/Filing Date: Publication: 2020-04-28; Filing: 2019-02-06.
    • Brief Description: This patent describes a distributed programmable data processing system designed for flash storage, covering aspects relevant to the overall system architecture.

  • US20200257564A1

    • Full Citation: US20200257564A1 to Bismuth et al., titled "DATA PROCESSING AND ANALYTICS SYSTEM AND METHOD," published August 13, 2020.
    • Publication/Filing Date: Publication: 2020-08-13; Filing: 2020-05-18.
    • Brief Description: This published application describes a data processing and analytics system and method, closely related to the subject matter of US12271636.

  • US20200257565A1

    • Full Citation: US20200257565A1 to Bismuth et al., titled "Data processing and analytics system and method," published August 13, 2020.
    • Publication/Filing Date: Publication: 2020-08-13; Filing: 2020-05-18.
    • Brief Description: Another published application by the same inventors and assignee, with a similar title and content.

  • US20220261172A1

    • Full Citation: US20220261172A1 to Bismuth et al., titled "Analytics, algorithm architecture, and data processing system and method," published August 18, 2022.
    • Publication/Filing Date: Publication: 2022-08-18; Filing: 2022-05-16.
    • Brief Description: This published application shares the identical title with US12271636, strongly indicating a direct family relationship (e.g., a direct parent application).

  • US20220261173A1

    • Full Citation: US20220261173A1 to Bismuth et al., titled "Analytics, algorithm architecture, and data processing system and method," published August 18, 2022.
    • Publication/Filing Date: Publication: 2022-08-18; Filing: 2022-05-16.
    • Brief Description: Another published application identical in title and by the same inventors, suggesting a very close family relationship.

Generated 5/26/2026, 12:46:55 AM