Invalidity dossier
US 12125550
Memory device, memory system including the memory device, and test operation of the memory device
Current assignee: SK Hynix Inc
Added 9/23/2026, 8:32:36 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 12125550 B2
Title: Memory device, memory system including the memory device, and test operation of the memory device
Assignee: SK Hynix Inc. (original assignee; listed current assignee)
Key Dates (per the supplied excerpt):
- Prior art date / priority date (assumed): 2021-04-20
- Filing date: 2021-10-15
- Publication of US20220336040A1: 2022-10-20
- Grant/publication of US12125550B2: 2024-10-22
- Status: Active; adjusted expiration 2042-10-06
- Application number: US17/502,561
Purpose:
The patent addresses testing a memory device for defects. More specifically, it relates to a memory device configured to test a defect of a memory device included in a memory system, the memory system including the memory device, and a test operation of the memory device.
Plain-Language Scope:
The memory device includes a memory block connected to word lines and select lines, a bit line connected to the memory block, a voltage generator that generates a test voltage applied to a selected line among the word lines and select lines, a page buffer that senses a bit line voltage to store and output test data, and a control logic circuit that determines whether a "first defect" exists in the memory block according to the test data. The page buffer includes a sensing latch that stores test data determined by a sensing node voltage during the test operation, a sensing discharge circuit that discharges the sensing node, and a bit line select circuit that blocks a connection between the sensing node and the bit line when determining test data. Test data is maintained as reset data in the sensing latch at test start when no defect exists, and changes when a defect exists. The memory system includes a controller that transmits a test command and determines whether a defect exists based on test data output from the memory device; a defect is determined when test data differs from initial data. A corresponding test method is also described.
Source: https://patents.google.com/patent/US12125550/en
What the excerpt does not establish: It does not establish litigation, ownership transfers, validity, or prior art beyond the listed prior-art keywords. The excerpt is partial (description omitted), so it does not fully establish the complete specification, all claims and their exact scope, figure contents, or any legal conclusions about the listed status and expiration dates.
Generated 10/1/2026, 9:41:20 PM
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Litigation summary
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Proceedings on file (0)
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PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.