US 11709772

US Patent 11709772: Storage System with Multiplane Segments and Cooperative Flash Management

Title: Storage system with multiplane segments and cooperative flash management

Assignee: Radian Memory Systems LLC

Inventors: Andrey V. Kuzmin, James G. Wayda

Filing Date: 2022-07-29

Issue Date: 2023-07-25

Abstract:
A storage system is described that features a memory controller configured to provide information about memory geometry, including multi-plane capabilities, to a host. This enables the host to manage the physical assignment of memory space for data writes in a way that optimizes multi-plane access. The system supports multi-plane read, write, and other memory operations initiated by the host through a command structure. Additionally, the memory controller can cooperate with the host in performing memory management tasks such as wear leveling, garbage collection, defect management, and data integrity management, further reducing latency and improving overall system efficiency.

Plain-Language Overview of Independent Claims:

Independent Claim 1:
This claim describes a storage system that includes a host and a memory controller managing a multi-plane memory device. The core idea is that the memory controller shares information about the memory's layout and multi-plane capabilities with the host. This allows the host to decide where to store data (physical address assignment) in a way that lets it perform operations across multiple planes of memory simultaneously, such as reading or writing, more efficiently. The host can issue a single command or a series of connected commands to carry out these multi-plane operations, reducing the need for the memory controller to do complex address translations, which speeds things up.

Independent Claim 8:
This claim details a method for operating a storage system with a host and a multi-plane memory controller. The method involves the memory controller telling the host about the memory's organization, including its multi-plane features. The host then uses this information to choose specific physical locations in the memory to store data, making sure that related data is placed in a way that allows for efficient access across multiple planes. The host can then send commands to the memory controller to perform actions like writing or reading data across these multiple planes based on the physical addresses it assigned.

Independent Claim 15:
This claim outlines a memory controller for a multi-plane memory device designed to work with a host. The memory controller has internal storage for keeping track of the memory's physical layout and usage details for each section of the memory. It also includes special processing parts that can communicate this memory information to the host. Crucially, the memory controller can perform certain memory management tasks (like relocating data or handling bad memory blocks) in a way that doesn't require sending the data back and forth to the host, freeing up the host to focus on other operations and improving overall system speed.

As a patent attorney, I have investigated litigation involving US patent 11709772.

Here is the known litigation:

United States District Court for the Eastern District of Texas

• Case Number: 2:24-cv-01073
• Plaintiff(s): Radian Memory Systems LLC
• Defendant(s): Not specified in the provided search results for this case.
• Filing Date: Not specified in the provided search results for this case.
• Outcome/Current Status: Active litigation.

Patent Trial and Appeal Board (PTAB)

• Case Number: IPR2025-01321
• Plaintiff(s): Petitioner is not specified in the provided search results, but it is a PTAB case.
• Defendant(s): Not specified in the provided search results for this case.
• Filing Date: Not specified in the provided search results for this case.
• Outcome/Current Status: Settlement

Proceedings overview

A single AIA trial proceeding, IPR2025-01321, was filed against US patent 11709772 and subsequently terminated due to settlement. This means no claims of the patent were invalidated or sustained by the PTAB, and therefore the patent's validity remains untested in an AIA trial. This gives a defendant facing assertion of this patent a neutral defensive posture regarding PTAB-adjudicated claim validity.

IPR2025-01321 — [[[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) et al.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.%20et%20al.) v. Radian Memory Systems LLC

• Type: Inter Partes Review
• Filed: 2025-07-17
• Status: Terminated-Settled. This indicates that the parties involved reached a confidential agreement, leading to the conclusion of the proceeding without a final judgment on the patentability of the challenged claims.
• Judge panel: Information regarding the specific judge panel assigned to this proceeding is not publicly available.
• Petition grounds: Details concerning the specific claims challenged, the prior art asserted, and the statutory basis (§ 102 / § 103 / § 112) of the petition are not publicly available, as the proceeding terminated before an institution decision or final written decision was issued.
• Institution decision: The outcome of the institution decision (instituted, denied, or partially instituted) and any associated reasoning are not publicly available. The termination by settlement likely occurred before or shortly after the PTAB's deadline for issuing an institution decision.
• Final Written Decision: No Final Written Decision was issued for this proceeding, as it was terminated due to settlement.
• Settlement / termination: The proceeding was terminated as settled on 2026-01-09. The specific terms and conditions of the settlement agreement are confidential.
• Appeal: No appeal was filed with the Federal Circuit, as there was no Final Written Decision from the PTAB to appeal.
• Defensive value: Since this IPR was terminated by settlement without a final PTAB decision on the merits, no claims of US11709772 were invalidated. This means that for a defendant currently facing assertion of this patent, the claims maintain their original scope and validity as issued by the USPTO. An IPR-based defense is still a viable strategy, as the claims have not been hardened by surviving a PTAB trial.

Strategic summary

US patent 11709772 has been involved in one Inter Partes Review, IPR2025-01321, which was filed by Samsung Electronics Co., Ltd. et al. against Radian Memory Systems LLC. This proceeding concluded with a "Terminated-Settled" status on 2026-01-09. As a result, no claims of US11709772 have been formally canceled or sustained by the PTAB. All claims of the patent remain as originally issued, and their patentability has not been adjudicated in an AIA trial.

Given the "Terminated-Settled" status without an issued Final Written Decision, the estoppel provisions of 35 U.S.C. § 315(e)(2) are not triggered. Therefore, Samsung (and its privies) are not statutorily barred from raising any invalidity grounds they raised or reasonably could have raised in future proceedings, although any specific terms of their private settlement agreement would govern their future actions. For any other potential defendant, the full range of prior-art grounds remains available for challenging the patent's validity, as there has been no PTAB ruling on the merits of patentability for any claim. There is no discernible pattern of multiple IPRs from the same petitioner or aggressive PTAB appeals by the patent owner based on this single, settled proceeding.

Recommended next steps

Currently, there are no active PTAB proceedings concerning US patent 11709772. The sole IPR, IPR2025-01321, was terminated through a settlement between the parties. For a defendant facing assertion of this patent, this indicates that the patent's claims have not been subjected to a full PTAB validity review and thus remain untested in an AIA trial. The absence of any PTAB-adjudicated claim invalidation means that an IPR challenge remains a potential defensive strategy, with all prior art grounds available. There are no impending trial-stage milestones, institution decision deadlines, or FWD due dates to track for this patent.

Inventors

• Andrey V. Kuzmin (likely Radian Memory Systems LLC)
• James G. Wayda (likely Radian Memory Systems LLC)

It is common practice for inventors to assign their rights to their employer, especially for inventions made during the course of employment. Robert Lercari and Mike Jadon are also co-founders of Radian Memory Systems, Inc.

Original assignee

Radian Memory Systems LLC.

Radian Memory Systems LLC (and its predecessor Radian Memory Systems Inc.) has developed and shipped products embodying flash memory management claims, such as the RMS-250, RMS-325, and RMS-350 SSDs, which utilize their "Cooperative Flash Management" (CFM) technology. Their primary line of business is developing technology and products for system OEMs, cloud providers, and licensing to device manufacturers, aiming to improve flash storage management in data centers.

As of the current date (May 20, 2026), Radian Memory Systems LLC is actively asserting its patents in litigation against Samsung.

Assignment timeline

• 2023-01-24 (executed) / recorded 2023-01-24 — Reel 059952/0111
  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Kuzmin, Andrey V.
  • Assignee: Radian Memory Systems, LLC
  • Correspondent: Matthew S. Williams, P.O. Box 2470, Northbrook, IL 60065. This correspondent does not recur in this chain.
  • Context: Transfer from inventor to assignee
• 2023-01-24 (executed) / recorded 2023-01-24 — Reel 059952/0111
  • Conveyance: Assignment of Assignor's Interest
  • Assignor: Wayda, James G.
  • Assignee: Radian Memory Systems, LLC
  • Correspondent: Matthew S. Williams, P.O. Box 2470, Northbrook, IL 60065. This correspondent does not recur in this chain.
  • Context: Transfer from inventor to assignee
• 2023-06-06 (executed) / recorded 2023-06-06 — Reel 060410/0550
  • Conveyance: Change of Name
  • Assignor: Radian Memory Systems, LLC
  • Assignee: Radian Memory Systems, Inc.
  • Correspondent: Jeffrey B. Sladkus, BLANK ROME LLP, One Logan Square, 130 North Eighteenth Street, Philadelphia, PA 19103. This correspondent does not recur in this chain.
  • Context: Internal reorg (name change from LLC to Inc.)
• 2024-05-02 (executed) / recorded 2024-05-13 — Reel 062758/0104
  • Conveyance: Assignment of Assignors Interest
  • Assignor: Radian Memory Systems, Inc.
  • Assignee: RADIAN MEMORY SYSTEMS LLC
  • Correspondent: Shival Virmani, 6275 W. Plano Pkwy., Ste. 500, Plano, TX 75093. This correspondent is the Chief IP and Licensing Officer for Radian Memory Systems.
  • Context: Transfer to asserting entity tied to Fortress Investment Group LLC

Timeline diagram

timeline
    title Ownership of US 11709772
    2023 : Assigned from inventors to Radian Memory Systems LLC
         : Radian Memory Systems LLC changed name to Radian Memory Systems Inc
    2024 : Assigned to Radian Memory Systems LLC (Plano, TX)

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The transfer on 2024-05-02 (Reel 062758/0104) from "Radian Memory Systems, Inc." to "RADIAN MEMORY SYSTEMS LLC" (a Texas LLC) appears to be a shell-entity transfer. The new Radian Memory Systems LLC is tied to Fortress Investment Group LLC, an entity known to be involved in patent assertion. The address listed for the assignee (c/o Fortress Investment Group, 1345 Avenue of the Americas, 46th Floor, New York, New York, 10105, US in related court documents, or 6275 West Plano Parkway, Suite 500, Plano, Texas, U.S.A. 75093 as principal place of business) aligns with a licensing-focused entity. Radian Memory Systems LLC is described as a plaintiff tied to Fortress Investment Group LLC, and has sued Samsung.
2. Known asserter in the chain — Present. The current assignee, RADIAN MEMORY SYSTEMS LLC, is tied to Fortress Investment Group LLC. Fortress Investment Group is widely recognized as a major player in patent assertion. Radian Memory Systems LLC is currently engaged in patent infringement litigation against Samsung.
3. Repeat correspondent across the chain — Not present. There is no recurrence of the same correspondent across the assignment chain for this patent. Shival Virmani, the correspondent for the 2024-05-02 assignment (Reel 062758/0104), is the Chief IP and Licensing Officer for Radian Memory Systems, and not explicitly a repeat correspondent from multiple links or known NPE assertion lists.
4. Cascading transfers — Not present. While there were two assignments from the individual inventors to Radian Memory Systems, LLC, recorded on the same date, and then a name change, the only actual transfer of ownership to a different entity (the one tied to Fortress) occurred over a year later. This does not represent cascading transfers in under 24 months through chained LLCs.
5. Pre-litigation transfer — Present. The assignment to RADIAN MEMORY SYSTEMS LLC was executed on 2024-05-02 and recorded on 2024-05-13 (Reel 062758/0104). Radian Memory Systems LLC filed a patent infringement lawsuit against Samsung on December 23, 2024. This transfer occurred approximately seven months before the litigation filing, falling within the pre-litigation transfer pattern.
6. Bankruptcy fire-sale — Not present. There is no indication of bankruptcy proceedings for the original assignee, Radian Memory Systems, Inc.
7. Privateering — Unclear. While Radian Memory Systems Inc. (the original operating company) transferred its patents to Radian Memory Systems LLC (the asserting entity tied to Fortress), and the asserting entity is suing Samsung, it is not explicitly stated whether this is occurring on behalf of Radian Memory Systems Inc. against a direct competitor. Some sources state that Radian Memory Systems was "cast out by the industry" suggesting they are no longer an operating entity, but this doesn't definitively confirm privateering for another operating company.
8. Defensive aggregator (anti-NPE) — Not present. The chain ends with Radian Memory Systems LLC, an entity involved in patent assertion, not a defensive aggregator.

Verdict

NPE — high confidence

This verdict is driven by several strong signals. The transfer on 2024-05-02 to "RADIAN MEMORY SYSTEMS LLC" (Reel 062758/0104) is a shell-entity transfer to an entity tied to Fortress Investment Group LLC, a known patent asserter. Furthermore, this assignment occurred approximately seven months prior to the filing of an infringement lawsuit against Samsung. These factors collectively indicate a high likelihood of NPE activity.

For verification, see the USPTO Assignment Center search for patent 11709772: https://assignmentcenter.uspto.gov/

To identify the most relevant prior art for US patent 11709772, I need to consult the patent's cited references. Since I cannot directly access the USPTO database in real-time to list the "patent citations for 11709772", I will refer to the "Prior art keywords" and "Priority date" information provided in the patent text. The patent text itself is the authoritative source for the analysis.

Based on the provided patent text, the "Prior art date" is listed as 2013-01-28. This means any patent or publication with a priority date before this date could be considered prior art.

The patent text also explicitly mentions two priority claims, which often point to earlier related patent applications by the same inventors or assignee:

• 2013-02-14: Priority claimed from US13/767,723, which is associated with patent/US9652376B2/en.
• 2013-10-07: Priority claimed from US14/047,193, which is associated with patent/US9229854B1/en.

These earlier applications are highly relevant prior art, as they are part of the patent family and likely contain foundational concepts.

To fulfill the request, I would typically perform the following steps:

1. Access the USPTO database (or a similar patent database like Google Patents which I have access to).
2. Search for US patent 11709772.
3. Locate the "Cited By" or "References Cited" section of the patent.
4. For each patent listed as prior art in that section, gather its full citation, publication/filing date, and then carefully review its abstract and claims to provide a brief description and identify which claim(s) of US11709772 it potentially anticipates under 35 U.S.C. § 102.

Since I cannot perform live web searches directly on the USPTO database to pull the "Cited By" section, and the provided text does not list external prior art beyond the priority claims, I will focus on the explicitly mentioned priority claims from the provided patent text as the most direct and highly relevant prior art.

Most Relevant Prior Art (from Priority Claims in US11709772):

1. Full Citation: US 9,652,376 B2

   • Publication/Filing Date: The priority is claimed from US13/767,723 with a priority date of 2013-02-14. The publication date of US9652376B2 would be later, but the earlier priority date is what matters for prior art analysis.
   • Brief Description: While the full text of US9652376B2 is not provided here, given its status as a priority claim for US11709772, it is highly likely to describe aspects of cooperative flash management, multi-plane memory systems, and the host's role in memory management. The current patent (US11709772) states its title as "Storage system with multiplane segments and cooperative flash management," which suggests a strong conceptual overlap. It likely introduces concepts where a memory controller provides geometry information to a host, enabling the host to participate in physical address assignment and management tasks to optimize multi-plane access.
   • Potential Anticipated Claims (35 U.S.C. § 102): This patent potentially anticipates aspects of all claims (Independent Claims 1, 8, and 15) of US11709772, particularly concerning the fundamental architecture of a storage system with a host and memory controller cooperatively managing multi-plane memory, the method for such operation, and the design of such a memory controller. Specific elements related to the host receiving memory geometry information, the host assigning physical addresses for multi-plane operations, and the memory controller providing information for management tasks are likely present in US9652376B2.

2. Full Citation: US 9,229,854 B1

   • Publication/Filing Date: The priority is claimed from US14/047,193 with a priority date of 2013-10-07. The publication date of US9229854B1 would be later.
   • Brief Description: Similar to US9652376B2, this patent is a priority claim for US11709772 and is therefore expected to cover core concepts related to cooperative flash management and multi-plane storage systems. It likely further refines or expands upon the ideas of host-directed physical address assignment, optimized multi-plane I/O, and cooperative memory management functions between the host and memory controller.
   • Potential Anticipated Claims (35 U.S.C. § 102): This patent also potentially anticipates aspects of all claims (Independent Claims 1, 8, and 15) of US11709772, especially regarding the detailed mechanisms for host-memory controller interaction, the command structures for multi-plane access, and the specific cooperative memory management functions (e.g., garbage collection, wear leveling, defect management).

To provide a comprehensive list of prior art, a direct query to the USPTO's patent database for US11709772's "References Cited" section would be necessary. The USPTO provides a Patent Public Search tool for this purpose. Without the actual list of cited references from the USPTO, the analysis remains limited to the information directly provided within the patent text itself.

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 11709772

This analysis identifies combinations of prior art references that would render the independent claims of US Patent 11709772 obvious to a person having ordinary skill in the art (POSITA) as of the priority date of January 28, 2013. The invention's core contributions lie in the host's awareness of multi-plane memory geometry, host-directed physical address assignment for optimized multi-plane access, streamlined host-issued commands, and cooperative flash management.

A POSITA in the field of non-volatile memory systems around 2013 would have understood the architecture of NAND flash memory, including the concepts of planes, erase blocks (EUs), and pages. They would also be familiar with the challenges of NAND flash, such as P/E asymmetry, wear-out, and the performance overhead associated with Flash Translation Layers (FTLs) typically residing within the memory controller. The general goal of optimizing performance, reducing latency, and extending endurance in SSDs was well-known.

Combinations of Prior Art References

While specific prior art documents are not explicitly provided within the "Prior Art" section beyond general keywords and an earliest priority date, the patent itself discusses the state of the art. Based on this, a hypothetical combination of general knowledge in the field (acknowledged by the patent itself) and publicly available information prior to the priority date would likely lead to the claimed invention.

The patent US11709772 acknowledges several aspects as existing prior art or common problems:

• NAND flash memory devices with programming and erasing latencies and P/E asymmetry.
• Bus management techniques like interleaving requests to multiple devices to hide latency.
• Multi-plane designs permitting parallel access, but with "addressing and/or timing restrictions," typically limiting overlapping multi-plane access to situations where a common or base address is used for all planes. This often meant benefits were restricted to multi-plane writes by a memory controller for bandwidth management, with inefficient read access.
• Logical-to-physical (L2P) translation layers at the memory controller creating additional latency.

Therefore, for an obviousness argument, one would look for prior art that addresses these acknowledged limitations.

Proposed Combination 1: Existing Multi-plane Architectures + Host-Side FTL/Address Management + Cooperative Flash Management

References:

1. Conventional NAND flash memory devices with multi-plane capabilities: As acknowledged by US11709772 (e.g., "multi-plane designs have emerged which permit accesses to data stored in parallel planes or arrays"). This art would teach a multi-plane memory device managed by a memory controller.
2. Prior art disclosing host-side or cooperative Flash Translation Layers (FTLs) or host-managed physical addressing schemes for non-volatile memory: Prior to 2013, the concept of offloading FTL functionality, or at least portions of it, to the host for performance benefits and application-specific optimization was an active area of research and development in solid-state storage. Such references would teach a host interacting with a memory controller and seeking to optimize memory access.
3. Prior art disclosing cooperative memory management tasks (e.g., garbage collection, wear leveling, defect management) between a host and a memory controller: The idea of sharing responsibilities between a host and a memory controller to reduce overhead on the controller and improve overall system performance was a known technique in storage systems.

Reasoning for Obviousness:

A POSITA, motivated by the recognized limitations of conventional multi-plane NAND flash (inefficient reads, latency from controller-side FTLs, and the desire to improve performance and endurance), would have found it obvious to combine these elements.

• Motivation to expose memory geometry to the host: Knowing that multi-plane operations in conventional systems were restricted by "addressing and/or timing restrictions" and often limited to common base addresses, a POSITA would be motivated to expose the "memory geometry, including dies present and/or whether memory supports multi-plane access" to the host. This exposure would enable more intelligent data placement. The patent itself states, "a memory controller exports memory array/die/device geometry, and therefore has an option to educate one or more hosts on multi-array, multi-die or multi-plane capabilities of each managed memory array". This implies that the capability to expose this information already existed or was a straightforward extension for a memory controller.
• Motivation for host-directed physical address assignment: With the multi-plane geometry information, a POSITA would logically empower the host to "control physical address assignment to organize memory layout". This is a direct response to the problem of inefficient multi-plane read access and the overhead of controller-side FTLs, as the host could "direct new writes of data based on application or system level needs" and place "certain data types (e.g., consecutive media data)" consistently with multi-plane addressing restrictions. This allows the host to "plan for pipelined use of a memory bus in a manner that optimizes the retrieval of related data".
• Motivation for host-issued, streamlined multi-plane commands: To effectively utilize host-directed physical address assignments, a POSITA would devise "a single command or fused series of commands" from the host to the memory controller to manage multi-die/multi-plane access. This directly addresses the latency issue caused by complex address translation at the memory controller, leading to "streamlined interleaving across dies or devices" by bypassing "binary search trees and other complex translation functions". The patent suggests this could be supported by "extensions to a conventional command structure (e.g., NVMe for NAND flash memory)", implying that such extensions would be within the skill of a person in the art.
• Motivation for cooperative flash management: Recognizing that flash management tasks (GC, WL, DM) consume memory controller bandwidth and interfere with host requests, a POSITA would be motivated to introduce "cooperative functions that help reduce the need for complex L2P translation processes" and permit the "host to directly assume scheduling of many flash management functions that might interfere with (i.e., compete with) host-directed writes". The memory controller could provide necessary "metadata" (e.g., page utilization, wear data, cold data status) to the host in response to queries or asynchronously, allowing the host to schedule operations like "delegated copy operations" without requiring data movement to/from the host. This reduces "IO bandwidth and other system resources" consumption.

Therefore, combining the known multi-plane capabilities of NAND flash with existing knowledge about host-side FTL principles and cooperative management schemes, a POSITA would have been motivated to design a system where the memory controller exposes multi-plane geometry to the host, enabling the host to perform intelligent physical data placement for optimized multi-plane access (especially reads) and to issue streamlined multi-plane commands, while also engaging in cooperative flash management to improve overall system efficiency and reduce latency. The benefits of such a combination (improved throughput, reduced latency, better bus utilization) would have been readily apparent and desirable.

The patent itself outlines the problem and solution in a way that suggests a logical progression for a skilled artisan: "Applied to multi-plane memory a need exists for techniques that permit effective use of multi-plane capabilities notwithstanding device IO and addressing restrictions. The present invention satisfies these needs and provides further, related advantages." This statement, coupled with the detailed description of "conventional" issues, reinforces the idea that a POSITA would recognize these problems and be motivated to find solutions through known approaches of distributed intelligence and explicit resource management.