US 11550512

US Patent 11550512: Analytics, Algorithm Architecture, and Data Processing System and Method

Title: Analytics, algorithm architecture, and data processing system and method

Assignee: Fermat International Inc.

Inventors: Robert Bismuth, Mike Stengle

Filing Date: February 7, 2022

Issue Date: January 10, 2023

Abstract: The disclosed subject matter generally relates to high-performance data processing, focusing on systems and methods employing a distributed hardware architecture, either independently or with a data structure. This is used for various data processing strategies and data analytics implementations. Additionally, or alternatively, the disclosure covers a unique algorithm architecture and processing system and method that can be implemented, independently or with an attendant data structure, for data processing strategies and analytics in various contexts.

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Plain-Language Overview of Independent Claims:

Here's a plain-language summary of the independent claims of US Patent 11550512:

Claim 1: Data Processing Method with Compute Node
This claim describes a method for executing data processing operations. It involves a "compute node" that works independently of a host computer but is connected to it. This compute node has a programmable logic component (like an FPGA) that runs data processing tasks with a first memory. A "data mover" component helps transfer data between this programmable logic and a second memory. The method includes using instructions to reformat data blocks, changing them from records with mixed field types into new records where all fields are of a single type. Finally, multiple communication channels are used to move this reformatted data between the programmable logic and the first memory.

Claim 10: Data Processing System with Router and Compute Node
This claim outlines a data processing system that works with a host computer. It includes a "router module" with interfaces for both the host and a compute node. The compute node connects to the router module via a communication link and contains a data store, a programmable logic component for executing operations, a node memory for support data and instructions, a data mover for internal data communication, and a storage interface. This storage interface uses multiple communication channels to transfer data between itself and the data store.

Claim 16: Data Processing System with Reformatting Capability
This claim describes a data processing system similar to Claim 10, including a router module and a compute node with a communications link, data store, programmable logic, node memory, data mover, and storage interface. The key difference here is that the programmable logic component is specifically configured to execute instructions to reformat a block of data. This reformatting changes original records (which have multiple field types) into new records where each new record contains fields of only a single type from the original records.

Claim 17: Distributed Algorithm Execution Method
This claim details a method for running an algorithm in a distributed processing environment. It involves an initiating compute node with memory, and one or more additional compute nodes connected in a series (forming an "execution pipeline"). Each compute node in this pipeline has its own memory. The method starts by loading an instruction set for the algorithm into the programmable logic of each compute node. The initiating node performs the first operation using these instructions and data from its memory, then passes the results to the next compute node. Subsequent nodes in the pipeline then execute their part of the algorithm using the instructions and the results from the previous node.

Claim 19: Compute Node for Data Reformatting
This claim describes a compute node itself. It's connected to a host computer but operates independently for data processing. It includes a programmable logic component (like an FPGA) that executes data processing using a first memory. A data mover facilitates data transfer between the programmable logic and a second memory. The compute node also has instructions that allow the programmable logic to reformat data: taking original records with different field types and transforming them into new records where all fields within a new record are of a single field type from the original. Multiple communication channels are used for data transfer between the programmable logic and the first memory.

Claim 23: Method of Processing Data with Optimized Output
This claim describes a method for processing data, specifically focused on maximizing output from a memory component. It involves retrieving a page of data from a memory, copying it to a cache, and then transferring this cached data to a compute array. Crucially, the method continuously issues further read commands to the memory component while data from previously initiated reads are still being transferred from the cache to the compute array. This overlapping of read commands and data transfers is designed to maximize the data output rate from the memory component.

Claim 24: Method of Processing Data with Co-located Related Data
This claim describes a method for processing data that involves receiving data from multiple independent sources, where some of this data is considered "related." Metadata is used to identify these relationships. The method then stores this related data in a "co-located" manner within a data store. This means related data is placed in memory locations that are physically or logically close to each other. When an algorithm is executed, the co-located related data is retrieved using a single read operation, improving efficiency.

Claim 25: Algorithm Processing System with Management Node and Pipeline
This claim defines a data processing system for executing algorithms. It includes a "management node" connected to a host computer and to a "memory-supported compute node" via a communications link. This memory-supported compute node has a data store, a programmable logic component, and a node memory. The system also features a "pipeline" of one or more additional compute nodes, each serially connected to the previous one (starting with the memory-supported compute node). Each of these additional compute nodes contains its own memory, a data store, and a programmable logic component.

Claim 26: Algorithm Processing System with Distributed Nodes
This claim describes a data processing system similar to Claim 25, with a management node and a memory-supported compute node. The key distinguishing feature is that each of the "one or more additional compute nodes" in the pipeline has its own communications link, data store, programmable logic, and node memory, and is connected to an "upstream compute node." The system uses a specific methodology to execute algorithms across these distributed compute nodes.

Claim 28: System for Executing Data Processing Operations with Interrupt Handling
This claim outlines a system for executing data processing operations. It includes a router module and a compute node. The compute node has a data store, a programmable logic component, and a processing system. The processing system comprises a first set of processors to manage data transfer apparatus (DMAs) and a second set of processors for general administrative tasks and algorithm execution support. The system is characterized by DMAs that issue interrupts to the first set of processors based on specific events (like a timeout or a transaction threshold), allowing these processors to respond by exchanging status information or performing other functions.

Claim 30: Method of Managing Data with Page Updates
This claim describes a method for managing data stored in pages within a data store. When a page of data needs to be updated, the method involves reading the entire page, modifying the specific data, and then writing a new copy of the modified page to a new location in the data store. This new copy is given an updated identifier (an "incarnation counter") to distinguish it from the old version. The method also maintains a page pointer index that is updated with the new location and incarnation counter to ensure the latest version of the page is always accessible.

Claim 31: Method of Managing Data Store with Block Recycling
This claim describes a method for managing a data store, specifically focusing on recycling memory blocks efficiently. It involves tracking two metrics for each block: a "valid page (VP) count" (number of valid pages in the block) and a "continuity factor (CF)" (number or percentage of pages in the block that are outdated). These metrics are then used to assign a priority for recycling operations. Blocks with a high continuity factor (meaning many outdated pages) are given a higher priority for recycling.

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CAFC 2026 Dockets for US11550512:

As of April 26, 2026, a search for US patent 11550512 in the CAFC 2026 dockets did not return any direct results indicating a case filed in the CAFC specifically for 2026. However, the Google Patents information for US11550512 notes that there is active litigation related to this patent. Specifically, a US case was filed in the Texas Western District Court, identified as case 7:26-cv-00011. Additionally, it states that the first worldwide family litigation has been filed. These district court cases could potentially lead to appeals at the CAFC in the future, but there is no explicit CAFC 2026 docket record provided at this time.The user has requested to summarize patent 11550512, including its title, assignee, inventors, filing date, issue date, abstract, and a plain-language overview of each independent claim. I have already performed the initial extraction of this information from the provided Google Patents URL in the previous turn, and I have also identified all independent claims.

The last part of the request is to search "CAFC 2026 dockets for the specific patent number 11550512." I performed a search for this in the last turn, and the result indicated no direct CAFC dockets for 2026, but identified existing district court litigation. I will reiterate this information clearly.

Now I need to compile all this information into the final concise summary. I already have all the necessary information.## US Patent 11550512: Analytics, Algorithm Architecture, and Data Processing System and Method

Title: Analytics, algorithm architecture, and data processing system and method

Assignee: Fermat International Inc.

Inventors: Robert Bismuth, Mike Stengle

Filing Date: February 7, 2022

Issue Date: January 10, 2023

Abstract: The disclosed subject matter generally relates to high-performance data processing, focusing on systems and methods employing a distributed hardware architecture, either independently or with a data structure. This is used for various data processing strategies and data analytics implementations. Additionally, or alternatively, the disclosure covers a unique algorithm architecture and processing system and method that can be implemented, independently or with an attendant data structure, for data processing strategies and analytics in various contexts.

---

Plain-Language Overview of Independent Claims:

Here's a plain-language summary of the independent claims of US Patent 11550512:

• Claim 1: Data Processing Method with Compute Node: This claim describes a method for executing data processing operations. It involves a "compute node" that works independently of a host computer but is connected to it. This compute node has a programmable logic component (like an FPGA) that runs data processing tasks with a first memory. A "data mover" component helps transfer data between this programmable logic and a second memory. The method includes using instructions to reformat data blocks, changing them from records with mixed field types into new records where all fields are of a single type. Finally, multiple communication channels are used to move this reformatted data between the programmable logic and the first memory.

• Claim 10: Data Processing System with Router and Compute Node: This claim outlines a data processing system that works with a host computer. It includes a "router module" with interfaces for both the host and a compute node. The compute node connects to the router module via a communication link and contains a data store, a programmable logic component for executing operations, a node memory for support data and instructions, a data mover for internal data communication, and a storage interface. This storage interface uses multiple communication channels to transfer data between itself and the data store.

• Claim 16: Data Processing System with Reformatting Capability: This claim describes a data processing system similar to Claim 10, including a router module and a compute node with a communications link, data store, programmable logic, node memory, data mover, and storage interface. The key distinguishing feature is that the programmable logic component is specifically configured to execute instructions to reformat a block of data. This reformatting changes original records (which have multiple field types) into new records where each new record contains fields of only a single type from the original records.

• Claim 17: Distributed Algorithm Execution Method: This claim details a method for running an algorithm in a distributed processing environment. It involves an initiating compute node with memory, and one or more additional compute nodes connected in a series (forming an "execution pipeline"). Each compute node in this pipeline has its own memory. The method starts by loading an instruction set for the algorithm into the programmable logic of each compute node. The initiating node performs the first operation using these instructions and data from its memory, then passes the results to the next compute node. Subsequent nodes in the pipeline then execute their part of the algorithm using the instructions and the results from the previous node.

• Claim 19: Compute Node for Data Reformatting: This claim describes a compute node itself. It's connected to a host computer but operates independently for data processing. It includes a programmable logic component (like an FPGA) that executes data processing using a first memory. A data mover facilitates data transfer between the programmable logic and a second memory. The compute node also has instructions that allow the programmable logic to reformat data: taking original records with different field types and transforming them into new records where all fields within a new record are of a single field type from the original. Multiple communication channels are used for data transfer between the programmable logic and the first memory.

• Claim 23: Method of Processing Data with Optimized Output: This claim describes a method for processing data, specifically focused on maximizing output from a memory component. It involves retrieving a page of data from a memory, copying it to a cache, and then transferring this cached data to a compute array. Crucially, the method continuously issues further read commands to the memory component while data from previously initiated reads are still being transferred from the cache to the compute array. This overlapping of read commands and data transfers is designed to maximize the data output rate from the memory component.

• Claim 24: Method of Processing Data with Co-located Related Data: This claim describes a method for processing data that involves receiving data from multiple independent sources, where some of this data is considered "related." Metadata is used to identify these relationships. The method then stores this related data in a "co-located" manner within a data store. This means related data is placed in memory locations that are physically or logically close to each other. When an algorithm is executed, the co-located related data is retrieved using a single read operation, improving efficiency.

• Claim 25: Algorithm Processing System with Management Node and Pipeline: This claim defines a data processing system for executing algorithms. It includes a "management node" connected to a host computer and to a "memory-supported compute node" via a communications link. This memory-supported compute node has a data store, a programmable logic component, and a node memory. The system also features a "pipeline" of one or more additional compute nodes, each serially connected to the previous one (starting with the memory-supported compute node). Each of these additional compute nodes contains its own memory, a data store, and a programmable logic component.

• Claim 26: Algorithm Processing System with Distributed Nodes: This claim describes a data processing system similar to Claim 25, with a management node and a memory-supported compute node. The key distinguishing feature is that each of the "one or more additional compute nodes" in the pipeline has its own communications link, data store, programmable logic, and node memory, and is connected to an "upstream compute node." The system uses a specific methodology to execute algorithms across these distributed compute nodes.

• Claim 28: System for Executing Data Processing Operations with Interrupt Handling: This claim outlines a system for executing data processing operations. It includes a router module and a compute node. The compute node has a data store, a programmable logic component, and a processing system. The processing system comprises a first set of processors to manage data transfer apparatus (DMAs) and a second set of processors for general administrative tasks and algorithm execution support. The system is characterized by DMAs that issue interrupts to the first set of processors based on specific events (like a timeout or a transaction threshold), allowing these processors to respond by exchanging status information or performing other functions.

• Claim 30: Method of Managing Data with Page Updates: This claim describes a method for managing data stored in pages within a data store. When a page of data needs to be updated, the method involves reading the entire page, modifying the specific data, and then writing a new copy of the modified page to a new location in the data store. This new copy is given an updated identifier (an "incarnation counter") to distinguish it from the old version. The method also maintains a page pointer index that is updated with the new location and incarnation counter to ensure the latest version of the page is always accessible.

• Claim 31: Method of Managing Data Store with Block Recycling: This claim describes a method for managing a data store, specifically focusing on recycling memory blocks efficiently. It involves tracking two metrics for each block: a "valid page (VP) count" (number of valid pages in the block) and a "continuity factor (CF)" (number or percentage of pages in the block that are outdated). These metrics are then used to assign a priority for recycling operations. Blocks with a high continuity factor (meaning many outdated pages) are given a higher priority for recycling.

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CAFC 2026 Dockets for US11550512:

As of April 26, 2026, a search for US patent 11550512 in the CAFC 2026 dockets did not return any direct results indicating a case filed in the CAFC specifically for 2026. However, the Google Patents information for US11550512 notes that there is active litigation related to this patent. Specifically, a US case was filed in the Texas Western District Court, identified as case 7:26-cv-00011. Additionally, it states that the first worldwide family litigation has been filed. These district court cases could potentially lead to appeals at the CAFC in the future, but no explicit CAFC 2026 docket record has been found at this time.