Obviousness

Obviousness Analysis of US Patent 11,538,763 Under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that would render the independent claims of US Patent 11,538,763 (hereinafter "the '763 patent") obvious to a person having ordinary skill in the art (PHOSITA) as of its priority date of September 26, 2012. The analysis relies on the prior art explicitly referenced and discussed within the '763 patent itself, particularly US Pat. No. 9,615,453 (hereinafter "'453 patent") and general knowledge in the semiconductor packaging and display industries as described in the background section of the '763 patent.

Due to the limitations of the provided tools, the full text of US Pat. No. 9,615,453 was not directly retrieved. However, based on the '763 patent stating that it is a continuation-in-part of the application that led to the '453 patent, and the '763 patent's detailed discussion of "Through Glass Vias (TGV's)" in the context of glass interposers, it is reasonably assumed that the '453 patent teaches the fundamental concept of a glass substrate incorporating through-glass metal conductors (metal plugs) for chip packaging or interposer applications. This assumption aligns with the background section of the '763 patent, which describes the use of "glass as an interposer to bridge between one or more IC chips and a printed circuit board" and notes the "difficulty in forming Through Glass Vias (TGV's)," indicating that this technology was a focus of the patent family.

Analysis of Independent Claim 1 (Display Device)

Claim 1 of the '763 patent describes a display device comprising:

• A display panel substrate with multiple contact pads and a display area defined by edges and boundaries, where the least distances between the display area's edges and the panel's boundaries are smaller than 100 micrometers.
• A glass substrate over the display panel substrate.
• Multiple metal conductors passing through the glass substrate.
• Multiple metal bumps between the glass substrate and the display panel substrate, connecting the metal conductors to the contact pads.

Combination of Prior Art:

1. US Pat. No. 9,615,453 (assumed): Teaches a glass interposer with through-glass metal conductors (or "metal plugs") used in chip packaging.
2. General knowledge in the display industry: A PHOSITA in the display field would be well aware of the continuous market demand and technical drive to reduce the "bezel" or border size around display areas for aesthetic and functional reasons, leading to a desire for "first, second, third and fourth least distances are smaller than 100 micrometers." The background of the '763 patent itself acknowledges the trend for microelectronic devices to be "minimized and thinned."

Motivation for Combination:
A PHOSITA would be motivated to combine the teachings of the '453 patent (glass interposer with TGVs) with the known desire for narrow-bezel displays. The glass substrate, being transparent, is a natural candidate for an overlying layer in a display device. Integrating the metal conductors (TGVs) within this glass substrate, as taught by the '453 patent, provides a compact and efficient means of routing electrical signals from the display panel's contact pads to external connections or other chips. This high-density routing capability enabled by TGVs would directly facilitate the reduction of the border area around the display, allowing for the "least distances" to be "smaller than 100 micrometers." The use of metal bumps for electrical connection between the glass substrate and the display panel substrate is a known and established technique in microelectronics, such as Chip-on-Glass (COG) bonding or flip-chip technology, which is explicitly mentioned as known in the background of the '763 patent. Therefore, utilizing a glass substrate with integrated through-glass conductors to enable a narrow-bezel display device would be an obvious design choice for a PHOSITA.

Analysis of Independent Claim 10 (Chip Package)

Claim 10 of the '763 patent describes a chip package comprising:

• A first substrate having a glass layer with multiple metal plugs extending through it, with their top and bottom surfaces coplanar with the respective glass layer surfaces.
• A first dielectric layer on the top surface of the first substrate, with openings exposing the metal plugs.
• A first metal layer on the first dielectric layer and in the openings, contacting the metal plugs.
• A second metal layer on the first metal layer.
• A second dielectric layer covering the first dielectric layer and the second metal layer, with openings exposing the second metal layer.
• A third metal layer on the second dielectric layer and in the openings, contacting the second metal layer.
• A fourth metal layer on the third metal layer.
• At least one chip on the fourth metal layer.

Combination of Prior Art:

1. US Pat. No. 9,615,453 (assumed): Teaches a glass substrate with through-glass metal plugs (TGVs) that are coplanar with the substrate surfaces. This forms the "first substrate" base of Claim 10.
2. Background of the '763 patent and general knowledge in semiconductor packaging: The '763 patent's background discusses the increasing importance of metal connections, parasitic capacitance and resistance, and attempts to use "low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines." This highlights the known challenges and solutions related to interconnect performance. Multi-layer redistribution layers (RDLs), consisting of alternating dielectric and metal layers, are a well-established technique in advanced semiconductor packaging to provide signal routing, power delivery, and fan-out capabilities between chips and packages. The materials described for the dielectric layers (e.g., silicon oxide, polyimide) and metal layers (e.g., titanium, copper, nickel, gold) in the '763 patent are standard RDL materials and processes (e.g., PVD, PECVD, sputtering, electroplating) are well-known fabrication methods.

Motivation for Combination:
A PHOSITA would be motivated to combine the glass interposer with TGVs (from the '453 patent) with standard RDL technology. The '763 patent's background explicitly recognizes the problems of parasitic effects in metal interconnections and the need for low resistance metals and low dielectric materials. Building multi-layer RDLs, as described in Claim 10 (first dielectric/metal, second dielectric/metal, etc.), on the glass interposer with TGVs is a direct and obvious solution to address these performance issues and provide the necessary routing complexity for connecting chips. The TGVs in the glass substrate provide vertical interconnects, while the RDLs on the surface provide horizontal routing and fan-out, enabling sophisticated chip packages. Placing a chip on the topmost metal layer (fourth metal layer) is the logical endpoint of such an RDL structure.

Analysis of Independent Claim 11 (Chip Package with Specific Chip Connection)

Claim 11 of the '763 patent describes a chip package comprising:

• All features of Claim 10.
• The at least one chip on the fourth metal layer comprises multiple metal pads and multiple metal bumps formed on the metal pads, wherein the metal bumps are connected to the fourth metal layer.

Combination of Prior Art:

1. All elements of Claim 10 (as rendered obvious above).
2. Background of the '763 patent and general knowledge in semiconductor packaging: The '763 patent's background extensively describes "Flip-chip Packages," stating that "Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads of chip and interconnects the bumps directly to the package media" to achieve "highest density of interconnection to the device and a very low inductance interconnection."

Motivation for Combination:
Given the chip package structure of Claim 10 (a glass interposer with multi-layer RDLs), a PHOSITA would be strongly motivated to connect chips to this structure using flip-chip technology. The '763 patent's background explicitly endorses flip-chip for its high interconnection density and low inductance, which are critical for meeting the "increased demands for high performance" in ICs. Therefore, adapting the well-known flip-chip bonding technique—which involves forming metal pads and metal bumps on the chip and connecting these bumps to the corresponding pads/layers (like the fourth metal layer in Claim 11) on the package medium (the glass interposer with RDLs)—is a straightforward and obvious choice for a PHOSITA seeking to achieve the known benefits of flip-chip packaging within the described structure.