Obviousness

Obviousness Analysis under 35 U.S.C. § 103 for US11456365

The present invention, US11456365, describes a memory transistor featuring a multi-layer charge storage layer and a high work function gate electrode, designed to enhance data retention and improve programming time and efficiency. A key aspect of the multi-layer charge trapping layer is its structure, which includes an oxygen-rich first nitride layer, an oxygen-lean second nitride layer, and an oxide anti-tunneling layer positioned between them, forming an ONONO (Oxide-Nitride-Oxide-Nitride-Oxide) stack (Abstract, Summary,,). The patent also emphasizes the use of a high work function gate electrode, often comprising doped polysilicon, compatible with CMOS processes and suitable for System-On-Chip (SOC) applications where logic and memory transistors are integrated on a common substrate (,-). Furthermore, the invention details applications in various device architectures, including planar, FinFET, and nanowire configurations (,-).

A person having ordinary skill in the art (PHOSITA) in semiconductor device fabrication and non-volatile memory would be motivated to address known problems in flash memory technology, specifically improving data retention, programming/erase speed, and scalability, as highlighted in the background of US11456365 (-). These problems include rapid voltage window collapse in silicon-rich nitride layers (FIG. 1A) and reduced initial program-erase windows in high-quality nitride layers (FIG. 1B).

For this obviousness analysis, we consider the priority date of US11456365, which is May 25, 2007. The patent itself explicitly references U.S. Patent No. 8,063,434 (US8063434B1), which issued from U.S. patent application Ser. No. 12/152,518 filed May 13, 2008, and claims benefit of the same provisional application (60/940,160, filed May 25, 2007). Therefore, US8063434B1 represents a highly relevant prior art reference, likely disclosing many foundational aspects of the claimed invention.

Combination 1: US8063434B1 in view of general knowledge regarding multi-layer charge traps and high-K gate dielectrics.

Primary Reference: US8063434B1
The abstract of US8063434B1 discloses a non-volatile memory transistor with a multi-layer charge trapping dielectric layer and a high work function gate electrode, specifically mentioning a polysilicon channel, a tunneling dielectric layer, a multi-layer charge trapping region, a blocking dielectric layer, and a high work function gate electrode. It states that the multi-layer charge trapping region includes at least one oxygen-rich first nitride layer and one oxygen-lean second nitride layer. It also notes that the high work function gate electrode "is doped to a concentration or dose selected so that the minimum energy needed to remove an electron from the gate electrode is from at least about 4.8 eV to about 5.3 eV".

Identified Differences from US11456365:
Based on the abstract of US8063434B1, the main feature not explicitly mentioned is the oxide anti-tunneling layer located between the oxygen-rich first nitride layer and the oxygen-lean second nitride layer within the multi-layer charge trapping region, which creates the distinctive ONONO stack within the gate dielectric. While US8063434B1 mentions the two types of nitride layers, the specific interposition of an oxide anti-tunneling layer is a distinguishing feature of US11456365.

Motivation for Combination:
A PHOSITA would have been motivated to introduce an anti-tunneling layer between charge trapping layers to further improve data retention and reduce leakage, which were known challenges in non-volatile memory at the time. The background of US11456365 explicitly states that "the charge stored or trapped in the charge trapping layer decreases over time due to leakage current through the insulating layers". The patent itself describes the anti-tunneling layer as "substantially reduc[ing] the probability of electron charge that accumulates at the boundaries of the oxygen-lean second nitride layer... from tunneling into the first nitride layer..., resulting in lower leakage current" (). The use of oxide layers within ONO stacks for blocking or tunneling functions was well-established in the art. Therefore, extending this concept to isolate distinct charge-trapping nitride layers to prevent charge leakage and enhance retention would have been a logical and predictable design choice for a PHOSITA.

The use of high work function gate electrodes is explicitly present in US8063434B1 and in US11456365. Similarly, the use of oxygen-rich and oxygen-lean nitride layers in combination in a charge trapping layer is also disclosed in US8063434B1 and is a core part of US11456365. The novelty primarily resides in the specific ONONO dielectric stack configuration and the advantages derived from it.

Combination 2: US8063434B1 in view of general knowledge regarding multi-layer dielectrics for charge trapping memory.

Primary Reference: US8063434B1
As described above, US8063434B1 discloses a non-volatile memory transistor with a multi-layer charge trapping dielectric layer (oxygen-rich and oxygen-lean nitrides) and a high work function gate electrode.

Secondary Reference/General Knowledge:
Prior to the priority date of US11456365, the field of non-volatile memory extensively explored various multi-layer dielectric stacks beyond simple ONO structures to optimize charge trapping and retention. For instance, modified ONO structures, including those with additional layers or variations in composition, were known to address issues like charge loss. The use of an oxide layer as an anti-tunneling barrier or a blocking layer to prevent charge leakage in memory devices was a common technique.
US11456365 itself discusses conventional memory transistors and their limitations related to data retention, implying that efforts to improve insulating layers were ongoing (-).

Motivation for Combination:
Given US8063434B1's disclosure of a multi-layer charge trapping region comprising both oxygen-rich and oxygen-lean nitride layers, a PHOSITA would be motivated to further optimize the charge retention characteristics of such a structure. Knowing that leakage through insulating layers is a primary cause of data loss (), and that oxide layers are effective barriers to charge transport, it would have been obvious to insert an oxide anti-tunneling layer between the distinct nitride layers described in US8063434B1. This would serve to isolate the charge stored in one nitride layer from leaking into the other or out of the trapping region, thereby improving overall data retention. The choice of an oxide layer for this purpose would be a predictable application of known dielectric engineering principles to solve the persistent problem of charge leakage in charge-trap memories. The patent explicitly notes that the anti-tunneling layer "substantially reduces the probability of electron charge that accumulates at the boundaries... from tunneling... resulting in lower leakage current" (), which directly addresses the problem of data retention due to leakage.

Conclusion

Based on this analysis, the claims of US11456365, particularly those directed to the specific ONONO stack within the charge trapping layer, would likely have been obvious to a PHOSITA in light of the disclosures of US8063434B1 combined with the general knowledge in the field regarding multi-layer dielectric engineering for improving charge retention and reducing leakage in non-volatile memory devices. The motivation would stem from the recognized need to overcome limitations in data retention and leakage currents in existing charge-trap memory architectures.