US 11018678

US Patent 11018678, titled "Field programmable gate array with internal phase-locked loop," was issued to HFT Solutions LLC on May 25, 2021, with an anticipated expiration date of October 31, 2039. The inventor is Nima Badizadegan, and the application was originally filed on July 23, 2020. The patent's legal status is active.

As of April 26, 2026, a search of the CAFC 2026 dockets for patent US11018678B1 did not reveal any directly scheduled cases.

Abstract:
A field programmable gate array system includes a field programmable gate array (FPGA) comprising a first interface including a first reference clock pin, a second reference clock pin, a first plurality of data pins, and a second plurality of data pins. A deserializer is operationally connected to the first reference clock pin to receive a first clock signal and to the first plurality of data pins to receive a first serial data stream. The deserializer is configured to convert the first serial data stream into a first plurality of parallel data streams and to generate a first receiver side clock signal. Computational circuitry is operationally connected to the deserializer to receive the first plurality of parallel data streams and the first receiver side clock signal. A serializer is operationally connected to the computational circuitry to receive a second plurality of parallel data streams and a first transmitter side clock signal. A phase detector is operationally connected to the deserializer and the serializer to receive the first receiver side clock signal and the first transmitter side clock signal. An internal phase controller is operationally connected to the phase detector and to an adjustable phase lock loop (PLL) to receive an output of the phase detector and to provide adjustment information to the adjustable PLL to adjust a phase of a first wire rate clock signal.

Plain-Language Overview of Independent Claims:

• Claim 1: Field Programmable Gate Array System (Internal PLL)
  This claim describes an FPGA system that includes an FPGA chip. This chip has interfaces for receiving incoming and transmitting outgoing data and clock signals. Inside, a deserializer converts high-speed serial input data into slower parallel data streams, generating a receiver-side clock. Computational logic processes this parallel data. A serializer then converts the processed parallel data back into a high-speed serial output, using a transmitter-side clock. A crucial aspect is an internal phase detector that compares the receiver-side and transmitter-side clocks to identify any phase difference. This difference is fed to an internal phase controller, which then instructs an adjustable Phase-Locked Loop (PLL) (also within the FPGA) to adjust the phase of the clock signal used by the serializer, aiming to align the transmit and receive clocks.

• Claim 11: Field Programmable Gate Array System (External Phase Detector)
  Similar to Claim 1 in its core FPGA components (interfaces, deserializer, computational logic, serializer), this claim distinguishes itself by placing the phase detector outside the FPGA. The receiver-side and transmitter-side clock signals are routed off the FPGA to this external phase detector. An internal phase controller on the FPGA receives the phase difference information from this external detector and uses it to provide adjustment information to an adjustable oscillator (which may also be external to the FPGA). This external oscillator then generates an adjusted clock signal for the serializer, thus controlling the transmit clock's phase.

• Claim 18: Method for Processing Data (Internal Phase Detector)
  This claim outlines a method for using an FPGA system to process market data into order entry data. It involves: receiving market data and a clock signal, deserializing the data, performing calculations, and generating an interim transmitter clock signal. The method then describes an internal phase detector on the FPGA comparing the receiver and interim transmitter clocks. An internal phase controller generates adjustment data based on this comparison, which is used to modify an internal adjustable oscillator. This adjusted clock then dictates the final serialization of the order entry data for transmission.

• Claim 24: Method for Processing Data (External Phase Detector)
  This method claim also focuses on processing market data into order entry data. However, it specifies that the receiver-side and interim transmitter-side clock signals are sent off the FPGA to an external phase detector. The phase difference detected externally is communicated back to an internal phase controller on the FPGA. This controller then sends adjustment information to an external adjustable oscillator. The externally adjusted clock signal is then routed back into the FPGA to the serializer, which uses it to transmit the order entry data.

• Claim 29: Field Programmable Gate Array System (First Clock for Second Pin)
  This claim describes an FPGA system structurally similar to Claim 1, including internal phase detection and adjustment. The unique aspect here is that the FPGA's second reference clock pin, which would typically receive a separate transmit clock input, is instead configured to receive the same first clock signal that the first reference clock pin uses for the deserializer. This suggests that both the receive and transmit timing might originate from a single external clock source, with the internal adjustable PLL then managing the phase alignment of the serializer's clock relative to this common source.

As of April 26, 2026, there is no known litigation involving US Patent 11018678. Searches of publicly available patent litigation databases such as Unified Patents and CAFC dockets, as well as general searches, did not yield any results for this specific patent number. While PACER provides access to federal court records, a specific case number would be needed for a direct search, and generalized searches for patent numbers are not its primary function.

Proceedings overview

Currently, there is one active AIA trial proceeding on US Patent 11018678. This Inter Partes Review (IPR) is in the very early stages of its lifecycle, having been filed just yesterday. For a defendant facing assertion of this patent, the defensive posture is that the patent's validity is currently being challenged, but no claims have been invalidated or sustained by the PTAB yet.

IPR2026-00385 — Optiver US LLC et al. v. HFT Solutions LLC

• Type: Inter Partes Review
• Filed: 2026-06-04
• Status: Pending - The petition has been filed and the Patent Owner has not yet submitted a preliminary response. The PTAB has not yet decided whether to institute the trial.
• Judge panel: Not yet assigned or publicly available at this early stage.
• Petition grounds: The petition grounds are not yet publicly available in detail via the USPTO PTAB E2E portal at this nascent stage of the proceeding.
• Institution decision: Not yet issued. The institution decision is typically due within three months of the Patent Owner's preliminary response or six months from the petition filing date if no preliminary response is filed, but no later than 12 months after the petition filing.
• Final Written Decision: Not applicable; no institution decision has been made.
• Settlement / termination: Not applicable; the proceeding is in its initial stage.
• Appeal: Not applicable; no Final Written Decision has been issued.
• Defensive value: This IPR indicates a challenge to the patent's validity, which could be a significant factor for any entity being asserted against. However, since it is newly filed, it provides no definitive outcome yet. Its existence means potential infringers could monitor its progress for a possible invalidation of claims, which would significantly weaken the patent owner's position.

Strategic summary

As of today, 2026-06-05, all claims of US Patent 11018678 remain UNTESTED by a Final Written Decision from the PTAB. IPR2026-00385, filed by Optiver US LLC et al., is the sole proceeding and is in its very nascent "Pending" stage. This means no claims have been canceled or sustained by the PTAB.

The estoppel landscape is currently undefined as there is no Final Written Decision. If IPR2026-00385 proceeds to a Final Written Decision, the petitioner (Optiver US LLC et al.) and their privies would be estopped from raising any ground raised or reasonably could have raised against the patent claims in future proceedings or civil actions, per 35 U.S.C. § 315(e)(2). However, for other potential defendants, all prior-art grounds remain available for challenge.

There is no discernible pattern signal yet, as this is the first recorded IPR against the patent. The petitioner, Optiver US LLC, is known to be involved in high-frequency trading, which aligns with the patent's claimed use in high-frequency trading (HFT).

Recommended next steps

For any entity currently facing assertion of US Patent 11018678, the primary next step would be to closely monitor the progress of IPR2026-00385. Key trial-stage milestones to watch for include:

• Patent Owner's Preliminary Response: Typically due within three months of the IPR petition filing (i.e., by approximately 2026-09-04).
• Institution Decision Deadline: The PTAB must decide whether to institute the IPR trial within three months of the Patent Owner's preliminary response, or by approximately 2026-12-04 if no preliminary response is filed.
• Final Written Decision Due Date: If instituted, the PTAB has a statutory 1-year trial deadline from the institution date to issue a Final Written Decision.

The absence of prior PTAB activity (until now) and prior litigation may suggest that the patent has not been extensively asserted in the past, or that previous assertions were resolved without public PTAB challenges or court filings.

Monitor the official record for IPR2026-00385 on the USPTO PTAB E2E system for updates regarding institution, judge panel assignment, and, eventually, a Final Written Decision.

https://ptab.uspto.gov/#/search/document?proceedingNumber=IPR2026-00385

Inventors

The sole named inventor for US Patent 11018678 is Nima Badizadegan. At the time of filing on July 23, 2020, Nima Badizadegan was an individual and the original assignee of the application, as indicated by the patent record stating "Application filed by Individual" and "Original Assignee: Individual."

Original assignee

The patent US11018678 was originally assigned to an individual (Nima Badizadegan) at the time of issue. However, shortly after its issue, the patent was assigned to HFT Solutions LLC.

HFT Solutions LLC is a wholly-owned subsidiary of Network-1 Technologies, Inc.. Network-1 Technologies, Inc. is a company whose primary line of business is "acquiring, developing, licensing, and monetizing intellectual property". HFT Solutions LLC itself was formed specifically to acquire and monetize a patent portfolio covering technologies related to high-frequency trading.

Based on available information, HFT Solutions LLC does not appear to ship products embodying the claims, but rather engages in licensing and assertion activities. The company is currently operating as an intellectual property monetization entity, with its parent company, Network-1 Technologies, Inc., being publicly traded on the NYSE American.

Assignment timeline

• 2022-03-29 (executed) / recorded 2022-04-04 — Reel 058098/0748
  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: BADIZADEGAN, NIMA
  • Assignee: HFT SOLUTIONS, LLC
  • Correspondent: NIMA BADIZADEGAN, 12 EAST 49TH ST, NEW YORK, NY 10017
  • Context: Transfer from individual inventor to an IP monetization entity.

Timeline diagram

timeline
    title Ownership of US11018678
    2019 : Priority Date
    2020 : Filed by Nima Badizadegan
    2021 : Issued to Nima Badizadegan
    2022 : Assigned to HFT Solutions LLC

NPE / troll-pattern signals

1. Shell-entity transfer — patent moved from an operating assignee to a licensing-only LLC.

   • Present. The patent was assigned from individual inventor Nima Badizadegan to HFT Solutions, LLC on 2022-03-29 (executed) / 2022-04-04 (recorded) [Reel 058098/0748]. HFT Solutions, LLC is a subsidiary of Network-1 Technologies, Inc., which is explicitly a company "engaged in acquiring, developing, licensing, and monetizing intellectual property". This indicates HFT Solutions, LLC is a licensing-only entity.

2. Known asserter in the chain — current or prior assignee matches a public NPE list.

   • Present. HFT Solutions, LLC is a wholly-owned subsidiary of Network-1 Technologies, Inc. (NYSE: NTIP). Network-1 Technologies, Inc. is a publicly known Non-Practicing Entity (NPE) that generates revenue through patent licensing and assertion. HFT Solutions, LLC has initiated patent litigation against companies like Optiver, Citadel Securities, and Jump Trading, referencing the HFT patent portfolio, of which US11018678 is a part.

3. Repeat correspondent across the chain — the same attorney or recording firm of record on multiple links in the chain, OR an attorney whose name has appeared as correspondent on a Unified Patents / RPX / Patent Progress NPE assertion list.

   • Unclear. There is only one recorded assignment for this patent (from Nima Badizadegan to HFT Solutions, LLC, Reel 058098/0748). The correspondent is NIMA BADIZADEGAN. With only one record, it is not possible to determine if this correspondent recurs across multiple patent chains or is otherwise associated with known NPE activities.

4. Cascading transfers — multiple consecutive assignments through chained LLCs in <24 months, especially when assignees share a correspondent address, the same correspondent attorney, or common principals.

   • Not present. Only one assignment is recorded for this patent.

5. Pre-litigation transfer — assignment dated within 6 months before the first infringement suit naming this patent.

   • Not present. The assignment to HFT Solutions, LLC was executed on 2022-03-29 and recorded on 2022-04-04 [Reel 058098/0748]. The earliest public record of litigation involving patents from the broader HFT patent portfolio (though not explicitly US11018678 as a named patent-in-suit in the cited articles) by HFT Solutions, LLC was in December 2024 against Citadel Securities and Jump Trading, and September 2025 against Optiver. The IPR against US11018678 was filed in June 2026. All these dates are more than 6 months after the assignment.

6. Bankruptcy fire-sale — original assignee filed Chapter 7 / 11 and patents sold in proceedings.

   • Not present. The patent was assigned from the individual inventor to HFT Solutions, LLC [Reel 058098/0748]. There is no indication of bankruptcy as part of this transfer.

7. Privateering — operating company transfers to an NPE that asserts on the operating company's behalf against competitors.

   • Unclear. While Network-1 Technologies, Inc. is an NPE and acquired the patent from the inventor (Nima Badizadegan), it is not evident from the provided information that Nima Badizadegan was operating a company that transferred the patent to Network-1 to assert against competitors. The transfer was from an "Individual."

8. Defensive aggregator (anti-NPE) — chain ends at RPX, Allied Security Trust (AST), LOT Network, Unified Patents, or Open Invention Network.

   • Not present. The chain ends with HFT Solutions, LLC, a subsidiary of Network-1 Technologies, Inc., which is an NPE.

Verdict

NPE — high confidence

The patent was transferred from the individual inventor to HFT Solutions, LLC, a subsidiary of Network-1 Technologies, Inc. (NTIP), on 2022-03-29 (executed) / 2022-04-04 (recorded) [Reel 058098/0748]. Network-1 Technologies, Inc. is a known Non-Practicing Entity (NPE) focused on intellectual property monetization, and HFT Solutions, LLC has initiated patent litigation as part of its business model. These facts represent strong signals consistent with an NPE assertion strategy.

USPTO Assignment Center search for US11018678

To identify the most relevant prior art for US Patent 11018678, I will search the USPTO Patent Public Search database. The USPTO provides tools for searching patents and their citations. Prior art includes any publicly available information before a patent's filing date that could bear on the patentability of its claims, particularly regarding novelty and non-obviousness.

I will focus on the "Cited By" references listed on the patent document itself, as these are the patents and publications considered by the examiner during prosecution and deemed most relevant to the patentability of US11018678.

I'm unable to directly access and parse the USPTO database for cited prior art patents as I do not have direct, real-time access to the full functionality of the USPTO's Patent Public Search tool or its enriched citations API. However, I can explain how to find this information if you were to perform the search yourself.

To find the most relevant prior art for US patent 11018678, you would typically:

1. Go to the USPTO Patent Public Search website. (e.g., https://ppubs.uspto.gov/pubwebapp/static/pages/landing.html or https://patents.google.com/patent/US11018678/en).
2. Search for "US11018678" in the patent number field.
3. Navigate to the "Citations" or "Cited By" section. This section lists all the prior art documents that the patent examiner and/or applicant cited during the patent's prosecution.
4. For each cited reference, you would then look up its full details.

The "Definitions" section of the patent text provides some insight into the technological problem the invention aims to solve: synchronizing receiving and transmitting clock signals within an FPGA without introducing unnecessary delay, especially in applications like high-frequency trading. This context would be crucial when evaluating the relevance of any cited prior art.

If I had access to the list of cited prior art, I would then detail for each:

• Full Citation: The complete patent number (e.g., USX,XXX,XXX B1 or US X,XXX,XXX A) or publication details.
• Publication/Filing Date: The relevant dates for assessing prior art status.
• Brief Description: A summary of what the prior art discloses.
• Potential Anticipation (35 U.S.C. § 102): An analysis of which claim(s) of US11018678 could potentially be anticipated by the prior art, meaning the prior art discloses every limitation of the claim.

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 11018678

This analysis considers the obviousness of US Patent 11018678 by combining elements from the prior art references and background information explicitly disclosed within the patent text itself. The patent identifies a significant technological problem: the latency introduced by conventional clock domain crossing (CDC) circuits used to synchronize receiver and transmitter clock signals within a Field Programmable Gate Array (FPGA). [Definitions: One technological problem with FPGAs is that there is a need to synchronize receiving side and transmitting side clock signals within the FPGA.; Description, Conventional FPGA: a significant drawback of the clock domain crossing circuit 112 is that it adds latency... such that it slows the effective processing speed of FPGA 100.] The stated objective of the invention is to address this challenge without introducing unnecessary processing delay. [Definitions: An object of the present invention is to address technological challenges that currently exist in phase matching receiver side and transmitter side clocks of a FPGA without introducing unnecessary delay in processing.]

Prior Art References Disclosed in the Patent:

The patent explicitly describes or references the following as prior art or common general knowledge:

1. Conventional Field Programmable Gate Array (FPGA) Architecture (FIGS. 1, 1A, 1B, 1C): This includes:
   • FPGA Core 106 and FPGA Transceiver Banks 102. [Description, Conventional FPGA: FIG. 1 illustrates an exemplary schematic of a FPGA 100.]
   • Deserializer 104 and Serializer 110 (SERDES circuits). [Description, Conventional FPGA: An exemplary transceiver (including deserializer 104′ and serializer 110′) suitable for use in FPGA 100 is shown in FIG. 1A.]
   • Transceiver PLL 108 used by the serializer to generate a fast clock from a reference clock. [Description, Conventional FPGA: the serializer 110 (e.g., the transmitter) typically runs off a fast clock generated... by the transceiver phase-locked loop 108 within the transceiver bank 102 from a reference clock signal received by oscillator or clock generator 122.]
   • Receiver clock (RXCLOCK) generated by a clock and data recovery (CDR) circuit from the incoming data stream, and a transmitter clock (TXCLOCK) generated by the transceiver PLL. [Description, Conventional FPGA: the receiver clock domain is typically generated by a clock and data recovery (CDR) circuit from the incoming data stream. The transmitter clock is typically generated by the transceiver phase-locked loop 108.]
   • The use of Clock Domain Crossing (CDC) circuits 112 (e.g., asynchronous FIFO, asynchronous gearbox, mesochronous clock crossing circuit) for phase matching or synchronizing these different clock domains. [Description, Conventional FPGA: phase matching or synchronizing is provided using the clock domain crossing circuit 112 that adjusts the phases of the two clock domains. The clock domain crossing circuit 112 may be an asynchronous FIFO or an asynchronous gearbox, to name a few.]
   • The patent explicitly states the "significant drawback" of CDC circuits: "it adds latency related to the phase difference between the clocks plus the latency of the synchronizers used, and does not perform any computation, such that it slows the effective processing speed of FPGA 100." [Description, Conventional FPGA].
2. Synchronous Ethernet Systems: These systems were designed for synchronizing a transmitter to a receiver. However, the patent explicitly notes their inadequacy for the present invention's problem: "phase alignment in synchronous Ethernet is not necessary, synchronous Ethernet FPGA systems usually do not phase-align the receiver and transmitter sides of a link." [Definitions]. Furthermore, their internal PLLs are "configured to measure accurately only the frequency but does not have to measure the phase of the two clocks accurately." [Definitions].
3. General Electronic Components and Techniques:
   • Phase-Locked Loops (PLLs) and adjustable oscillators (voltage-controlled oscillators (VCOs), numerically/digitally-controlled oscillators (DCOs), ring oscillators, varactor-tuned oscillators, digital delay lines, voltage-controlled delay elements). Specific commercial examples are mentioned (e.g., Si550 from Silicon Labs, SY89295U from Micrel, HMC910 from Analog Devices). [Description, FIG. 4A: The adjustable oscillator 4200 may be implemented in a variety of ways...Other types of oscillators may be used including negative-resistance oscillators, Clapp oscillators, Colpitts oscillators, ring oscillators, and varactor-tuned oscillators, to name a few.]
   • Phase Detectors (PDs) for measuring phase differences (e.g., illustrated in FIGS. 8A-8D). [Description, FIGS. 8A-C are exemplary block diagram of a phase detector suitable for use in the field programmable gate array systems of FIGS. 3A-3F, 4A-4C and 5A-5F in accordance with an exemplary embodiment of the present invention.]
   • Control loops, controllers, and loop filters (e.g., first, second, third, fourth order filters with derivative components). [Description, FIG. 3A: Any loop filter order may be used in the controller 3202... a second-order loop filter may be used... a third-order filter may be used... a first-order filter is also an option...]
   • Zero-Delay Buffer (ZDB) PLLs (e.g., 4208a, 4208b). [Description, FIG. 4A: The FPGA 4100 includes zero-delay buffer PLLS 4208a, 4208b.]
   • High-frequency trading (HFT) as an application where rapid FPGA processing is desired. [Definitions: FPGAs are used in the financial industry in high frequency trading where the rapid processing of the FPGA is desired.]

A Person Having Ordinary Skill in the Art (POSITA) in FPGA design would be familiar with these conventional architectures, the inherent latency issues of CDC circuits, and the fundamental operation of PLLs, phase detectors, and control systems for clock synchronization.

Obviousness Analysis of Representative Claims:

Claim 1: Field Programmable Gate Array System (Internal PLL)

• Claimed Elements (Summary): An FPGA system with internal deserializer and serializer, computational circuitry, an internal phase detector comparing receiver-side and transmitter-side clock signals, and an internal phase controller that provides adjustment information to an internal adjustable PLL to adjust the phase of the serializer's clock.
• Prior Art Baseline: The conventional FPGA (FIG. 1, 1A, 1B) teaches an FPGA with deserializers (104) and serializers (110) operating with different clock domains, and the use of a transceiver PLL (108) to generate the serializer's fast clock. Crucially, it also teaches the problematic use of a CDC circuit (112) to synchronize these domains, with the explicit drawback of added latency. [Description, Conventional FPGA: a significant drawback of the clock domain crossing circuit 112 is that it adds latency...].
• Differences from Prior Art Baseline: The core difference is the replacement of the latency-inducing CDC circuit with an active feedback loop internal to the FPGA that precisely aligns the phases of the RXCLOCK and TXCLOCK using an internal phase detector, controller, and an adjustable PLL.
• Motivation to Combine: A POSITA, recognizing the explicit and significant latency drawback of CDC circuits in conventional FPGAs as highlighted by the patent, would be strongly motivated to find a solution that reduces or eliminates this latency. PLLs are a well-known means for clock synchronization and phase locking. The conventional FPGA already incorporates a transceiver PLL (108) for the serializer. Integrating an internal phase detector (as generically illustrated in FIGS. 8A-8D, which the patent describes as "suitable for use in the field programmable gate array systems") to compare the RXCLOCK and TXCLOCK, and an internal phase controller to feed adjustment information to an adjustable internal PLL (e.g., an adjustable transceiver PLL 3108 or a PLL with phase adjustment 3300 located within the FPGA core, as shown in FIG. 3A/3B), would be an obvious approach to actively align the phases and thereby avoid the latency of CDC circuits. The patent itself suggests that "PLL with phase adjustment 3300 may be located inside the FPGA 3100 fabric with adjustable feedback dividers, which in turn adjust the frequency of the PLL" or "may comprise a phase adjuster on the output of the loop, which adjusts the phase of the PLL directly." [Description, FIG. 3A]. This direct teaching, along with the explicit problem statement, makes the combination obvious. The synchronous Ethernet systems, explicitly noted as not accurately phase-aligning clocks, further emphasizes the motivation to devise a system that does achieve accurate phase alignment.

Claim 11: Field Programmable Gate Array System (External Phase Detector)

• Claimed Elements (Summary): An FPGA system similar to Claim 1, but with the phase detector located outside the FPGA. The FPGA provides output pins for the receiver-side and transmitter-side clock signals to the external phase detector. An internal phase controller receives the phase difference from the external detector and provides adjustment information to an external adjustable oscillator, which then generates the first wire rate clock signal for the serializer. The FPGA includes zero-delay buffer PLLs.
• Prior Art Baseline: The conventional FPGA (FIG. 1) provides the basic deserializer, serializer, and computational logic. The general knowledge of phase detectors, controllers, and adjustable oscillators is well established. The patent itself introduces the concept of an external phase detector and external adjustable oscillator in FIG. 4A. [Description, FIG. 4A: One difference between the system of FIG. 4A and the system of FIGS. 3A and 3B is that the phase detector 4206 is off-chip, i.e., not of the FPGA 4100.] It also teaches the use of zero-delay buffer PLLs (4208a, 4208b) to accurately transmit clock signals off-chip. [Description, FIG. 4A: The FPGA 4100 includes zero-delay buffer PLLS 4208a, 4208b.]
• Differences from Prior Art Baseline: The primary difference from Claim 1 is the placement of the phase detector and the adjustable oscillator outside the FPGA, with ZDBs facilitating accurate off-chip clock transmission.
• Motivation to Combine: A POSITA, motivated to achieve the same low-latency phase alignment as in Claim 1, might choose an external implementation for the phase detector and/or adjustable oscillator based on design considerations such as: if a higher-precision phase detector is only available off-chip, or if a centralized external clock source is preferred for managing multiple FPGAs or for specific noise/jitter performance requirements. The patent itself presents this configuration (FIG. 4A) as an alternative embodiment, indicating it is an obvious design choice for a POSITA. The use of zero-delay buffers (ZDBs) to transmit clock signals off-chip for accurate phase comparison without introducing significant deterministic delay is a known technique for managing clock integrity in system-level designs. The patent discusses "Any length mismatch between reference traces... may introduce a deterministic phase error" when dealing with external components, indicating these are known engineering challenges addressed by using appropriate components like ZDBs. [Description, FIG. 4A].

Claim 18: Method for Processing Data (Internal Phase Detector)

• Claimed Elements (Summary): A method for processing market data into order entry data using an FPGA system. The steps include receiving market data and a first clock, deserializing, generating a first receiver side clock, performing operations (a trading algorithm), generating an interim transmitter side clock, an internal phase detector comparing the receiver and interim transmitter clocks, an internal phase controller generating adjustment information, adjusting an internal adjustable oscillator to generate a wire rate clock, serializing, and transmitting order entry data.
• Prior Art Baseline: The method steps directly correspond to the operational flow of the system described in Claim 1. The patent explicitly states that "FPGAs are used in the financial industry in high frequency trading where the rapid processing of the FPGA is desired." [Definitions]. It also defines a "trading algorithm" as comprising parsing market data, performing mathematical operations, and generating order packets. [Definitions: the trading algorithm includes the steps of: (a) parsing market data; (b) performing mathematical operations at a portion of the market data; and (c) generating order packets using at least an output of (b).]
• Differences from Prior Art Baseline: The specific application of the phase-aligned FPGA system to processing "market data" into "order entry data" via a "trading algorithm."
• Motivation to Combine: Given the patent's explicit identification of HFT as an application for FPGAs where "rapid processing" is "desired," and the critical need to reduce latency in such applications, it would be an obvious application for a POSITA to employ the low-latency phase alignment system of Claim 1 (or its methodological equivalent) in an HFT context. The steps of a trading algorithm are well-known in the HFT domain. Therefore, applying the described latency-minimizing clock synchronization method to a known latency-critical application for FPGAs is an obvious combination.

Claim 29: Field Programmable Gate Array System (First Clock for Second Pin)

• Claimed Elements (Summary): An FPGA system similar to Claim 1, where the first reference clock pin receives a first clock signal, and the second reference clock pin also receives the same first clock signal. The system still includes the internal phase detector, controller, and adjustable PLL for phase alignment.
• Prior Art Baseline: The conventional FPGA (FIG. 1) shows an Oscillator or Clock Generator 122 providing a REFERENCE CLOCK signal, which is then fed to both the deserializer 104 and the transceiver PLL 108 (which ultimately influences the serializer 110). [Description, Conventional FPGA: a REFERENCE CLOCK signal is provided, by Oscillator or Clock Generator 122, to both the deserializer 104 and the serializer 110. The REFERENCE CLOCK signal is received by the serializer 110 via the transceiver PLL 108.]
• Differences from Prior Art Baseline: The explicit statement that the second reference clock pin receives the same first clock signal as the first reference clock pin, while retaining the internal phase alignment mechanism.
• Motivation to Combine: A POSITA would be motivated to simplify the clocking architecture of an FPGA system by utilizing a single, common external reference clock for both receive and transmit paths. This is a common design practice to ensure frequency coherence and simplify clock distribution. Even with a common reference clock, internal delays in the deserializer, computational logic, and serializer paths will inevitably lead to phase differences between the RXCLOCK and TXCLOCK. Therefore, it would be obvious for a POSITA to combine this simplified common reference clock input scheme (already present conceptually in FIG. 1) with the internal active phase alignment mechanism of Claim 1 to compensate for these internal phase discrepancies and maintain optimal low-latency operation.

Conclusion

The claims of US Patent 11018678 would likely be considered obvious under 35 U.S.C. § 103 given the explicit problem statement and the disclosed prior art within the patent itself. A POSITA, motivated to overcome the known latency drawbacks of conventional CDC circuits in FPGAs, would have reasonably combined known components such as phase detectors, control loops, and adjustable PLLs/oscillators into a feedback system for active phase alignment. The patent explicitly provides the problem, the conventional (problematic) solutions, and the fundamental building blocks for the claimed solution, and even describes various embodiments (internal vs. external components, common reference clocks) as alternative design choices. The application of this latency-reducing technology to high-frequency trading is also explicitly taught as a desirable use case for FPGAs.