Prior art

Most Relevant Prior Art for US Patent 10944400

US Patent 10944400's earliest priority date is June 2, 2006. Therefore, the following analysis focuses on prior art citations with a priority or publication date predating June 2, 2006, that appear most relevant to the patent's independent claims (Claims 1, 11, and 20). The core innovation of US10944400 is applying a first on-die termination impedance during write-data reception and a second, different on-die termination impedance after write-data reception, controlled by commands that cause control values to be stored in registers within the DRAM.

Below are selected prior art references from the patent's citation list that potentially anticipate aspects of US10944400, along with their details and potential anticipatory relevance.

1. US20050007835A1: Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods

• Full Citation: US20050007835A1, "Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods," inventors Lee, Kee-Hoon; Park, Youn-Sik, published January 13, 2005.
• Publication/Filing Date: Priority Date: July 20, 2001; Publication Date: January 13, 2005.
• Brief Description: This patent application describes integrated circuit memory devices (including DRAM) that can receive and implement "selective mode register set commands." These commands allow a memory controller to configure various operational aspects of the memory device by storing control values in mode registers. Such configurations could include termination settings.
• Potential Anticipation of Claims: This reference is highly relevant to Claims 1, 11, and 20 of US10944400. It teaches the fundamental mechanism of a memory controller (an integrated circuit device) transmitting commands to a DRAM to store control values (via mode register set commands) within registers of the DRAM. These control values can then "specify" various operations, which could inherently include termination characteristics. While it may not explicitly detail the two specific termination phases (during and after write data reception) or the precise impedance values, it anticipates the architectural and methodological aspects of using commands and registers to programably control DRAM functionality, including likely termination.

2. US6894691B2: Dynamic switching of parallel termination for power management with DDR memory

• Full Citation: US6894691B2, "Dynamic switching of parallel termination for power management with DDR memory," inventors Tsuchida, Hiroyuki, published May 17, 2005.
• Publication/Filing Date: Priority Date: May 1, 2002; Publication Date: May 17, 2005.
• Brief Description: This patent describes techniques for dynamically switching parallel termination in DDR memory systems, primarily for power management. The "dynamic switching" implies changing the termination characteristics based on the operational state of the memory, which suggests the application of different termination loads at different times.
• Potential Anticipation of Claims: This patent is relevant to Claims 1, 11, and 20 due to its disclosure of "dynamic switching of parallel termination" in a memory environment. This directly addresses the concept of changing termination impedance during operation. While focused on power management, the principle of an integrated circuit device (e.g., memory controller) causing a memory device to dynamically apply different termination values based on operating conditions is present. It potentially anticipates the idea of applying different termination values, though it may not explicitly detail the "during write-data reception" and "after write-data reception" specific intervals or control via dedicated control values in registers as precisely as US10944400.

3. US20040098528A1: Active termination control though on module register

• Full Citation: US20040098528A1, "Active termination control though on module register," inventors Gillingham, Peter B., published May 20, 2004.
• Publication/Filing Date: Priority Date: November 20, 2002; Publication Date: May 20, 2004.
• Brief Description: This reference teaches the control of active termination (which often refers to on-die termination) using a register located on a memory module. This implies that external control signals or commands can program a register to configure the termination behavior of memory devices on the module.
• Potential Anticipation of Claims: This patent application is highly relevant to Claims 1, 11, and 20. It directly discloses "active termination control through on module register," which directly aligns with the elements of US10944400 relating to an integrated circuit device transmitting commands to store control values in registers for termination. Similar to US20050007835A1, the key difference might be the explicit two-phase termination for write data reception, but the core control mechanism for setting termination via registers is present.

4. US20060106951A1: Command controlling different operations in different chips

• Full Citation: US20060106951A1, "Command controlling different operations in different chips," inventors Bains, Kuljit S.; Janzen, Jeffery; Poulton, John W.; Smith, Kevin M., published May 18, 2006.
• Publication/Filing Date: Priority Date: November 18, 2004; Publication Date: May 18, 2006.
• Brief Description: This patent application describes a system where a command issued to multiple integrated circuits (chips) can cause them to perform different operations. This highlights a mechanism for differentiated control based on a command, which could be applied to selective termination.
• Potential Anticipation of Claims: This reference is relevant to Claims 1, 11, and 20 for its disclosure of command-based control leading to "different operations" in different chips. While it might not explicitly detail on-die termination or the specific "during/after write data reception" phases, it teaches the fundamental concept of an integrated circuit (controller) issuing commands that result in varied functionality across connected devices. This provides a foundational mechanism for a controller to instruct a DRAM to perform different termination states.

5. US6781405B2: Adaptive signal termination

• Full Citation: US6781405B2, "Adaptive signal termination," inventors Garlepp, Bruno W.; Kizer, Jay D.; Zerbe, Jared L., published August 24, 2004.
• Publication/Filing Date: Priority Date: April 29, 2002; Publication Date: August 24, 2004.
• Brief Description: This patent introduces adaptive signal termination techniques, where the termination impedance can be adjusted or adapted based on various system conditions. "Adaptive" implies dynamic changes to optimize signal integrity.
• Potential Anticipation of Claims: This patent is relevant to Claims 1, 11, and 20 as it broadly covers "adaptive signal termination." The adaptive nature suggests the use of different termination values based on operational needs, which is a precursor to the graduated termination in US10944400. While it may not explicitly detail the control via registers or the two specific phases during a write operation, it lays groundwork for dynamically altering termination values in a system.