Obviousness

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 10944400

The independent claims of US Patent 10944400 (Claims 1, 11, and 20) describe an integrated circuit device (e.g., a memory controller) and a corresponding method. The core invention lies in transmitting commands to a Dynamic Random Access Memory (DRAM) component to configure it to apply a first on-die termination (ODT) impedance during a write-data reception interval and a second, different ODT impedance after the write-data reception interval has transpired. The first impedance is typically higher (lower load, "soft termination") than the second impedance (higher load, "hard termination") as per dependent claim 10 and the patent's description.

A person having ordinary skill in the art (PHOSITA) in high-speed signaling systems and memory design would have found the claimed invention obvious due to the combination of known prior art references, driven by the motivation to improve signal integrity and minimize reflections in high-speed memory interfaces.

Combination of Prior Art References

The following combination of prior art references would render the claims of US10944400 obvious:

1. US7138823B2 (Micron Technology, Inc.): This patent, titled "Apparatus and method for independent control of on-die termination for output buffers of a memory device," teaches a memory device that includes a control circuit adapted to receive mode register set commands to program registers to set the ODT impedance for its output buffers. This reference thus provides the mechanism for a DRAM to have registers to store control values for termination, and for an integrated circuit device (memory controller) to transmit commands to instruct the DRAM to store these ODT values.
2. US7439760B2 (Rambus Inc.): Titled "Configurable on-die termination," this patent describes an integrated circuit device with a data interface and at least one termination circuit. This termination circuit includes a plurality of termination elements that can be selectively coupled to the data interface. It also features a configuration circuit to store a configuration value that determines which of these termination elements are coupled. This reference teaches the concept of having multiple, selectable termination options with different impedance values available within the DRAM.
3. TWI763803B: This patent, titled "Method of controlling on-die termination and system performing the same," explicitly discloses that "during a write operation, the resistance value of the in-die termination circuit of the write target memory bank is changed from a first resistance value to a second resistance value different from the first resistance value value". This is highly significant as it directly teaches the concept of dynamically changing the termination impedance for a target memory device during a write operation from a first value to a second, different value.

Motivation to Combine and Obviousness Analysis

A PHOSITA, faced with the challenge of optimizing signal integrity and reflection management in high-speed memory systems, would have been motivated to combine the teachings of these references for the following reasons:

1. Flexible and Programmable ODT: US7138823B2 provides a well-known method for programming ODT impedance values into registers within a DRAM via mode register set commands, enabling external control over termination characteristics. US7439760B2 further demonstrates the capability of having multiple, distinct termination elements that can be selected by a stored configuration value. A PHOSITA would find it obvious to combine these to allow a memory controller to program specific values into DRAM registers to select from a plurality of available termination impedances, thereby achieving greater flexibility and optimization than a single, fixed ODT.
2. Dynamic ODT for Write Operations: The problem of signal reflections and impedance discontinuities during high-speed memory operations, particularly writes, was well-recognized prior to US10944400's priority date (June 2, 2006). TWI763803B directly addresses this by teaching the dynamic alteration of termination resistance values during a write operation for the target memory bank. This explicit teaching would motivate a PHOSITA to implement such dynamic changes to improve signal integrity throughout the entire write transaction.
3. Application of Different Terminations During and After Write Data Reception: The general understanding of on-die termination in DDR SDRAM systems, as evidenced by general technical literature, indicates that ODT is dynamically controlled and asserted "at the appropriate times" during read and write operations to manage incoming signals. Furthermore, the prior art recognized that ODT behavior can change during a transaction; for instance, in read operations, ODT might be disabled during data output and then briefly enabled after the data burst to absorb residual reflections. Given TWI763803B's teaching of changing ODT resistance values "during a write operation", a PHOSITA would readily appreciate the benefit of applying a first termination impedance (e.g., a "soft" termination for less attenuation) during the critical write data reception interval and then switching to a second, different termination impedance (e.g., a "hard" termination for stronger reflection cancellation) after the data has been received to optimize the bus characteristics. This temporal adjustment of ODT values during different phases of a single write transaction would be a logical and predictable optimization to further enhance signal integrity, building on the concepts of programmable and dynamically changeable ODT already present in the art. The selection of specific impedance values (e.g., the first being higher than the second as in claim 10) would be an engineering design choice made by a PHOSITA to achieve optimal signal characteristics for the different phases of a write operation.

Therefore, the combination of programmable ODT from US7138823B2 and US7439760B2, coupled with the explicit teaching of dynamically changing ODT during a write operation from TWI763803B, and motivated by the well-understood need for improved signal integrity in high-speed memory systems, would have rendered the invention of US10944400 obvious to a PHOSITA.