Prior art — US Patent 10937880

Here is an analysis of the most relevant prior art for US Patent 10,937,880, focusing on patent citations with priority dates before August 12, 2002, which is the priority date of US10937880. The information is drawn from the provided patent text and the "Prior art citations" section of the Google Patents page for US10937880.

Key Claims of US10937880 for Anticipation Analysis:

Claim 1 (Electrical device): An electrical device comprising a semiconductor, a metal, and an interface layer between them. The interface layer is configured to depin the Fermi level of the semiconductor (by terminating dangling bonds and reducing MIGS by displacement) and allow current flow. The specific contact resistance is less than approximately 10 Ω-μm².
Claim 11 (Electrical device): An electrical device with a silicon-based semiconductor, a conductor, and an interface layer. The interface layer causes the Fermi level of the conductor to align with the conduction band, valence band, or be independent of the Fermi level of the semiconductor. The specific contact resistance is less than or equal to approximately 10 Ω-μm². The interface layer is formed by heating the semiconductor in a nitrogenous material within a vacuum chamber.
Claim 17 (Method): A method for creating an electrical junction that depins the Fermi level of a semiconductor by placing an interface layer between the semiconductor and a conductor. The interface layer (i) is thick enough to reduce effects of MIGS and (ii) passivates the surface. Its thickness is chosen to provide a minimum (or near minimum) specific contact resistance. The interface layer includes a passivating material (e.g., nitride, oxide, hydride).

Most Relevant Prior Art (Anticipating under 35 U.S.C. § 102)

The following prior art patents are identified as highly relevant due to their disclosure of interface layers or thin dielectric films for modifying Schottky barrier heights, with priority dates predating US10937880's priority date of August 12, 2002.

1. US 6,433,385 B1

Full Citation: US 6,433,385 B1 to Ramdani et al., titled "Device and method for reducing Schottky barrier height in a metal-semiconductor contact"
Publication Date: August 13, 2002
Filing Date: April 20, 2001 (Predates US10937880's priority date)
Brief Description: This patent describes a semiconductor device that includes a metal contact on a semiconductor surface with an intermediate layer between them. The intermediate layer consists of a silicon compound with a thickness and composition sufficient to reduce the Schottky barrier height between the metal and the semiconductor.
Potential Anticipation (35 U.S.C. § 102):
- Claim 1: Potentially anticipates the broad concept of an electrical device with a metal, semiconductor, and an intermediate layer to reduce Schottky barrier height. However, it does not explicitly disclose "depinning the Fermi level" as defined by US10937880 (i.e., by terminating dangling bonds and reducing MIGS by displacement), nor does it specify the target specific contact resistance of less than approximately 10 Ω-μm².
- Claim 11: The patent describes an intermediate layer affecting electrical properties between a conductor and a semiconductor. However, it lacks specific disclosures regarding the Fermi level aligning with the conduction/valence band or being independent, the precise low specific contact resistance values, and the method of forming the layer by heating in a nitrogenous material within a vacuum chamber.
- Claim 17: Potentially anticipates the general method of using an intermediate layer to reduce Schottky barrier height. However, it does not explicitly teach the specific combined mechanisms of reducing MIGS through displacement and full surface passivation for depinning the Fermi level, nor the optimization for achieving a minimum specific contact resistance.

2. US 6,166,405 A

Full Citation: US 6,166,405 A to Lin et al., titled "High-performance Schottky source/drain MOSFET and method of manufacture"
Publication Date: December 26, 2000
Filing Date: October 8, 1998 (Predates US10937880's priority date)
Brief Description: This patent discloses a MOSFET with Schottky source/drain contacts, where a thin dielectric layer (e.g., nitride or oxide) is formed between the metal and the semiconductor to effectively lower the Schottky barrier height.
Potential Anticipation (35 U.S.C. § 102):
- Claim 1: Highly relevant, describing an electrical device (MOSFET) with a metal, semiconductor, and a thin dielectric interface layer (nitride/oxide) to lower Schottky barrier height and permit current flow. The core structural elements and the function of modifying barrier height with an interface layer are present. However, similar to US6433385B1, it lacks the explicit definition of "depinning the Fermi level" (including MIGS reduction by displacement) and the specific contact resistance range of less than 10 Ω-μm².
- Claim 11: Describes using a thin dielectric layer (like nitride) as an interface between a conductor and a silicon-based semiconductor to affect electrical properties. It does not explicitly detail the Fermi level alignment conditions or the specific method of formation involving heating in a nitrogenous material under vacuum as broadly claimed in US10937880.
- Claim 17: The method of forming a thin dielectric layer (nitride/oxide) to lower barrier height is disclosed. The explicit combined depinning mechanisms (passivation + MIGS reduction by displacement) and the optimization for minimum specific contact resistance are not explicitly described or claimed.

3. US 6,081,014 A

Full Citation: US 6,081,014 A to Furukawa et al., titled "Device and method for forming semiconductor device contact having reduced Schottky barrier height"
Publication Date: June 27, 2000
Filing Date: October 26, 1999 (Predates US10937880's priority date)
Brief Description: This patent details a semiconductor device contact that includes a heavily doped semiconductor region and a Schottky contact. An insulating layer (formed by nitridation or oxidation of the semiconductor surface) with a controlled thickness is placed between the metal and the heavily doped semiconductor layer to reduce the Schottky barrier height.
Potential Anticipation (35 U.S.C. § 102):
- Claim 1: Presents an electrical device with a metal, semiconductor, and an insulating layer (nitride/oxide) to reduce barrier height. The use of nitridation/oxidation is aligned with US10937880. However, it relies on heavily doped semiconductors and does not explicitly teach "depinning the Fermi level" as defined in 10937880 (passivation and MIGS reduction by displacement) or the specific contact resistance.
- Claim 11: Mentions nitridation/oxidation for forming the insulating layer, which aligns with the nitrogenous material aspect. However, it relies on heavy doping and does not broadly claim specific Fermi level alignments or the precise vacuum conditions for layer formation in a manner that fully anticipates Claim 11.
- Claim 17: The method involves forming an insulating layer by nitridation or oxidation to reduce barrier height. This overlaps with material types and general function. However, the explicit requirements of (i) reducing MIGS by thickness and (ii) passivating the surface for depinning the Fermi level, and specifically selecting thickness for minimum specific contact resistance, distinguish US10937880.

4. US 5,883,401 A

Full Citation: US 5,883,401 A to Lin et al., titled "Schottky source/drain MOSFET with low Schottky barrier height"
Publication Date: March 16, 1999
Filing Date: May 29, 1997 (Predates US10937880's priority date)
Brief Description: This patent describes a MOSFET where low Schottky barrier height for the source/drain contacts is achieved by forming a thin insulating film (e.g., SiO2, Si3N4) between the metal and the semiconductor.
Potential Anticipation (35 U.S.C. § 102):
- Claim 1: Very similar to US6166405A. Discloses a MOSFET with metal, semiconductor, and a "thin insulating film" (SiO2, Si3N4) to achieve low Schottky barrier height. This anticipates the structural elements and the function of lowering barrier height using an interface layer. It lacks explicit disclosure of "depinning the Fermi level" as defined by US10937880 and the specific contact resistance range.
- Claim 11: Mentions Si3N4 (a nitrogenous material) as a thin insulating film. Similar to US6166405A, it does not explicitly detail Fermi level alignment conditions or the specific vacuum formation method.
- Claim 17: The method of forming a thin insulating film of SiO2 or Si3N4 to lower barrier height is disclosed. The explicit combined depinning mechanisms (passivation + MIGS reduction by displacement) and the optimization for achieving minimum specific contact resistance are not explicitly present as claimed in US10937880.

Other Patent Citations (Pre-August 12, 2002 Priority Date)

The following patents are also cited but are generally less directly anticipatory of the core claims of US10937880 due to differing mechanisms, materials, or scope.

US 6,284,646 B1 (Sep 4, 2001; Filed: Jun 30, 2000): Describes forming self-assembled monolayers on hydrogen-terminated silicon, related to surface preparation but not the specific depinning and contact resistance aspects of US10937880.
US 6,107,659 A (Aug 22, 2000; Filed: Jun 10, 1999): Focuses on optimizing Schottky barrier height by selecting different metals or doping, not through an interface layer that specifically depins the Fermi level by passivation and MIGS reduction.
US 6,057,582 A (May 2, 2000; Filed: Jun 11, 1998): Focuses on reducing parasitic resistance using doping, not an interface layer for Fermi level depinning.
US 5,977,583 A (Nov 2, 1999; Filed: May 15, 1998): Discusses silicide-free Schottky source/drain regions using direct metal-silicon contact, without the specific interface layer to depin the Fermi level as in US10937880.
US 5,844,274 A (Dec 1, 1998; Filed: Oct 28, 1997): Relies on metal silicides for Schottky contacts, which US10937880 seeks to avoid or provide an alternative to due to Fermi level pinning.
US 5,729,035 A (Mar 17, 1998; Filed: Jul 26, 1996): Similar to the other Schottky MOSFET patents, describes a thin dielectric layer to reduce barrier height, but without the explicit "depinning the Fermi level" definition or minimum specific contact resistance claims of US10937880.
US 5,693,963 A (Dec 2, 1997; Filed: Jan 12, 1996): Relies on metal silicides.
US 5,625,219 A (Apr 29, 1997; Filed: Aug 15, 1995): Focuses on low work function metals and doping, not an intermediate interface layer for Fermi level depinning via passivation and MIGS reduction.
US 5,523,604 A (Jun 4, 1996; Filed: Oct 21, 1994): General Schottky MOSFET, no specific interface layer for Fermi level depinning.
US 5,471,066 A (Nov 28, 1995; Filed: Mar 28, 1994): Relies on metal silicides.
US 5,103,280 A (Apr 7, 1992; Filed: Sep 25, 1990): Focuses on silicided gates, not the source/drain interface layer for depinning.
US 4,998,144 A (Mar 5, 1991; Filed: Dec 21, 1989): Describes a Schottky barrier diode with a guard ring, not the interface layer mechanism for Fermi level depinning.
US 4,975,760 A (Dec 4, 1990; Filed: May 19, 1989): Describes a trench gate structure, not relevant to the core innovation of US10937880.
US 4,933,737 A (Jun 12, 1990; Filed: Jun 30, 1989): General Schottky FET, no specific interface layer for Fermi level depinning.
US 4,751,563 A (Jun 14, 1988; Filed: Apr 28, 1987): Relies on silicided source and drain.
US 4,723,149 A (Feb 2, 1988; Filed: Jul 28, 1986): General Schottky FET, no specific interface layer for Fermi level depinning.
US 4,698,656 A (Oct 6, 1987; Filed: Mar 28, 1986): Describes a Schottky diode with a guard ring.
US 4,524,419 A (Jun 18, 1985; Filed: Jul 3, 1984): Describes a Schottky diode on amorphous silicon. US10937880 specifies silicon-based semiconductors which typically refers to crystalline silicon or its alloys.
US 4,486,766 A (Dec 4, 1984; Filed: Oct 28, 1982): Describes a silicide Schottky contact.
US 4,460,914 A (Jul 17, 1984; Filed: Dec 29, 1981): Describes a Schottky diode on amorphous semiconductor.
US 4,456,926 A (Jun 26, 1984; Filed: Oct 29, 1981): General Schottky diode fabrication.
US 4,384,299 A (May 17, 1983; Filed: Feb 24, 1981): Describes a Schottky diode with a metal silicide electrode.
US 4,261,001 A (Apr 7, 1981; Filed: Jun 28, 1979): Describes a Schottky diode utilizing silicide.
US 4,104,764 A (Aug 8, 1978; Filed: Oct 28, 1977): Schottky gate FET device.
US 4,029,471 A (Jun 14, 1977; Filed: Dec 29, 1975): Schottky barrier type field effect transistor.
US 4,000,508 A (Dec 27, 1976; Filed: Jan 28, 1976): Gallium arsenide Schottky barrier FETs (different semiconductor material).
US 3,701,955 A (Oct 31, 1972; Filed: Apr 20, 1971): Schottky barrier field effect transistor.
US 3,678,358 A (Jul 18, 1972; Filed: Dec 28, 1970): Schottky barrier type field effect transistor.
US 3,490,013 A (Jan 13, 1970; Filed: Oct 26, 1966): Insulated gate field effect transistor.
US 3,401,314 A (Sep 10, 1968; Filed: Aug 15, 1966): Schottky barrier diode.
US 3,012,204 A (Dec 5, 1961; Filed: Feb 10, 1958): General semiconductor devices.

Non-Patent Literature

J. Tersoff, “Schottky Barrier Heights and the Continuum of Gap States,” Phys. Rev. Lett. 52 (6), Feb. 6, 1984.
- Description: This scientific paper is fundamental to the understanding of Schottky barrier formation, proposing Metal-Induced Gap States (MIGS) as a key mechanism for Fermi level pinning.
- Potential Anticipation (35 U.S.C. § 102): This reference explains the scientific problem (Fermi level pinning due to MIGS) that US10937880 seeks to overcome. It does not, however, disclose the specific technical solution of using an engineered interface layer to depin the Fermi level, passivate dangling bonds, reduce MIGS by displacement, and achieve specific low contact resistances as claimed in US10937880.
Louie, Chelikowsky, and Cohen, “Ionicity and the theory of Schottky barriers,” Phys. Rev. B 15, 2154 (1977)
- Description: This academic paper contributes to the theoretical framework of Schottky barriers and interface properties.
- Potential Anticipation (35 U.S.C. § 102): Similar to Tersoff's work, this paper provides theoretical background rather than disclosing the specific inventive methods and devices of US10937880.

Note on US 6,833,556 B2:
U.S. Pat. No. 6,833,556 B2 is explicitly mentioned in US10937880 as a "co-pending" application by the "present inventors". While it describes highly similar technology (e.g., FETs with passivated Schottky barriers, depinning the Fermi level), its filing date (January 14, 2003) is after the priority date of US10937880 (August 12, 2002). Therefore, it cannot be considered prior art under 35 U.S.C. § 102 for anticipation purposes against US10937880. It represents related inventive work by the same inventors and could be relevant for obviousness-type double patenting considerations, but not direct anticipation.