Obviousness

Obviousness Analysis of US Patent 10937880 under 35 U.S.C. § 103

This analysis identifies combinations of prior art references (as disclosed within the patent itself) that a person having ordinary skill in the art (PHOSITA) would have been motivated to combine, and evaluates whether such combinations would render the claims of US patent 10937880 obvious. The current date is April 26, 2026.

Overview of the Invention's Asserted Novelty

US patent 10937880 focuses on a method and device for "depinning the Fermi level" of a semiconductor at an electrical junction by introducing a thin interface layer between a metal and the semiconductor. This interface layer serves a dual purpose: (1) it passivates the semiconductor surface by terminating dangling bonds and reducing surface states, and (2) it displaces the semiconductor from the metal to reduce the effect of metal-induced gap states (MIGS). The patent asserts that this approach allows for controlled tuning of the Schottky barrier height and, critically, achieves a minimum specific contact resistance (e.g., less than approximately 10 Ω-μm²) through an "optimum thickness" of the interface layer. This optimum thickness balances the desire for a thin layer to permit tunneling current with a thick enough layer to reduce MIGS, which otherwise increase resistance by pinning the Fermi level near mid-gap.

Identified Prior Art References (from the patent's disclosure)

The patent's background section describes the state of the art and known problems, which serve as the basis for this obviousness analysis. No specific prior art patents, other than general concepts, are detailed that would anticipate the core inventive step.

• A1: Schottky (1938) and Bardeen's Model: These describe the fundamental concept of a Schottky barrier at metal-semiconductor junctions and introduce the idea of surface states causing Fermi level pinning, making the barrier height largely independent of the metal's work function. The patent states that Bardeen's model, like Schottky's, is best considered a "limiting case" rarely observed experimentally.
• A2: Tersoff (1984) and Louie, Chelikowsky, and Cohen (1977): These references explain that Fermi level pinning is primarily due to metal-induced gap states (MIGS), where metal electron wave functions decay into the semiconductor bandgap. These MIGS populate energy states that pin the Fermi level.
• A3: Conventional Semiconductor Surface Passivation: The patent describes surface passivation (e.g., with silicon dioxide) as a "common processing operation" to chemically neutralize dangling bonds and physically protect silicon. However, it notes that silicon dioxide is an "insulating dielectric" that poses a "significant barrier to the flow of current" and is difficult to grow as a thin, controlled layer.
• A4: Prior Attempts to Control Barrier Height: The patent mentions prior attempts using silicides as contact metals (which limit metal choices and result in a pinned, fixed barrier height) and high doping levels (which reduce resistance through tunneling but do not truly tune the barrier height).

Obviousness Analysis

Combination 1: A1 (Schottky/Bardeen's problem of pinning) + A2 (Tersoff's explanation of MIGS) + A3 (Conventional passivation shortcomings) + A4 (Limitations of existing solutions)

• PHOSITA's Motivation to Combine: A PHOSITA, aware of the persistent problem of Fermi level pinning (A1) and Tersoff's explanation of MIGS (A2) as a primary cause, would be highly motivated to find a solution that effectively "depins" the Fermi level. They would also be aware that conventional passivation techniques (A3) address surface states but often introduce high resistance (e.g., SiO2), and that other methods like silicides or heavy doping (A4) do not fully solve the pinning or allow for barrier height tuning. Therefore, a PHOSITA would seek an improved interface that simultaneously addresses both surface states and MIGS to achieve a truly tunable and electrically efficient junction. It would be a logical step to consider an interface layer that chemically passivates the semiconductor surface while also creating a physical separation between the metal and semiconductor to reduce MIGS effects.

• Why Claims Would Not Be Rendered Obvious by this Combination (Core Non-Obviousness):
  While the motivation exists to combine these prior art teachings to attempt depinning, this combination does not explicitly teach or suggest the critical discovery claimed by US10937880: the existence of an "optimum thickness" for the interface layer that leads to a minimum specific contact resistance (e.g., less than approximately 10 Ω-μm² or 1 Ω-μm²) by balancing the competing effects of increasing tunneling current (with decreasing thickness) and increasing MIGS-induced barrier formation (with further decreasing thickness below a certain point).

  The patent explicitly describes this as a discovery: "The present inventors have determined that for thin interface layers disposed between a metal and a silicon-based semiconductor... there exist corresponding minimum specific contact resistances." It further illustrates this "competition" and "optimum thickness" with FIG. 8. Prior art generally understood that thinner layers typically lead to lower tunneling resistance, and that separating metal from semiconductor reduces MIGS. However, the counter-intuitive observation that resistance increases again at very thin layers due to MIGS reasserting pinning, thus creating a minimum, is not taught by the combined references A1-A4. Without this insight, a PHOSITA would likely struggle to achieve the specific low contact resistances (e.g., <10 Ω-μm²) while simultaneously achieving depinning, as merely making the layer very thin for tunneling might run into the increased resistance due to MIGS.

  Therefore, the invention's emphasis on selecting an interface layer thickness to achieve this minimum specific contact resistance (as specified in Claim 1, Claim 11, and Claim 17) through the described mechanism of balancing MIGS reduction and tunneling current represents a non-obvious advancement over the collective teachings of A1, A2, A3, and A4.

Additional Considerations Regarding Specific Embodiments (e.g., Claim 11's nitrogenous formation):

Claim 11 specifically recites an interface layer formed by "heating the semiconductor in presence of nitrogenous material in a vacuum chamber." The patent itself notes that "Rapid Thermal Nitridation (RTN)" is a conventional process, implying that nitridation as a passivation technique was known. However, the patent then describes specific processing conditions (e.g., lower temperatures of 300-750° C., or high temperatures of 900-1000° C.+ in ultra-high vacuum with short pulses/small amounts of nitrogenous material) to "controllably form thin yet effective interface layers" (e.g., <1nm, monolayer thickness).

While a PHOSITA would know about nitridation, the specific combination of these precise processing parameters with the goal of achieving the "optimal thickness" for minimum specific contact resistance and Fermi level depinning, driven by the previously mentioned discovery, would not be obvious. Without the underlying understanding of the resistance-thickness curve (FIG. 8) and the resulting "optimum thickness," merely applying known nitridation techniques would likely not consistently yield the claimed device properties (depinning + very low specific contact resistance).

Conclusion

Based on the information provided within the patent document US10937880, the core inventive step, which is the discovery and application of an "optimum thickness" for an interface layer that simultaneously achieves Fermi level depinning (by both surface passivation and MIGS reduction) and a minimum specific contact resistance, is not explicitly taught or strongly suggested by the prior art acknowledged in the patent's background. While a PHOSITA would be motivated to combine existing knowledge to address the problems of Fermi level pinning, they would not be led to the specific insight of the "optimal thickness" where resistance first decreases due to tunneling but then increases again due to MIGS-induced barrier formation. This unexpected phenomenon and its exploitation to achieve specific low contact resistances represent a non-obvious contribution.