Derivative works — US Patent 10937880

Here is a comprehensive "Defensive Disclosure" document for US patent 10937880, focusing on generating "Prior Art" to render future incremental improvements obvious or non-novel, based on the provided independent claims.

Defensive Disclosure for US Patent 10937880

This document describes various technical derivatives and extensions of the core inventions claimed in US Patent 10937880, "Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions." The purpose is to establish prior art for potential future incremental innovations, making them appear obvious or non-novel, thereby limiting the scope of future patentability for competitors.

Derivations from Claim 1

Claim 1: An electrical device, comprising: a semiconductor; a metal; and an interface layer disposed between and in contact with the metal and the semiconductor and configured to depin a Fermi level of the semiconductor while still permitting current flow between the metal and the semiconductor when the electrical device is biased, wherein a specific contact resistance of the electrical device is less than approximately 10 Ω-μm², wherein the interface layer comprises a passivation layer, and wherein the passivation layer comprises at least one of a nitride, an oxide, an oxynitride, an arsenide, a hydride and a fluoride.

Derivative 1.1: Material & Component Substitution - Two-Dimensional (2D) Semiconductor with Transition Metal Dichalcogenide (TMD) Interface

Enabling Description: An electrical device comprising a graphene sheet (semiconductor) and a platinum (Pt) contact (metal). An interface layer, comprising a monolayer or few-layer tungsten disulfide (WS₂) film, is disposed between the graphene and the Pt. The WS₂ layer, acting as both a passivation layer and a separation layer, is formed via chemical vapor deposition (CVD) or atomic layer deposition (ALD) to achieve a thickness between 0.5 nm and 2 nm. This WS₂ interface provides a large enough bandgap to reduce metal-induced gap states (MIGS) in the graphene and passivates dangling bonds at the graphene surface, thereby depinning the Fermi level of the graphene. The specific contact resistance is maintained below 10 Ω-μm² due to efficient tunneling through the thin WS₂ layer. The choice of Pt and WS₂ enables precise tuning of the work function difference at the junction for optimized carrier injection.

graph TD
    A[Graphene Semiconductor] --> B{WS2 Interface Layer};
    B --> C[Platinum Metal Contact];
    C -- Electrical Bias --> A;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px

Derivative 1.2: Operational Parameter Expansion - Cryogenic High-Frequency Device with Quantum Dot Interface

Enabling Description: An electrical device incorporating a silicon-germanium (SiGe) heterostructure (semiconductor) and a niobium (Nb) alloy (metal) contact, designed for operation at cryogenic temperatures (e.g., 4 K) and THz frequencies (e.g., 300 GHz). The interface layer consists of an array of cadmium selenide (CdSe) quantum dots embedded within a thin (< 1 nm) hafnium oxide (HfO₂) matrix. The quantum dots are precisely controlled in size (2-5 nm diameter) to introduce specific energy states that facilitate resonant tunneling, effectively depinning the SiGe Fermi level and minimizing MIGS at 4 K. The HfO₂ matrix provides passivation and structural integrity. The device exhibits a specific contact resistance well below 1 Ω-μm² under these extreme conditions, optimizing charge transport for high-frequency quantum computing or superconducting circuit applications.

graph TD
    A[SiGe Semiconductor] --> B{HfO2/CdSe QD Interface};
    B -- Resonant Tunneling --> C[Niobium Alloy Metal];
    A -- Cryogenic/THz Operation --> D[External Control Unit];
    C -- Cryogenic/THz Operation --> D;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#ddf,stroke:#333,stroke-width:2px

Derivative 1.3: Cross-Domain Application - Bio-Integrated Neural Interface

Enabling Description: A bio-integrated neural interface device comprising a biocompatible silicon carbide (SiC) semiconductor substrate (biologically inert and robust) and a gold (Au) microelectrode (metal) for neural signal detection. An ultrathin (0.8 nm) silicon oxynitride (SiON) interface layer is formed between the SiC and Au via plasma-enhanced atomic layer deposition. This SiON layer is engineered to depin the Fermi level of the SiC, optimizing charge transfer with neural tissue while maintaining biocompatibility. The specific contact resistance is kept below 5 Ω-μm², ensuring efficient and low-noise electrical communication with neurons for prosthetic control or brain-computer interfaces. The SiON layer provides robust passivation against biofluids, reducing impedance drift over long-term implantation.

flowchart LR
    A[SiC Semiconductor] --> B{SiON Interface Layer};
    B --> C[Gold Microelectrode];
    C -- Neural Signal Transduction --> D(Neural Tissue);
    A -- Biocompatible --> D;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#afa,stroke:#333,stroke-width:2px

Derivative 1.4: Integration with Emerging Tech - AI-Optimized Interface Layer for Reconfigurable Computing

Enabling Description: A reconfigurable computing device utilizing gallium nitride (GaN) high-electron-mobility transistors (HEMTs) as semiconductors and titanium nitride (TiN) gate contacts (metal). An interface layer, comprising a self-assembled monolayer of an organosilane derivative (e.g., aminopropyltriethoxysilane, APTS) followed by an ultrathin plasma-nitrided aluminum oxide (AlON) layer, is dynamically optimized via an integrated AI controller. During fabrication, the AI system monitors in situ deposition parameters (temperature, pressure, precursor flow) to achieve a desired interface thickness (0.3-1.5 nm) and composition, targeting minimal specific contact resistance (< 1 Ω-μm²) and precise Fermi level depinning for a particular GaN doping profile. Post-fabrication, the AI can apply small, localized electrical biases to subtly adjust interface trap states, dynamically reconfiguring the Schottky barrier height for optimal performance in different computational tasks. IoT sensors embedded in the device provide real-time electrical characteristics to the AI.

graph TD
    A[GaN HEMT Semiconductor] --> B{APTS/AlON Interface Layer};
    B --> C[TiN Gate Metal];
    D[IoT Sensors] -- Real-time Data --> E(AI Controller);
    E -- Optimization Feedback --> B;
    E -- Dynamic Tuning --> B;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#afa,stroke:#333,stroke-width:2px
    style E fill:#dde,stroke:#333,stroke-width:2px

Derivative 1.5: The "Inverse" or Failure Mode - Self-Limiting Current for Safe Operation in Power Electronics

Enabling Description: A power semiconductor device, such as a silicon carbide (SiC) MOSFET, with aluminum (Al) ohmic contacts. The interface layer, in this case, is a tailored hydrogenated amorphous silicon (a-Si:H) layer deposited between the SiC and Al, with a precise thickness (2-5 nm) and hydrogen content (5-15%). This layer is designed such that, under nominal operating conditions, it behaves as described in Claim 1, providing depinning and low contact resistance (< 10 Ω-μm²). However, upon an overcurrent event (e.g., short circuit), the a-Si:H layer is engineered to undergo a localized, self-limiting structural transformation (e.g., increase in trap density, slight delamination or local crystallization) that intentionally increases its specific contact resistance by several orders of magnitude (> 100 Ω-μm²). This controlled failure mode acts as an integrated fuse, limiting current flow and protecting downstream circuitry and the device from catastrophic thermal runaway, without causing permanent damage to the bulk semiconductor. The device can then be reset or replaced.

stateDiagram-v2
    state NormalOperation {
        Semiconductor --> InterfaceLayer: Low Resistance (<10 Ω-μm²)
        InterfaceLayer --> Metal: Depinned Fermi Level
        NormalOperation --> OvercurrentDetected: Current > Threshold
    }
    state OvercurrentDetected {
        OvercurrentDetected --> ControlledResistanceIncrease: Interface Layer Transformation
        ControlledResistanceIncrease --> HighResistanceMode: Current Limited
        HighResistanceMode --> SafeShutdown: System Protection
    }
    HighResistanceMode --> NormalOperation: Reset/Replacement

Derivations from Claim 11

Claim 11: An electrical device, comprising: a silicon-based semiconductor; a conductor; and an interface layer disposed between and in contact with the conductor and the silicon-based semiconductor and configured to allow a Fermi level of the conductor to (i) align with a conduction band of the silicon-based semiconductor, (ii) align with a valence band of the silicon-based semiconductor, or (iii) be independent of the Fermi level of the silicon-based semiconductor, wherein current flows between the conductor and the silicon-based semiconductor when the electrical device is biased, wherein the interface layer has a thickness corresponding to a minimum or near minimum specific contact resistance for the junction of less than or equal to approximately 10 Ω-μm², and wherein the interface layer is formed by heating the silicon-based semiconductor in the presence of a nitrogenous material selected from the group consisting of ammonia (NH3), nitrogen (N2) and unbound gaseous nitrogen (N) generated from a plasma process while in a vacuum chamber.

Derivative 11.1: Material & Component Substitution - Germanium Semiconductor with Metal Nitride Conductor and Boron Nitride Interface

Enabling Description: An electrical device using a p-type germanium (Ge) substrate (silicon-based semiconductor analog) and a molybdenum nitride (MoN) film (conductor). The interface layer is a hexagonal boron nitride (h-BN) film, formed by heating the Ge substrate in an ultra-high vacuum chamber at 700°C under a partial pressure of nitrogen gas (N₂) derived from a remote plasma source. This method ensures a precisely controlled h-BN monolayer or bilayer (<1 nm) growth. The h-BN layer enables the Fermi level of the MoN conductor to align with the valence band of the p-type Ge, or to be intentionally shifted via localized strain engineering to be independent. The specific contact resistance is maintained below 1 Ω-μm². This architecture is optimized for high-speed p-channel devices with tailored barrier heights.

graph TD
    A[Germanium Semiconductor (p-type)] --> B{h-BN Interface Layer};
    B --> C[Molybdenum Nitride Conductor];
    D(UHV Chamber + Plasma N2) -- Heating --> B;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#ddf,stroke:#333,stroke-width:2px

Derivative 11.2: Operational Parameter Expansion - High-Pressure, High-Temperature Deep-Well Junction

Enabling Description: An electrical device designed for extreme downhole drilling environments (e.g., 200 MPa, 400°C) using a deep-well silicon carbide (SiC) semiconductor (silicon-based analog). The conductor is a refractory metal alloy, specifically a tungsten-rhenium (W-Re) alloy. The interface layer is a highly stable, dense silicon nitride (Si₃N₄) film, precisely formed by rapid thermal annealing of the SiC substrate in a sealed high-pressure chamber (e.g., 10 MPa) with an ammonia (NH₃) ambient at 1200°C. This high-pressure, high-temperature synthesis produces an ultrathin (1-3 nm) Si₃N₄ layer that can withstand the operational extremes while ensuring Fermi level control (e.g., alignment with conduction band for n-type SiC). The specific contact resistance remains below 5 Ω-μm² under these severe conditions.

graph TD
    A[SiC Semiconductor (Deep Well)] --> B{Dense Si3N4 Interface Layer};
    B --> C[W-Re Alloy Conductor];
    D(High Pressure/Temp Chamber) -- NH3 Ambient --> B;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#ddf,stroke:#333,stroke-width:2px

Derivative 11.3: Cross-Domain Application - Space-Hardened Radiation Detector

Enabling Description: A radiation detector for space applications, employing a high-purity silicon (Si) semiconductor and a tantalum (Ta) conductor. The interface layer is a plasma-nitrided silicon layer, approximately 0.5 nm to 1.5 nm thick, formed by exposing the Si substrate to an unbound gaseous nitrogen (N) plasma in a vacuum chamber at 450°C. This specific process creates a radiation-hardened interface that maintains Fermi level depinning and low contact resistance (< 10 Ω-μm²) even after exposure to significant ionizing radiation doses. The controlled Fermi level allows for precise adjustment of the Schottky barrier for optimal signal-to-noise ratio in radiation detection. The device is designed to operate reliably in the extreme temperature fluctuations and radiation fields of space.

flowchart LR
    A[High-Purity Silicon Semiconductor] --> B{Plasma-Nitridated Si Interface Layer};
    B --> C[Tantalum Conductor];
    D(Vacuum Chamber + N Plasma) -- Exposure --> B;
    C -- Radiation Detection --> E(Signal Processing);
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#ddf,stroke:#333,stroke-width:2px
    style E fill:#afa,stroke:#333,stroke-width:2px

Derivative 11.4: Integration with Emerging Tech - IoT Edge Device with Self-Calibrating Junctions

Enabling Description: An IoT edge computing device incorporating low-power silicon-on-insulator (SOI) transistors (silicon-based semiconductor) and aluminum (Al) interconnects (conductor). Each junction utilizes a nitrogen-based interface layer (e.g., amorphous silicon nitride, SiNₓ) formed by pulsed-ammonia annealing in a vacuum chamber. Integrated IoT sensors measure the instantaneous specific contact resistance and barrier height of individual junctions in real-time. This data is fed to a local AI module that uses machine learning models to self-calibrate the device by predicting and compensating for performance drift due to aging or environmental factors. Firmware updates, potentially verified via blockchain, can then dynamically adjust operational parameters (e.g., gate voltage timings) to maintain optimal Fermi level alignment and contact resistance below 10 Ω-μm² over the device's lifespan.

sequenceDiagram
    participant S as SOI Semiconductor
    participant I as SiNx Interface
    participant C as Aluminum Conductor
    participant O as IoT Sensors
    participant A as AI Module (Edge)
    participant B as Blockchain (Cloud)

    S->>I: Bias Current
    I->>C: Current Flow
    O->>A: Measure (Resistance, Barrier Height)
    A->>A: Analyze Drift (ML Model)
    A->>I: Calibrate (Adjust Params)
    A->>B: Log Performance (Secure)
    B->>A: Verify Firmware Updates

Derivative 11.5: The "Inverse" or Failure Mode - Tunable Rectification for Adaptive Power Management

Enabling Description: An adaptive power management unit for a complex system (e.g., autonomous vehicle) where the silicon-based semiconductors (e.g., power SiGe rectifiers) require dynamic rectification characteristics. Each rectifier features a copper (Cu) conductor and a nitrogen-doped amorphous silicon (a-Si:N) interface layer. This a-Si:N layer is formed by heating the SiGe in a vacuum with controlled pulses of ammonia (NH₃) to achieve a thickness between 1-4 nm, precisely setting the initial Fermi level alignment for a specific rectification ratio. When the system detects an anomalous power surge or drop, the a-Si:N interface is subjected to a transient, reversible thermal or electrical pulse. This pulse induces a temporary, controlled change in the nitrogen bonding configuration within the a-Si:N, which in turn alters the effective work function difference and thus the Schottky barrier height. This deliberately increases the reverse bias current (reducing the rectification ratio) or increases the forward bias resistance, providing an adaptive current-limiting or voltage-clamping behavior as a fail-safe or power-saving mode, rather than merely maintaining low resistance. Upon cessation of the anomalous condition, the interface reverts to its original properties.

stateDiagram-v2
    state NormalRectification {
        SiGe --> Interface: Desired Barrier
        Interface --> Cu: Optimal Rectification
        NormalRectification --> AnomalyDetected: Power Surge/Drop
    }
    state AnomalyDetected {
        AnomalyDetected --> AdaptiveTuning: Thermal/Electrical Pulse
        AdaptiveTuning --> ModifiedRectification: Barrier Altered
        ModifiedRectification --> SafeOperation: Current Limited/Clamped
        ModifiedRectification --> NormalRectification: Anomaly Resolved
    }

Derivations from Claim 17

Claim 17: A method for depinning a Fermi level of a semiconductor in an electrical junction, the method comprising: disposing an interface layer between a surface of the semiconductor and a conductor, the interface layer being configured to (i) be of a thickness sufficient to reduce effects of metal-induced gap states (MIGS) in the semiconductor, and (ii) passivate the surface of the semiconductor, wherein significant current flows between the conductor and the semiconductor because the thickness of the interface layer is chosen to provide a minimum or near minimum specific contact resistance for the junction, and wherein the interface layer comprises at least one of a nitride, an oxide, an oxynitride, an arsenide, a hydride and a fluoride.

Derivative 17.1: Material & Component Substitution - Organic Semiconductor with Conductive Polymer and Graphene Oxide Interface

Enabling Description: A method for depinning the Fermi level in an electrical junction using an organic semiconductor (e.g., P3HT:PCBM bulk heterojunction film) and a conductive polymer (e.g., PEDOT:PSS) as the conductor. The interface layer is a chemically modified graphene oxide (GO) film, partially reduced to tune its electronic properties. The method involves spin-coating the GO dispersion onto the organic semiconductor surface, followed by a controlled thermal annealing step in a reducing atmosphere (e.g., hydrogen/argon mix) to create a reduced graphene oxide (rGO) layer with a thickness between 1-3 nm. This rGO layer is configured to (i) reduce MIGS in the organic semiconductor by providing an effective displacement, and (ii) passivate the organic semiconductor surface by terminating charge trapping sites. The rGO's tunable work function and high conductivity ensure significant current flow, with its thickness chosen for a minimum specific contact resistance for the organic junction, typically below 50 Ω-μm² for organic devices.

flowchart TD
    A[Organic Semiconductor Surface] --> B{Spin-Coat Graphene Oxide (GO)};
    B --> C{Anneal in Reducing Atmosphere};
    C --> D[Reduced Graphene Oxide (rGO) Interface Layer];
    D --> E[Conductive Polymer (PEDOT:PSS) Conductor];
    E -- Current Flow --> A;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style D fill:#bbf,stroke:#333,stroke-width:2px
    style E fill:#ccf,stroke:#333,stroke-width:2px

Derivative 17.2: Operational Parameter Expansion - High-Vacuum Atomic Layer Deposition (ALD) with Sub-Angstrom Control

Enabling Description: A method for depinning the Fermi level of a semiconductor (e.g., indium gallium arsenide, InGaAs) in an electrical junction with a gold (Au) conductor. The interface layer is an aluminum oxide (Al₂O₃) film, precisely grown via ultra-high vacuum (UHV) atomic layer deposition (ALD) using trimethylaluminum (TMA) and water vapor precursors. The method disposes the Al₂O₃ layer with sub-angstrom thickness control (e.g., 0.3 nm to 1.0 nm, corresponding to 1-3 atomic layers) at a substrate temperature of 150°C. This extreme precision in thickness ensures (i) optimal reduction of MIGS in the InGaAs by minimizing tunneling path and maximizing separation, and (ii) atomic-scale passivation of the InGaAs surface. The specific ALD parameters are rigorously calibrated to achieve the minimum specific contact resistance, potentially below 0.1 Ω-μm², by tailoring the Al₂O₃ to act as a quantum mechanical tunnel barrier rather than a conventional dielectric.

sequenceDiagram
    participant S as InGaAs Semiconductor
    participant U as UHV ALD Chamber
    participant A as TMA Precursor
    participant W as H2O Precursor
    participant C as Gold Conductor

    U->>S: Place Substrate
    loop ALD Cycles (1-3)
        U->>A: Pulse TMA
        A->>S: Adsorb TMA
        U->>U: Purge
        U->>W: Pulse H2O
        W->>S: React to Form Al2O3
        U->>U: Purge
    end
    S->>C: Deposit Gold Conductor
    C->>S: Electrical Junction Formed

Derivative 17.3: Cross-Domain Application - Photoelectrochemical Energy Conversion Cells

Enabling Description: A method for manufacturing a photoelectrochemical (PEC) cell, where a wide bandgap semiconductor (e.g., titanium dioxide, TiO₂) acts as a photoanode, and a platinum (Pt) mesh serves as the electrocatalytic conductor. The method disposes an interface layer of hafnium oxynitride (HfON) between the TiO₂ and the Pt mesh. The HfON layer is formed by plasma-enhanced ALD, tuning the nitrogen flow during deposition to achieve a specific composition and a thickness of 2-4 nm. This HfON layer is configured to (i) reduce MIGS at the TiO₂/electrolyte interface, enhancing charge separation efficiency, and (ii) passivate surface defects on the TiO₂ photoanode, suppressing recombination pathways. The thickness is chosen to provide a minimum specific contact resistance for charge transfer to the electrolyte and through the Pt mesh, optimizing the PEC cell's efficiency for solar hydrogen production or CO₂ reduction.

flowchart LR
    A[TiO2 Photoanode Semiconductor] --> B{HfON Interface Layer (ALD)};
    B --> C[Platinum Mesh Conductor];
    C -- Electrocatalytic Reaction --> D(Electrolyte);
    A -- Photoexcitation --> D;
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style B fill:#bbf,stroke:#333,stroke-width:2px
    style C fill:#ccf,stroke:#333,stroke-width:2px
    style D fill:#afa,stroke:#333,stroke-width:2px

Derivative 17.4: Integration with Emerging Tech - Automated Robotic Fabrication with Real-time Defect Detection

Enabling Description: A method for automated, robotic fabrication of electrical junctions on flexible semiconductor substrates (e.g., polysilicon on Kapton). The process disposes a fluorinated graphene (FG) interface layer between the polysilicon and a silver (Ag) conductor. The FG layer is applied via a robotic arm using a controlled spray deposition of fluorinated graphene nanoplatelets, followed by UV curing and annealing. High-resolution optical and electron microscopy, coupled with AI-driven image recognition, performs real-time defect detection during deposition. The AI system adjusts the spray parameters (nozzle pressure, droplet size, movement speed) to achieve a precise FG thickness (1-5 nm) across the flexible substrate, ensuring optimal MIGS reduction and surface passivation. Anomalies detected by the AI trigger immediate corrective actions or flagging for rework, ensuring that each junction achieves the minimum specific contact resistance (e.g., < 10 Ω-μm²) and validated via blockchain ledger for quality assurance.

graph TD
    A[Flexible Polysilicon Substrate] --> B(Robotic Spray Deposition of FG);
    B --> C{UV Curing & Annealing};
    C --> D[FG Interface Layer];
    D --> E[Silver Conductor Deposition];
    E -- Electrical Connection --> A;
    F(AI Vision System) -- Real-time Monitoring --> B;
    F -- Parameter Adjustment --> B;
    F -- Defect Flagging --> G{Blockchain Ledger};
    style A fill:#f9f,stroke:#333,stroke-width:2px
    style D fill:#bbf,stroke:#333,stroke-width:2px
    style E fill:#ccf,stroke:#333,stroke-width:2px
    style F fill:#afa,stroke:#333,stroke-width:2px
    style G fill:#dde,stroke:#333,stroke-width:2px

Derivative 17.5: The "Inverse" or Failure Mode - Reversible High-Impedance Switching for Redundant Systems

Enabling Description: A method for fabricating electrical junctions in a redundant system (e.g., aerospace avionics) where a semiconductor (e.g., silicon-on-sapphire, SOS) must selectively enter a high-impedance, low-leakage state. The conductor is a platinum-iridium (PtIr) alloy. The interface layer is a dynamically tunable strontium titanate (SrTiO₃) thin film, deposited via pulsed laser deposition (PLD) to a thickness of 3-5 nm. This SrTiO₃ layer is configured to provide passivation and MIGS reduction under normal operation, achieving low specific contact resistance (< 10 Ω-μm²). However, upon a system-level fault detection, a controlled, localized electric field or thermal pulse is applied to the SrTiO₃ layer. This induces a reversible phase transition or defect engineering within the SrTiO₃, which increases the junction's specific contact resistance to > 10⁸ Ω-μm² (effectively a high-impedance "off" state) and maximizes the Schottky barrier height. This enables the faulty section to be electrically isolated with minimal leakage, allowing the redundant system to continue operation without a full shutdown. The "on" state can be restored by reversing the applied field/pulse.

stateDiagram-v2
    state NormalOperation_LowResistance {
        SOS --> SrTiO3: Low Z (<10 Ω-μm²)
        SrTiO3 --> PtIr: Current Flow
        NormalOperation_LowResistance --> FaultDetected: System Fault
    }
    state FaultDetected {
        FaultDetected --> ApplyElectricField: Induce Phase Transition
        ApplyElectricField --> HighImpedanceState: Z > 10^8 Ω-μm²
        HighImpedanceState --> SystemIsolation: Redundant Operation
        HighImpedanceState --> RestoreNormalOperation: Clear Fault
    }
    state RestoreNormalOperation {
        RestoreNormalOperation --> RemoveElectricField: Revert Phase
        RemoveElectricOperation --> NormalOperation_LowResistance
    }

Combination Prior Art Scenarios

Here are three "Combination Prior Art" scenarios where US Patent 10937880 is combined with existing open-source standards, demonstrating how future improvements could be considered obvious:

US10937880 + Open-Source Semiconductor Process Design Kit (PDK) Libraries:
- Description: The methodologies for forming interface layers and controlling Fermi level pinning, as described in US10937880, could be readily integrated into standard, open-source Process Design Kit (PDK) libraries (e.g., those developed by academic consortia or community efforts for specific fabrication foundries like SkyWater Technology's open-source PDK). A skilled engineer, using a PDK that specifies standard processes for thin film deposition (e.g., ALD, CVD) and surface passivation (e.g., nitridation, oxidation), would find it obvious to apply the principles of US10937880 to existing semiconductor device architectures. Specifically, the PDK could include recipes for depositing ultra-thin (0.1-5 nm) passivation layers (nitrides, oxides, fluorides) at metal-semiconductor contacts, with parameters tuned to achieve specific contact resistances below 10 Ω-μm². This would enable designers to implement depinned Fermi level junctions in various standard devices (e.g., MOSFETs, diodes) for performance enhancement, without inventive effort.
US10937880 + IPC-2221 Generic Standard for Printed Board Design (or similar electronics manufacturing standards):
- Description: The principles of forming a depinned Fermi level junction using an interface layer (as per US10937880) can be extended to advanced packaging and interconnect technologies governed by open standards such as IPC-2221. Given the drive for miniaturization and performance in package-level integration, it would be obvious to apply these interface layer techniques to improve the electrical characteristics of solder joints or direct metal-to-semiconductor bonds within a 3D integrated circuit (3D-IC) stack. For instance, before bonding a micro-bump of copper to a silicon die, a thin (e.g., 2 nm) interface layer of silicon nitride or an oxynitride could be selectively grown on the silicon contact pad. This application of US10937880 would reduce contact resistance and mitigate Fermi level pinning at the inter-die interface, thereby improving the overall performance and reliability of the 3D-IC, a known challenge in advanced packaging. The methods described in US10937880, when applied in the context of improving established interconnect standards, would be obvious to those skilled in semiconductor packaging.
US10937880 + Open-Source Materials Characterization & Simulation Software (e.g., VASP, Quantum ESPRESSO):
- Description: The inventive concept of US10937880 hinges on understanding and controlling phenomena like MIGS and surface passivation. The use of open-source computational materials science software packages (e.g., VASP for Vienna Ab initio Simulation Package, or Quantum ESPRESSO for ab initio calculations of electronic structure and materials properties) has become standard practice in academic and industrial research for predicting and analyzing material behavior at the atomic scale. Given the detailed descriptions in US10937880 regarding the effects of interface layer thickness and material properties on Fermi level depinning, a person skilled in the art of computational materials science would find it obvious to use these open-source tools to predictively design novel interface layers or optimize existing ones. For example, simulating the electron wave function decay and band alignment at metal/interface layer/semiconductor junctions for various passivation materials (e.g., different nitrides, oxides, arsenides) and thicknesses would be a routine exercise to achieve the desired depinning and minimal specific contact resistance, thereby extending or refining the disclosed inventions without requiring inventive steps.