Invalidity dossier
US 10930517
Method of forming fin-shaped structure
Current assignee: Marlin Semiconductor Ltd
Added 9/23/2026, 8:11:51 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US10930517B2
Title: Method of forming fin-shaped structure
Patent number / application: US10930517B2; application US16/532,477, filed 2019-08-06; published as US20190362981A1 on 2019-11-28; granted 2021-02-23. Priority date listed as 2014-09-09; adjusted expiration 2034-12-14. Legal status shown as active.
Assignee: Original assignee United Microelectronics Corp; current assignee listed as Marlin Semiconductor Ltd (assignment recorded 2021-07-26). Inventors include Wen-Jiun Shen, Ssu-I Fu, Yen-Liang Wu, Chia-Jong Liu, Yu-Hsiang Hung, Chung-Fu Chang, Man-Ling Lu, and Yi-Wei Chen.
Purpose: The excerpt states the invention relates generally to a fin-shaped structure and method thereof, more specifically to a fin-shaped structure having a ladder-shaped cross-sectional profile. It notes that transistors in different areas (e.g., logic and input/output areas) serve different purposes, so their structures should be tailored and their electrical demands considered. The invention therefore selectively forms fin-shaped structures with ladder-shaped cross-sectional profile parts in some areas, enabling fin-shaped structures of different heights and critical dimensions (CD) suited to each area's electrical demands. Multi-gate MOSFET advantages cited include compatibility with traditional logic processes, increased gate/substrate overlap for better channel control, reduced drain-induced barrier lowering (DIBL) and short channel effect, and increased source-drain current for the same gate length.
Plain-language scope (from the excerpt): In one method, a substrate is provided with a first fin-shaped structure in a first area and a second fin-shaped structure in a second area. An isolation structure is filled beside both. A patterned mask covers the first area and exposes the second area. A top part of the second area's isolation structure is removed to expose a first top part of the second fin-shaped structure. A treatment process modifies the external surface of that first top part to form a modified part covering it. The mask is removed. A removing process then removes part of the isolation structure and the modified part, with high removing selectivity to the fin-shaped structures, exposing a top part of the first fin-shaped structure and a second top part of the second fin-shaped structure. A second described method involves first and second gates (each a dielectric layer plus a sacrificial gate) formed across the respective fin-shaped structures, then removing the sacrificial gates.
Not established by this excerpt: The full claim set and claim language; the complete specification and drawings; specific materials, process parameters, or numeric ranges; the precise meaning or breadth of "ladder-shaped cross-sectional profile"; the remainder of the second method's steps (text is truncated); and any legal conclusions as to validity, enforceability, or claim scope. Google Patents states the legal status is an assumption and not a legal conclusion; the assignee listing may also be inaccurate.
Source: https://patents.google.com/patent/[US10930517](/patent/US10930517)/en
Generated 10/1/2026, 9:41:31 PM
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