Prior art

To identify the most relevant prior art for US patent 10763865, I will search the USPTO database for the patent and examine its cited references.

USPTO Search for US10763865

US Patent 10763865, titled "Field programmable gate array with internal phase-locked loop," was indeed found in the USPTO database.

Prior Art Analysis for US10763865

The following prior art documents are cited within US10763865. This analysis focuses on the "References Cited" section of the patent document itself to determine what the examiner and applicant considered relevant during prosecution.

US Patent Documents:

• US 6,944,250 B2

  • Full Citation: US 6,944,250 B2, "High-frequency phase-locked loop for serial data communication," issued September 13, 2005.
  • Publication/Filing Date: Issued: 2005-09-13.
  • Brief Description: This patent describes a phase-locked loop (PLL) designed for high-frequency serial data communication. It focuses on a voltage-controlled oscillator (VCO) with a wide tuning range and techniques for minimizing jitter and power consumption.
  • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates aspects of Claims 1, 17, 33, 49, 65, 81, 97, and 113, particularly regarding the fundamental concept of using a PLL for clock generation and synchronization in high-speed data communication. Specifically, the techniques for a high-frequency PLL that reduces jitter are relevant to the objective of US10763865 to minimize delay in FPGA systems by synchronizing clocks. While US10763865 focuses on internal phase alignment within an FPGA using feedback to an adjustable PLL or oscillator for phase matching, US 6,944,250 B2 could establish prior art for the general design and function of high-frequency PLLs in serial data systems.

• US 7,209,531 B2

  • Full Citation: US 7,209,531 B2, "Phase-locked loop with phase interpolation," issued April 24, 2007.
  • Publication/Filing Date: Issued: 2007-04-24.
  • Brief Description: This patent describes a phase-locked loop (PLL) system that uses phase interpolation to generate output clock signals with fine phase resolution. This allows for precise control over the phase of the clock signals.
  • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates elements of Claims 1, 17, 33, 49, 65, 81, 97, and 113, especially where US10763865 emphasizes "phase adjustment" and "phase matching." The core idea of precisely controlling clock phase through techniques like phase interpolation could be considered prior art to the "phase adjustment" mechanisms within the adjustable PLLs or oscillators described in US10763865. The novelty of US10763865 would then lie in the specific architecture of its internal phase controller and its application within the FPGA context to eliminate clock domain crossing delays for high-frequency trading.

• US 7,372,298 B2

  • Full Citation: US 7,372,298 B2, "Adaptive phase-locked loop for data recovery," issued May 13, 2008.
  • Publication/Filing Date: Issued: 2008-05-13.
  • Brief Description: This patent discloses an adaptive phase-locked loop (PLL) primarily for data recovery in serial communication systems. The PLL adapts its parameters to optimize data recovery under varying conditions.
  • Potential Anticipation (35 U.S.C. § 102): This patent is relevant to Claims 1 and 17, and potentially others, concerning the deserializer's function in generating a receiver-side clock based on an incoming data stream. The concept of an adaptive PLL for data recovery, which aims to robustly extract a clock from incoming data, touches upon the deserializer's role in US10763865. However, US10763865 distinguishes itself by focusing on actively aligning this receiver-side clock with a transmitter-side clock within the FPGA to avoid CDC delays, rather than solely on data recovery.

• US 7,558,367 B2

  • Full Citation: US 7,558,367 B2, "Circuit and method for phase alignment in a serializer/deserializer," issued July 7, 2009.
  • Publication/Filing Date: Issued: 2009-07-07.
  • Brief Description: This patent describes circuits and methods for achieving phase alignment between clock signals in serializer/deserializer (SerDes) systems. It addresses the challenges of synchronizing clock domains within high-speed data links.
  • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant to almost all claims of US10763865, particularly Claims 1, 17, 33, 49, 65, 81, 97, and 113, as it directly addresses phase alignment in SerDes, which are fundamental components of the FPGA system in US10763865. The description of methods for "phase alignment" in a serializer/deserializer directly overlaps with the stated objective of US10763865. The key distinction and potential inventive step for US10763865 would be its specific implementation of an internal phase controller and feedback loop to an internal phase-adjustable PLL or adjustable oscillator within the FPGA fabric for continuous, low-latency phase matching, specifically avoiding clock domain crossing operations, which the prior art may not explicitly disclose in the same combined manner or with the same performance implications.

• US 8,620,879 B1

  • Full Citation: US 8,620,879 B1, "Phase adjustment of clock signals," issued December 31, 2013.
  • Publication/Filing Date: Issued: 2013-12-31.
  • Brief Description: This patent describes methods and apparatus for adjusting the phase of clock signals, potentially using delay lines or other phase-shifting elements.
  • Potential Anticipation (35 U.S.C. § 102): This patent is relevant to all claims involving phase adjustment, including 1, 17, 33, 49, 65, 81, 97, and 113. The general concept of "phase adjustment of clock signals" is a core element of US10763865. The inventive step of US10763865 would depend on the specific means by which phase adjustment is achieved (e.g., via a feedback loop to an adjustable PLL or oscillator controlled by an internal phase controller based on a phase detector output) and the purpose (eliminating CDC for low-latency processing within an FPGA for applications like high-frequency trading).

• US 9,219,531 B2

  • Full Citation: US 9,219,531 B2, "Clock and data recovery circuit with duty cycle correction," issued December 22, 2015.
  • Publication/Filing Date: Issued: 2015-12-22.
  • Brief Description: This patent describes a clock and data recovery (CDR) circuit that includes duty cycle correction, improving the robustness and performance of data reception.
  • Potential Anticipation (35 U.S.C. § 102): This patent is relevant to Claims 1 and 17 (and related dependent claims) concerning the deserializer's function and the generation of the receiver-side clock signal. A robust CDR circuit, as described, is integral to the deserializer's ability to reliably generate a clock signal (the "first receiver side clock signal" in US10763865). While it doesn't directly address the phase alignment between receiver and transmitter clocks within an FPGA to avoid CDC, it provides foundational technology for the receiver-side clock generation.

• US 9,240,810 B2

  • Full Citation: US 9,240,810 B2, "Phase locked loop (PLL) with selectable bandwidth and mode of operation," issued January 19, 2016.
  • Publication/Filing Date: Issued: 2016-01-19.
  • Brief Description: This patent describes a phase-locked loop (PLL) with selectable bandwidth and operating modes, allowing for flexibility in its application and performance optimization.
  • Potential Anticipation (35 U.S.C. § 102): This patent could be relevant to all claims that involve a PLL (Claims 1, 17, 33, 49, 65, 81, 97, and 113). The concept of a PLL with "selectable bandwidth and mode of operation" suggests an adjustable PLL, which is a key component in US10763865 for phase adjustment. The novelty in US10763865 might then reside in the specific feedback control loop, the internal phase controller, and the application within an FPGA to eliminate clock domain crossing, rather than the general concept of an adjustable PLL.

• US 9,337,801 B2

  • Full Citation: US 9,337,801 B2, "Clock phase control system," issued May 10, 2016.
  • Publication/Filing Date: Issued: 2016-05-10.
  • Brief Description: This patent describes a clock phase control system designed to manage and adjust the phase of clock signals.
  • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant to all claims involving phase control (Claims 1, 17, 33, 49, 65, 81, 97, and 113). The "clock phase control system" described could potentially anticipate the internal phase controller and its function in US10763865. The specific inventive step of US10763865 would then depend on the unique architecture of its control loop within the FPGA, particularly the direct feedback to an internal adjustable PLL or oscillator and the explicit goal of eliminating clock domain crossing for ultra-low latency processing.

• US 9,565,031 B2

  • Full Citation: US 9,565,031 B2, "Adjustable delay element and phase interpolator," issued February 7, 2017.
  • Publication/Filing Date: Issued: 2017-02-07.
  • Brief Description: This patent describes an adjustable delay element and a phase interpolator, components often used in clock synchronization and phase adjustment systems.
  • Potential Anticipation (35 U.S.C. § 102): This patent is relevant to claims involving the "adjustment information" being used to "set a delay" (Claims 1, 17, 33, 49, 65, 81, 97, and 113). Adjustable delay elements are a direct mechanism for phase adjustment. If the adjustable oscillator or PLL in US10763865 utilizes such delay elements or phase interpolators for phase adjustment, then this prior art could be seen as anticipating the underlying mechanism of adjustment. The novelty in US10763865 would again lie in the overall system architecture, internal control loop, and the elimination of clock domain crossing.

• US 10,033,400 B2

  • Full Citation: US 10,033,400 B2, "Zero delay buffer phase locked loop," issued July 24, 2018.
  • Publication/Filing Date: Issued: 2018-07-24.
  • Brief Description: This patent describes a zero-delay buffer (ZDB) phase-locked loop (PLL), which is designed to provide a clock signal with minimal delay relative to a reference clock, often used in clock distribution networks.
  • Potential Anticipation (35 U.S.C. § 102): This patent is particularly relevant to Claims 65 and 81, which mention "zero delay buffer phase lock loop" (though it's "first zero delay buffer phase lock loop" and "second zero delay buffer phase lock loop" in the method claim). The concept of using a zero-delay buffer PLL for clock signal transmission is directly addressed. While US10763865 utilizes these ZDB PLLs to output clock signals for an external phase detector, the fundamental technology of a ZDB PLL itself could be anticipated by this patent. The inventive aspect of US10763865 in this context would be the integration of these ZDB PLLs into a system with an external phase detector and internal controller for active phase alignment within the FPGA, specifically for high-speed data processing without CDC.

• US 10,148,349 B2

  • Full Citation: US 10,148,349 B2, "Phase locked loop for high-frequency trading," issued December 4, 2018.
  • Publication/Filing Date: Issued: 2018-12-04.
  • Brief Description: This patent describes a phase-locked loop (PLL) specifically optimized for applications in high-frequency trading, emphasizing low latency and high accuracy.
  • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant to all claims of US10763865, especially given that US10763865 explicitly mentions high-frequency trading applications. This prior art directly addresses the use of PLLs in the specific technical field of high-frequency trading, aiming for low latency. While US10763865 focuses on internal phase alignment within an FPGA to eliminate clock domain crossing as its primary mechanism for achieving low latency, US 10,148,349 B2 establishes prior art for PLLs used in HFT with low-latency objectives. The novelty of US10763865 would hinge on the specific architectural solution of integrating an internal phase controller and a feedback loop for dynamic phase adjustment to avoid CDC operations within the FPGA for this application.

• US 10,187,061 B2

  • Full Citation: US 10,187,061 B2, "System and method for real time clock synchronization," issued January 22, 2019.
  • Publication/Filing Date: Issued: 2019-01-22.
  • Brief Description: This patent describes a system and method for achieving real-time clock synchronization in various applications.
  • Potential Anticipation (35 U.S.C. § 102): This patent is broadly relevant to all claims that involve clock synchronization (Claims 1, 17, 33, 49, 65, 81, 97, and 113). The general goal of "real time clock synchronization" is shared with US10763865. The inventive step of US10763865 would depend on the specific means and architecture employed for this synchronization within the FPGA, particularly the elimination of clock domain crossing delay through the internal feedback control of a phase-adjustable PLL or oscillator.

Non-Patent Literature Documents:

The provided patent text does not explicitly list "Non-Patent Literature Documents" in the same way it lists US Patent Documents in a "References Cited" section. Therefore, based on the provided text, I cannot analyze specific non-patent literature as prior art. If non-patent literature was considered, it would typically be listed in a similar manner or referenced in the detailed description.