Obviousness

Obviousness Analysis under 35 U.S.C. § 103

A patent claim is considered obvious if "the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains." This analysis requires considering the scope and content of the prior art, the differences between the prior art and the claims, the level of ordinary skill in the pertinent art, and any secondary considerations of non-obviousness. The Supreme Court's decision in KSR Int'l Co. v. Teleflex Inc. emphasized a "common sense" approach, recognizing that a combination of familiar elements according to known methods is likely to be obvious if the improvement is merely the predictable use of prior art elements according to their established functions.

For US10763865, the effective filing date is May 29, 2020. The prior art listed in the patent includes:

• FIG. 1 (Conventional FPGA)
• FIG. 1A (Exemplary transceiver in FIG. 1 FPGA)
• FIG. 1B (Clock Domain Crossing Circuit in FIG. 1 FPGA)
• FIG. 1C (Input/output waveforms of CDC circuit)
• Discussion of conventional FPGAs, deserializers, serializers, transceivers, and clock domain crossing circuits (CDCs).
• Mention of synchronous Ethernet systems and their limitations regarding phase alignment.

A person having ordinary skill in the art (PHOSITA) in this field would likely have a strong understanding of FPGA architecture, high-speed serial communication, clock generation and distribution, and phase-locked loops (PLLs). They would be familiar with the challenges of clock synchronization, particularly in high-frequency applications, and the use of PLLs for frequency and phase locking.

Potential Combinations of Prior Art for Obviousness:

The core inventive concept of US10763865 revolves around achieving phase matching between receiver and transmitter clocks within an FPGA, specifically by using an internal phase controller and an adjustable PLL/oscillator, to avoid the latency introduced by traditional clock domain crossing (CDC) circuits.

Several aspects of the claimed invention appear to be predictable combinations of existing technologies, particularly given the known problems with latency in conventional FPGA clock synchronization.

Combination 1: Conventional FPGA with integrated PLL and external phase detection/control.

• Prior Art Elements:

  • FIG. 1, 1A, 1B, 1C and accompanying text: These figures and descriptions clearly show a conventional FPGA with transceiver banks, deserializers, serializers, and the use of a transceiver PLL (e.g., transceiver PLL 108 in FIG. 1A) to generate the fast clock for the serializer. The patent explicitly identifies the drawback of conventional CDC circuits (112) in terms of added latency.
  • General knowledge of PLLs: PLLs are well-known control systems used to generate output signals whose phase and frequency are related to an input signal. They consist of components like a phase detector, loop filter, and voltage-controlled oscillator (VCO). FPGAs commonly incorporate PLLs for clock management, including clock multiplication and phase shifting. All-Digital PLLs (ADPLLs) are also known, which use digital components for all blocks, including a digital loop filter and digitally controlled oscillator (DCO), and can be implemented on FPGAs.
  • General knowledge of external control loops: It is a known engineering practice to implement control loops that extend beyond a single chip or module to achieve desired system-level behavior. For example, some FPGA systems route clocks externally for synchronization.

• Motivation for Combination:

  • The patent itself identifies a significant technological problem with conventional FPGAs: the latency introduced by clock domain crossing (CDC) circuits (e.g., 112 in FIG. 1B) when synchronizing receiver and transmitter clocks. A PHOSITA would be motivated to minimize this latency, especially in applications requiring fast processing, such as high-frequency trading where FPGAs are commonly used.
  • Given that PLLs are fundamental to clock generation and synchronization within FPGAs, and that external control loops are used for system-level synchronization, it would be an obvious step for a PHOSITA to combine the known elements to address the identified latency problem. Specifically, sending the receiver-side and transmitter-side clocks outside the FPGA to an external phase detector, and then feeding adjustment information back to an adjustable PLL or oscillator controlling the transmitter clock, would be a predictable way to achieve phase alignment without relying on a latency-inducing CDC. This directly addresses the problem highlighted by the patent in its background.
  • The concept of using a phase detector to measure the phase difference between two clocks and then using this difference to adjust an oscillator to align them is the fundamental principle of a PLL. Applying this principle to align two clocks within an FPGA system, even if some components (like the phase detector or a controlling oscillator) are external, would be a logical design choice for a PHOSITA trying to optimize timing.

• Obviousness of specific claims:

  • Claim 65 (System Claim - External Phase Detector) and Claim 81 (Method Claim - External Phase Detector): These claims describe a system and method where the phase detector is not on the FPGA, but communicates with the FPGA's internal phase controller to adjust an internal or external adjustable oscillator/PLL. This directly aligns with the motivation to leverage existing external control methodologies and PLL principles to solve the latency problem. The use of zero-delay buffers (e.g., 4208a, 4208b in FIG. 4A) to mitigate external wire delays is also a known technique for maintaining clock integrity.

Combination 2: Conventional FPGA with internal phase detection and an internal, adjustable PLL.

• Prior Art Elements:

  • FIG. 1, 1A, 1B, 1C and accompanying text: As above, this establishes the basic FPGA architecture and the problem of CDC latency.
  • Internal PLLs in FPGAs: FPGAs are well-known to include internal PLLs for various clock management functions. The patent itself mentions a "PLL with phase adjustment 3300" within the FPGA core (FIG. 3A) and an "adjustable transceiver PLL 3108" within the FPGA transceiver banks (FIG. 3B). These components, by their very nature, are designed to generate and adjust clock signals.
  • Digital control within FPGAs: FPGAs are programmable devices, and it is common practice to implement digital control logic within the FPGA fabric.

• Motivation for Combination:

  • If the goal is to minimize latency, keeping the entire synchronization loop within the FPGA would be highly desirable to a PHOSITA. The patent's explicit mention of an "internal phase controller" (3202 in FIG. 3A, 3B) implies the existence of computational logic within the FPGA to manage the phase adjustment.
  • Given the presence of internal PLLs in FPGAs, and the known ability to control them digitally, it would be an obvious design choice to place the phase detector and phase controller directly within the FPGA. This would allow for a completely on-chip solution, further reducing potential delays associated with off-chip communication and external components. The concept of an All-Digital PLL (ADPLL) further supports the notion of implementing such control entirely within a digital environment like an FPGA.

• Obviousness of specific claims:

  • Claim 1 (System Claim) and Claim 17 (Method Claim): These claims broadly cover an FPGA system with a deserializer, computational circuitry (without CDC), a serializer, a phase detector (on or off FPGA), and an internal phase controller that provides adjustment information to a phase-adjustable PLL within the FPGA core or an adjustable oscillator (internal/external). The inclusion of the internal phase controller and an adjustable PLL (whether explicit or an inherent feature of a modern FPGA's transceiver PLL) is a logical extension of known FPGA capabilities and the motivation to eliminate CDC latency.
  • Claim 33 (System Claim - Transceiver PLL) and Claim 49 (Method Claim - Transceiver PLL): These claims explicitly focus on using an adjustable transceiver PLL within the FPGA to generate the wire rate clock. Since transceiver PLLs (e.g., 108 in FIG. 1A) are already present in conventional FPGAs and are responsible for high-speed clock generation for serializers, making them "adjustable" based on a phase difference signal is a predictable optimization for a PHOSITA.

Overall Obviousness Rationale:

The primary motivation driving the claimed invention is the reduction of latency associated with clock domain crossing circuits in FPGAs. This problem is explicitly stated in the patent itself. The solutions proposed—using phase detectors and adjustable PLLs/oscillators (whether internal or external) to actively align clock phases—are based on well-established principles of clock synchronization and PLL design, which are widely understood and applied in digital electronics, particularly within the context of FPGAs.

A PHOSITA would recognize the benefits of eliminating CDCs for latency-sensitive applications and would naturally look to known clock management techniques, such as PLLs and delay lines, to achieve precise phase alignment. The implementation details, such as whether the phase detector or adjustable oscillator is internal or external, or the specific type of PLL used, would be considered design choices predictable to a PHOSITA based on system requirements (e.g., desired bandwidth, precision, available FPGA resources). The concept of adjusting an oscillator's bias, divider ratio, or delay based on phase difference is also a standard operation in PLLs.

Therefore, the combinations of conventional FPGA architectures with integrated or external PLLs/oscillators, coupled with phase detection and control logic, would have been obvious to a PHOSITA seeking to solve the known latency problem associated with clock synchronization in FPGAs at the time of the invention.