Prior art

Prior Art Analysis for US Patent 10,140,028: Clock Mode Determination in a Memory System

U.S. Patent 10,140,028, titled "Clock mode determination in a memory system," describes a configurable memory device that can operate with either parallel or serial clock signals, where the operating mode is set by sensing a reference voltage. The patent emphasizes the ability for a single memory component to function in both high-performance source-synchronous clocking configurations and lower-performance parallel clocking configurations.

The most relevant prior art references cited within US10140028, as identified from its "CROSS REFERENCE TO RELATED APPLICATIONS" and "BACKGROUND" sections, are analyzed below for their potential anticipation of claims under 35 U.S.C. § 102.

Identified Prior Art References:

1. U.S. Provisional Patent Application Ser. No. 60/902,003

   • Full Citation: U.S. Provisional Patent Application Ser. No. 60/902,003, filed on February 16, 2007.
   • Publication/Filing Date: February 16, 2007 (Filing Date).
   • Brief Description: This provisional application is the priority document for the patent family, meaning it describes the foundational concepts of the invention. While not explicitly detailed as a separate prior art disclosure within the provided text beyond its priority claim, it is fundamental to the lineage of the '028 patent.
   • Potential Anticipation: As the direct provisional application from which US10140028 claims benefit, it is not typically considered anticipatory against US10140028 in the usual sense of 35 U.S.C. § 102, but rather establishes the effective filing date for the subject matter disclosed within it. Therefore, it would potentially anticipate claims 1-20 and 21-27 if they fully align with the disclosure of the provisional application.

2. U.S. Patent Application Ser. No. 12/032,249 (Issued as U.S. Pat. No. 7,885,140)

   • Full Citation: U.S. patent application Ser. No. 12/032,249, filed on February 15, 2008, now issued as U.S. Pat. No. 7,885,140 on February 8, 2011.
   • Publication/Filing Date: February 15, 2008 (Filing Date); February 8, 2011 (Publication/Issue Date).
   • Brief Description: This is the parent non-provisional application from which US10140028 directly claims continuation. It likely discloses the core concepts of "Clock mode determination in a memory system," including the configurable memory device with a mode setter, clock switch, and configurable data input/output buffer, where the mode is selected by sensing a reference voltage. It describes memory systems configurable to operate with parallel or serial clock signals.
   • Potential Anticipation: Given that US10140028 is a continuation of this application, the subject matter of US10140028 is largely derived from and likely present in US7885140. Therefore, US7885140 would potentially anticipate most, if not all, of claims 1-20 (semiconductor device and configurable memory device claims) and claims 21-27 (method claims for configuring a clock operating mode, and memory system claims).

3. U.S. Patent Application Ser. No. 11/843,440

   • Full Citation: U.S. patent application Ser. No. 11/843,440.
   • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but implied to be prior to February 16, 2007, as it's mentioned as "commonly owned U.S. patent application Ser. No. 11/843,440" in the context of serial memory systems being modular.
   • Brief Description: This application describes a serial memory system that can be modular, allowing additional memory devices to be added to expand total memory capacity. It focuses on the general concept of modularity in serial memory systems.
   • Potential Anticipation: This reference primarily addresses the modularity and expandability of serial memory systems. It might potentially anticipate aspects of claims 21-27 related to a "memory system" (Claim 21, 27) that is serially connected, but it does not appear to directly address the core inventive concept of clock mode determination based on a reference voltage or the configurable input circuits for different clocking schemes as broadly detailed in claims 1-20. Therefore, its anticipation is likely limited to the general architecture of a serial memory system rather than the specific clock mode configuration.

4. U.S. Patent Application Ser. No. 11/324,023

   • Full Citation: U.S. patent application Ser. No. 11/324,023.
   • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned as prior art describing functions of a serial interface and control logic block.
   • Brief Description: This application describes various functions of a serial interface and control logic block (e.g., setting device identifier numbers, passing data, decoding commands for native operations) within a memory device that receives commands serially.
   • Potential Anticipation: This reference focuses on the functionality of the serial interface and control logic block. It potentially anticipates aspects related to the "serial input/output interface" (Claim 21) of a memory device and the general command handling within a serial memory system. However, similar to the above, it does not appear to directly disclose the clock mode determination based on VREF or the configurable input circuits for different clock signal formats. Its anticipation would likely be limited to the broader context of serial memory device operation rather than the specific clocking mode configuration.

5. U.S. Provisional Patent Application No. 60/868,773

   • Full Citation: U.S. Provisional Patent Application No. 60/868,773, filed December 6, 2006.
   • Publication/Filing Date: December 6, 2006 (Filing Date).
   • Brief Description: This provisional application discloses a configuration having memory devices of mixed types within a memory system.
   • Potential Anticipation: This reference deals with memory systems having mixed types of memory devices. While it relates to memory system configurations, it does not appear to directly teach or suggest the clock mode determination based on a reference voltage or the configurable input circuits as claimed in US10140028. Its relevance would be to the overall memory system architecture, not the specific clocking mode features.

6. U.S. Patent Application Ser. No. 11/771,023 (titled "ADDRESS ASSIGNMENT AND TYPE RECOGNITION OF SERIALLY INTERCONNECTED MEMORY DEVICES OF MIXED TYPE")

   • Full Citation: U.S. patent application Ser. No. 11/771,023, titled "ADDRESS ASSIGNMENT AND TYPE RECOGNITION OF SERIALLY INTERCONNECTED MEMORY DEVICES OF MIXED TYPE."
   • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned in the context of generating ID numbers and addressing for serially connected memory devices.
   • Brief Description: This application describes methods for address assignment and type recognition for serially interconnected memory devices, particularly in systems with mixed memory device types.
   • Potential Anticipation: This reference pertains to addressing and identification within serially connected memory devices. It informs the general operational environment of the memory system but does not directly disclose the specific clock mode determination mechanism of US10140028. Its anticipation, if any, would be to the system-level aspects of serial connectivity and device identification.

7. U.S. Patent Application Ser. No. 11/622,828 (titled "APPARATUS AND METHOD FOR PRODUCING IDS FOR INTERCONNECTED DEVICES OF MIXED TYPE")

   • Full Citation: U.S. patent application Ser. No. 11/622,828, titled "APPARATUS AND METHOD FOR PRODUCING IDS FOR INTERCONNECTED DEVICES OF MIXED TYPE."
   • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned in the context of generating ID numbers for serially connected memory devices.
   • Brief Description: This application describes apparatus and methods for producing identification (ID) numbers for interconnected devices of mixed types.
   • Potential Anticipation: Similar to U.S. Patent Application Ser. No. 11/771,023, this reference focuses on device identification. It provides context for the addressing scheme in a serial memory system but does not directly address the clock mode configuration of US10140028.

8. U.S. Patent Application Ser. No. 11/750,649 (titled "APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES")

   • Full Citation: U.S. patent application Ser. No. 11/750,649, titled "APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES."
   • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned in the context of generating ID numbers for serially connected memory devices.
   • Brief Description: This application describes methods for establishing device identifiers for serially interconnected devices.
   • Potential Anticipation: This reference is also focused on device identification in serially interconnected systems. Its relevance to US10140028 is in the general system architecture rather than the specific clock mode configuration.

9. U.S. Patent Application Ser. No. 11/692,452 (titled "APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE")

   • Full Citation: U.S. patent application Ser. No. 11/692,452, titled "APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE."
   • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned in the context of generating ID numbers for serially connected memory devices.
   • Brief Description: This application describes apparatus and methods for producing device identifiers for serially interconnected devices of mixed types.
   • Potential Anticipation: Another reference primarily concerned with device identification in mixed-type serially interconnected systems, it contributes to the general background but does not directly anticipate the clock mode determination.

10. U.S. Patent Application Ser. No. 11/692,446 (titled "APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION")

    • Full Citation: U.S. patent application Ser. No. 11/692,446, titled "APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION."
    • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned in the context of generating ID numbers for serially connected memory devices.
    • Brief Description: This application describes apparatus and methods for producing identifiers regardless of mixed device type in a serial interconnection.
    • Potential Anticipation: This reference, like the preceding ones, focuses on device identification in serially connected systems, contributing to the general system context but not the specific clock mode features of US10140028.

11. U.S. Patent Application Ser. No. 11/692,326 (titled "APPARATUS AND METHOD FOR IDENTIFYING DEVICE TYPE OF SERIALLY INTERCONNECTED DEVICES")

    • Full Citation: U.S. patent application Ser. No. 11/692,326, titled "APPARATUS AND METHOD FOR IDENTIFYING DEVICE TYPE OF SERIALLY INTERCONNECTED DEVICES."
    • Publication/Filing Date: Not explicitly stated in the provided text for US10140028, but mentioned in the context of generating ID numbers for serially connected memory devices.
    • Brief Description: This application describes apparatus and methods for identifying device types of serially interconnected devices.
    • Potential Anticipation: Similar to the previous few references, this one is concerned with device type identification in serially connected memory systems, offering background on system configuration rather than the core invention of clock mode determination.

Summary of Anticipation:

The primary and most direct prior art for US10140028 appears to be its own parent application, U.S. Pat. No. 7,885,140 (derived from Ser. No. 12/032,249), and its provisional application, Ser. No. 60/902,003. As a continuation, US10140028 is expected to claim subject matter disclosed in these earlier applications, and thus, they would largely anticipate the claims of US10140028 if the scope of the claims is not sufficiently distinguished by new features or combinations.

The other cited patent applications (Ser. Nos. 11/843,440, 11/324,023, 60/868,773, 11/771,023, 11/622,828, 11/750,649, 11/692,452, 11/692,446, and 11/692,326) appear to provide broader context regarding serial memory systems, device addressing, and mixed device types. While foundational to the environment in which US10140028 operates, they do not appear to directly anticipate the specific mechanism of "clock mode determination in a memory system" through sensing a reference voltage and configuring input circuits accordingly, as defined in claims 1-20 and 21-27. Their potential anticipation would be limited to generic elements of a serial memory system.