Obviousness

Under 35 U.S.C. § 103, an invention is considered obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). The US10140028 patent explicitly describes the relevant prior art and the problem it aims to solve, providing a strong basis for an obviousness analysis.

Prior Art References for Combination:

1. Prior Art Flash Memory System 10 (FIG. 1 of US10140028): This reference describes a multi-drop memory system where memory devices 16 are connected in parallel to a channel 18, and a clock signal CLK is provided in parallel to each device. The patent notes its limitations, including signal integrity issues, increased power consumption at higher frequencies, and scalability limits.
2. Serial Memory System 20 (FIG. 2A of US10140028): This reference describes a serial memory system where memory devices (24, 26, 28, 30) are connected in series, but the clock signal CLK is still provided in parallel to all memory devices from a memory controller 22. This system uses "low voltage CMOS unterminated full swing signaling" (LVTTL) and operates at a "relatively relaxed clock frequency." This mode typically does not require a specific reference voltage (VREF) for data sensing, or VREF might be tied to a power supply rail (VDD or VSS).
3. Serial Memory System 40 (FIG. 2B of US10140028): This reference describes a serial memory system where memory devices (44, 46, 48, 50) are connected in series, and the clock signal CLK is provided serially from one memory device to another from an alternate memory controller 42. This "source synchronous" clock signal allows for "high frequencies" and "greater speed." This system uses "high speed transceiver logic (HSTL) signaling," which requires "a reference voltage that is used for determining a logic state of the incoming data signals." High-speed source-synchronous operation often necessitates clock synthesizers (e.g., Delay Locked Loops (DLLs) or Phase Locked Loops (PLLs)) to generate shifted clock edges for precise data sampling.

Motivation to Combine these References:

The US10140028 patent explicitly articulates the problem that provides the motivation for a person having ordinary skill in the art (PHOSITA) to combine the features of the aforementioned prior art systems. The patent states: "it may not be cost effective to replace existing slower speed serial memory systems with the high speed memory systems. Therefore, both types of memory devices would have to be available for upgrading or assembling of both types of serial memory systems." It further clarifies, "persons skilled in the art will understand that it is not cost effective to manufacture two different types of memory devices, where one type is configured for interfacing with memory controller 22 while another type is configured for interfacing with memory controller 42."

Thus, the clear motivation for a PHOSITA would be to design a single, configurable memory device that can operate interchangeably in both the slower, parallel-clocked serial memory systems (like FIG. 2A, using LVTTL) and the faster, source-synchronous serial-clocked memory systems (like FIG. 2B, using HSTL). Such a device would reduce manufacturing costs, simplify inventory, and offer greater flexibility for system designers.

Obviousness Analysis of the Independent Claims:

Claim 1: Semiconductor Device

Claim 1 describes a semiconductor device with a configurable input circuit operable in a first mode (for coincident clock/data edges, providing shifted clock edges for sampling) and a second mode (for non-coincident clock/data edges, sampling directly). The mode is set by an input pin (a reference voltage pin) which is set to a low/high power supply level for the second mode and a reference voltage level (between supply levels) for the first mode, the latter also being used to sense logic levels of input data.

• First Mode Operation: The requirements of the "first mode" (coincident edges, shifted clock edges for sampling) are directly addressed by the high-speed, source-synchronous serial memory system of FIG. 2B. Such systems, particularly those using HSTL signaling, have coincident clock and data edges and necessitate clock synthesizers (DLLs or PLLs) to generate precisely shifted internal clock phases to reliably sample data within narrow valid windows. The patent explicitly notes that "Each memory device will include a clock synthesizer, such as a DLL or a PLL for generating phases of the received clocks. Certain phases will be used to center the clock edges within the input data valid window internally to ensure reliable operation."
• Second Mode Operation: The requirements of the "second mode" (non-coincident edges, direct sampling) are met by the parallel-clocked serial memory system of FIG. 2A, which uses LVTTL signaling at "relaxed clock frequency." In such environments, clock and data edges are typically not source-synchronous, and simpler direct sampling with received clock edges is sufficient.
• Configurable Input Pin (VREF): The inventive aspect lies in using the VREF pin for dual functionality: mode selection and data reference. The HSTL signaling format described in FIG. 2B explicitly requires a "reference voltage that is used for determining a logic state of the incoming data signals." Conversely, for LVTTL signaling as used in FIG. 2A, a VREF voltage is typically "not required," and the VREF pin "can be set to either VDD or VSS."
  A PHOSITA, motivated by the stated need for a single, cost-effective device, would find it obvious to leverage an existing, required pin (VREF for HSTL) to also serve as the mode selection input. By tying VREF to a mid-supply level (e.g., VDD/2) for the high-speed HSTL/serial mode and to a power rail (VDD or VSS) for the lower-speed LVTTL/parallel mode, the device could automatically configure itself. This approach efficiently utilizes existing hardware and minimizes pin count, which is a common design goal in semiconductor packaging to reduce cost.

Claim 10: Configurable Memory Device

Claim 10 describes a configurable memory device including a mode setter, a clock switch, and a configurable data input/output buffer.

• Mode Setter: The mode setter senses the VREF voltage level and generates a mode selection signal. This is an obvious implementation of the mode selection mechanism described for Claim 1. Standard circuit elements such as voltage dividers and comparators (e.g., elements 506, 508, 512 in FIG. 6) are well-known building blocks for sensing voltage levels and generating logic signals. The addition of a delay circuit (e.g., counter 514 in FIG. 6) to allow voltages to stabilize and then disable the sensing circuit for power saving is also a conventional and obvious optimization in low-power design.
• Clock Switch: The clock switch receives either parallel or serial complementary clock signals and generates internal clock signals based on the mode selection signal. FIG. 8A explicitly shows a clock switch circuit 402 with a comparator 700 for serial clocks and buffers 702, 704 for parallel clocks, selectively enabled by the MODE signal. It also includes a PLL 706 for generating shifted clock phases in the serial mode, which can be disabled in the parallel mode to reduce power consumption. A PHOSITA would find it obvious to employ such known switching mechanisms and clock generation/management circuits to adapt to different clocking schemes based on the detected mode, especially given the explicit differences in clocking between FIG. 2A and FIG. 2B.
• Configurable Data Input/Output Buffer: This buffer is coupled to the data input port and VREF port and senses data relative to VREF in response to the serial mode (second logic state in Claim 10). FIG. 8A's data input buffer 412 shows a comparator 720 with VREF for HSTL data sensing and a buffer 722 for LVTTL data, with selection controlled by the MODE signal. This directly implements the known signaling requirements for HSTL (from FIG. 2B) and LVTTL (from FIG. 2A). The selective enabling of these known input buffer types based on the mode signal would be obvious for a PHOSITA aiming to support both signaling formats.

Claim 16: Method for Configuring a Clock Operating Mode

Claim 16 describes a method including setting a reference voltage level, comparing it to a preset reference voltage to generate a mode selection signal, and configuring a clock input buffer based on the mode selection signal. These method steps directly correspond to the functions of the hardware elements described in Claim 10. If the configurable hardware itself is obvious, then the method of operating that hardware in the described manner, using known techniques for voltage sensing, mode signal generation, and selective circuit activation, would also be obvious to a PHOSITA. The details of latching the mode signal, disabling unused circuits after a delay for power saving (determined by counting clock edges), and selectively enabling comparators or buffers, are all conventional design practices for configurable devices.

Claim 20: Configurable Memory System

Claim 20 describes a memory system comprising a memory controller and at least one serially connected memory device, where the device has clock input ports, a VREF input port, a mode setter, and a clock switch circuit. The mode setter compares VREF to a predetermined level and generates a mode selection signal, and the clock switch generates internal clocks based on this signal.

If the configurable memory device itself (as detailed in Claim 10) is deemed obvious, then incorporating such devices into a system where a memory controller provides either parallel (as in FIG. 2A) or serial (as in FIG. 2B) clock signals and sets the VREF level accordingly would be an obvious system-level integration. The patent explicitly states that the "memory controller can control" VREF or an "alternate circuit" can do so. A PHOSITA, equipped with the configurable memory device, would naturally design the memory system to utilize the device's configurable features, thereby realizing the stated goal of a versatile system.

In conclusion, the problem identified by US10140028 (the cost-ineffectiveness of manufacturing two different types of memory devices for different serial memory systems) provides a clear and explicit motivation for a PHOSITA to combine the known operational characteristics of the serial memory systems described in FIG. 2A (parallel-distributed clock, LVTTL) and FIG. 2B (source-synchronous serial clock, HSTL, VREF for sensing, DLL/PLL for timing). The implementation of this combination using a dual-purpose VREF pin for mode selection and data sensing, along with conventional circuit components for mode detection, clock switching, and data buffering, would have been obvious to a PHOSITA at the time of the invention.