US 10056902

US patent 10056902, titled "On-die termination control," was issued on August 21, 2018, from an application filed on April 28, 2017. The original assignee was Rambus Inc., with the current assignee listed as Signal LLP. The inventors are Kyung Suk Oh and Ian P. Shaeffer.

Abstract:
A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs.

Plain-Language Overview of Independent Claims:

• Claim 1 (Integrated Circuit Device): This claim describes an integrated circuit device (e.g., a memory controller) that controls a Dynamic Random Access Memory (DRAM). The device includes a first interface to send a write command to the DRAM (indicating data will be received), a chip-select signal (to make the DRAM respond), and commands to store a digital control value in a DRAM register. This digital control value specifies a termination impedance value for the DRAM's data interface. The impedance is connected before the write data arrives (based on a set time after the write command) and disconnected after the write data is received. The device also has a second interface to send the actual write data to the DRAM's data interface.

• Claim 11 (Method of Control): This claim describes a method for controlling a DRAM. The method involves transmitting a write command to the DRAM, along with a chip-select signal to ensure the DRAM responds. It also includes transmitting commands to store a digital control value in a DRAM register. This digital control value dictates the termination impedance that the DRAM should apply to its data interface in response to the chip-select signal and write command. Crucially, the termination impedance is connected to the data interface at a predetermined time before the write data arrives and is then disconnected after the write data has been received. Finally, the method includes transmitting the write data to the DRAM's data interface.

Litigation Information:
According to the patent's Google Patents page, there is active litigation related to this patent. US cases have been filed in the Texas Western District Court (case 7:26-cv-00095) and the Texas Eastern District Court (case 2:26-cv-00093), both in 2026. There is also mention of the first worldwide family litigation filed. No specific CAFC 2026 dockets were found for patent 10056902 in the search results.

As of April 26, 2026, the Google Patents page for US patent 10056902 indicates active litigation.

Known litigation involving US patent 10056902 includes:

• Jurisdiction: Texas Western District Court

  • Case Number: 7:26-cv-00095
  • Filing Date: 2026 (specific day and month not provided in the snippet)
  • Status/Outcome: Active litigation.

• Jurisdiction: Texas Eastern District Court

  • Case Number: 2:26-cv-00093
  • Filing Date: 2026 (specific day and month not provided in the snippet)
  • Status/Outcome: Active litigation.

Additionally, the Google Patents page mentions that the "First worldwide family litigation filed". However, specific details such as plaintiff(s), defendant(s), jurisdiction, case number, and filing date for this worldwide litigation are not provided in the available information.

No specific CAFC 2026 dockets were found for patent 10056902. Similarly, a PACER search for "US10056902" did not return specific litigation details beyond what was already indicated on the Google Patents page.

Proceedings overview

There is no PTAB activity on file for US patent 10056902. This means all claims of the patent are currently untested by AIA trial proceedings, which offers a defendant a wide-open defensive posture regarding validity challenges at the PTAB.

Strategic summary

All twenty claims of US10056902 remain untested by PTAB review. Therefore, there are no canceled, sustained, or narrowed claims as a result of AIA trial proceedings. The estoppel landscape is entirely open; a defendant is not barred by § 315(e)(2) from raising any prior-art ground. There are no pattern signals of repeated petitioner filings or aggressive appeals by the patent owner at the PTAB.

Recommended next steps

As there is no PTAB activity on file for US10056902, the absence of IPRs, PGRs, or CBMs means that a defendant has the full spectrum of prior art grounds available for a potential PTAB challenge. If facing assertion of this patent, exploring an IPR petition should be considered, as the patent's validity has not yet been scrutinized in an AIA trial.

Inventors

• Kyung Suk Oh (Rambus Inc.)
• Ian P. Shaeffer (Rambus Inc.)

Both inventors appear to have remained with Rambus Inc. for some time after the 2017 filing date of US10056902B2, based on their continued inventorship on later patents assigned to Rambus Inc. (e.g., US10270442B2 filed in 2018, US10651849B2 filed in 2019, US10944400B2 filed in 2020, and US11349478B2 filed in 2020, all of which share the same priority date as US10056902B2). This does not suggest an unusual pattern of inventors departing the original assignee.

Original assignee

Rambus Inc. was the original assignee. Rambus is a company that designs, develops, and licenses a wide range of semiconductor products and intellectual property, including memory interface technologies. They ship products embodying the claims, specifically in the area of high-speed signaling and memory controllers. Rambus Inc. is an actively operating company.

Assignment timeline

No recorded assignments for US patent 10056902 were found on the USPTO Assignment Center search portal using the patent number. Google Patents, however, indicates two assignment events:

• 2018-04-25 / Recorded 2018-04-25 - (No Reel/Frame information available on Google Patents)

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: OH, KYUNG SUK, SHAEFFER, IAN P.
  • Assignee: RAMBUS INC.
  • Context: This appears to be the initial assignment from the individual inventors to the original corporate assignee, Rambus Inc., confirming Rambus's ownership before the patent issued.

• 2025-10-15 / Recorded 2025-10-15 - (No Reel/Frame information available on Google Patents)

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: RAMBUS INC.
  • Assignee: SIGNAL LLP
  • Context: This is a transfer of ownership from the original assignee, Rambus Inc., to Signal LLP. This event is listed in Google Patents as a reassignment and indicates a change in ownership.

Without specific reel/frame numbers from USPTO, a full detailed record of the correspondents cannot be established at this time.

Timeline diagram

timeline
    title Ownership of US 10056902
    2017 : Filed by Rambus Inc
    2018 : Inventors to Rambus Inc
         : Issued to Rambus Inc
    2025 : Assigned to Signal LLP
    2026 : Litigation filed

NPE / troll-pattern signals

1. Shell-entity transfer — unclear. The transfer from Rambus Inc. to Signal LLP in 2025-10-15 suggests a potential shell entity. However, without further information on Signal LLP's business activities, physical address, or legal structure (e.g., if it's a registered-agent service address, or a single-member LLC), it's difficult to definitively classify it as a shell entity.

2. Known asserter in the chain — unclear. Signal LLP is not immediately recognizable as a high-frequency NPE from commonly referenced lists (Acacia Research Corp, Marathon Patent Group, etc.). Further investigation into Signal LLP would be needed to determine if they are a known asserter.

3. Repeat correspondent across the chain — not present. Due to the lack of reel/frame information from Google Patents, specific correspondent details for the recorded assignments are unavailable at this time. Therefore, it's not possible to identify repeat correspondents.

4. Cascading transfers — not present. There is only one transfer event recorded post-issuance (Rambus Inc. to Signal LLP) on 2025-10-15, which does not constitute cascading transfers.

5. Pre-litigation transfer — present. The patent was assigned to Signal LLP on 2025-10-15, and litigation was filed in Texas Western District Court (case 7:26-cv-00095) and Texas Eastern District Court (case 2:26-cv-00093) in 2026. This transfer occurred within six months of the litigation filing, specifically about five months prior to the likely filing of the lawsuits (assuming early 2026 filing dates based on the case numbers).

6. Bankruptcy fire-sale — not present. Rambus Inc. is an operating company and there is no indication of bankruptcy in the assignment record or other provided information.

7. Privateering — unclear. While the transfer from an operating company (Rambus Inc.) to an entity like Signal LLP, followed by litigation, could be indicative of privateering, there is no direct evidence (e.g., SEC filings or specific reporting) to confirm that Signal LLP is asserting on Rambus Inc.'s behalf against competitors.

8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at a known defensive aggregator.

Verdict

NPE — moderate confidence. The primary signal supporting this verdict is the pre-litigation transfer of the patent from Rambus Inc. to Signal LLP on 2025-10-15, which occurred approximately five months before the patent was involved in litigation in Texas in 2026. This timing suggests the transfer may have been arranged to facilitate assertion. The nature of "Signal LLP" also hints at a potential shell entity, though this remains unclear without further details.

Verification: https://assignmentcenter.uspto.gov/

Most Relevant Prior Art for US Patent 10056902

To identify the most relevant prior art, I will refer to the "Cited by" section of US Patent 10056902 on Google Patents, which lists the patents and other publications that have cited US10056902. However, the request asks for prior art for 10056902, meaning it is citing prior art. I will therefore look at the "Prior art citations" section from the patent itself.

Unfortunately, I cannot directly access or "search within" the USPTO database or Google Patents in real-time to list the specific prior art cited by US10056902, as I do not have direct access to that function. The "Prior art keywords" and "Prior art date" sections on the Google Patents page provide high-level information but do not list specific patent numbers and their details. The provided patent text includes a "CROSS REFERENCE TO RELATED APPLICATIONS" section which lists a chain of continuation applications that eventually lead back to U.S. patent application Ser. No. 11/422,022, filed Jun. 2, 2006 (issued as U.S. Pat. No. 7,486,104), but these are not considered "prior art" in the traditional sense of anticipating the claims, rather they are part of the patent family.

Without direct access to the "Prior Art Citations" section that would typically be found on a patent document from the USPTO or a detailed Google Patents view, I cannot provide a comprehensive list of specific prior art references, their publication/filing dates, descriptions, and which claims they potentially anticipate.

Therefore, I must explicitly state that I do not have the requisite information to complete this part of the task with high confidence.

To analyze the obviousness of US patent 10056902 under 35 U.S.C. § 103, we need to identify combinations of prior art references that predate the patent's priority date of June 2, 2006, and explain why a person having ordinary skill in the art (PHOSITA) would have been motivated to combine them to arrive at the claimed invention. The independent claims, Claim 1 (integrated circuit device) and Claim 11 (method of control), are the primary focus.

Elements of Independent Claims (Claims 1 and 11)

The core elements of the independent claims revolve around a memory control component (or method of controlling) that interacts with a DRAM and manages its on-die termination (ODT) during write operations. Key features include:

1. Memory Controller/IC Device: An integrated circuit device configured to control a DRAM.
2. Transmission of Commands: Transmitting a write command, a chip-select signal, and one or more commands to store a digital control value in a DRAM register.
3. Programmable Termination Impedance: The digital control value specifies a value of a termination impedance.
4. Conditional ODT Coupling: The DRAM couples this termination impedance to its data interface in response to the chip-select signal and the write command.
5. Timed ODT Application/Decoupling: The termination impedance is coupled to the data interface prior to the reception of write data (according to a predetermined time after the write command) and decoupled from the data interface after the reception of the write data.
6. Write Data Transmission: Transmitting the actual write data to the DRAM's data interface.

The patent itself describes a "prior-art memory system 100" in FIG. 1, which employs a single on-die termination scheme where the memory controller asserts a termination control signal for non-selected memory modules during write operations and deasserts it for the selected module. This background highlights the known concept of ODT and its control by a memory controller.

Identification of Prior Art References

Given the priority date of June 2, 2006, we look for prior art that teaches the elements of the claims, particularly programmable ODT, control via commands, and dynamic timing of ODT during write operations.

The search results provide excellent prior art, particularly regarding DDR2 and DDR3 SDRAM specifications and technical notes. The relevant publications and information include:

• DDR2 SDRAM Standard (JEDEC JESD79-2): Published in September 2003, this standard formalized the first commercial implementation of On-Die Termination (ODT).
• "New Function of DDR2 SDRAM - On Die Termination (ODT)" (Digchip): This technical note, though its specific publication date is listed as April 15, 2007, describes ODT as a feature added to DDR2 SDRAM, indicating it was understood and implemented prior to 2006. It explicitly states that DDR2 SDRAM embeds termination resistors, and the DRAM controller can use an ODT control pin to set the termination resistance (e.g., ON and OFF) and select impedance values (50Ω, 75Ω, 150Ω) via the Extended Mode Register Set (EMRS). It also discusses how ODT is used during write operations, where the DDR2 SDRAM (as the receiving end) has its ODT pin high to open the internal termination resistor.
• Micron Technology Technical Note TN-47-02 (referenced in Digchip's "TECHNICAL NOTE"): Discusses DDR2 features, including ODT. It mentions JEDEC identified ODT values of 75 ohms and 150 ohms, and later added 50 ohms as an optional support. It shows an "Extended Mode Register Control for On-Die Termination" in Figure 1.
• Micron Technology Technical Note TN-41-04: "DDR3 Dynamic On-Die Termination": While this document is dated March 2008, it explicitly discusses the new feature introduced with DDR3 as "dynamic on-die termination (ODT)" which "enables the DRAM to switch between HIGH or LOW termination impedance without issuing a mode register set (MRS) command." It states that if Rtt_Nom and Rtt_WR are enabled via the mode register, the DRAM changes termination from Rtt_Nom to Rtt_WR upon issuing the WRITE command, and back to Rtt_Nom when the WRITE burst is complete. This strongly suggests that dynamic ODT switching based on write commands and programmable values was a known concept or a natural evolution in DDR3, building upon DDR2 ODT.
• Wikipedia "On-die termination": States that ODT is controlled via a programmable configuration register in the DRAM by the DRAM controller. It further notes that ODT is turned on just before data transfer and shut off immediately after.
• Xilinx Answer Record 38623: "Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mbps?" This document, while addressing a specific issue, confirms that in DDR2, the ODT pin goes high at the same time the WRITE command is issued to the DRAM, enabling termination 2nCK after the WRITE command. It also describes issues with ODT being enabled "too late" and solutions involving adjusting CAS latency to enable termination "one clock cycle before the first rising edge of DQS". This clearly demonstrates the understanding and practice of timing ODT assertion relative to write commands and data reception in DDR2.

Obviousness Analysis

Based on the identified prior art, the elements of Claims 1 and 11 appear to be individually known and the combination would have been obvious to a PHOSITA before June 2, 2006.

1. Memory Controller/IC Device and Transmission of Commands:
It was well-known in the art to have a memory controller (IC device) that transmits write commands and chip-select signals to a DRAM. The DDR2 SDRAM standard (published September 2003) formalized the use of ODT within DRAMs. Furthermore, the Digchip technical note on DDR2 SDRAM clearly states that the "DRAM controller can use ODT to set the termination resistance simultaneously to each pin...ON and OFF".

2. Programmable Termination Impedance via Register:
The prior art clearly teaches programmable ODT values stored in DRAM registers. The DDR2 standard allowed selection of impedance values like 50Ω, 75Ω, or 150Ω, set in advance via the Extended Mode Register Set (EMRS). The Wikipedia entry on ODT explicitly mentions that the "DRAM controller manages the on-die termination resistance through a programmable configuration register that resides in the DRAM" and that "in DRAM, it is done by setting up the device's extended mode register with the proper ODT value."

3. Conditional ODT Coupling in Response to Commands:
The DDR2 architecture already incorporated ODT that could be dynamically enabled/disabled. For example, during a write operation, the receiving DDR2 SDRAM enables ODT by asserting the ODT pin high. This shows that ODT was coupled in response to control signals (like the ODT pin, which would be controlled by the memory controller in conjunction with a write command and chip-select). The Xilinx Answer Record for DDR2 explicitly states that "the ODT pin will always go high at the same time that the WRITE command is issued to the DRAM". This directly links the ODT activation to the write command.

4. Timed ODT Application/Decoupling Relative to Write Data:
This is a critical aspect of the claims. The prior art demonstrates that ODT was understood to be dynamically turned on "just before the data transfer and then shut off immediately after". More specifically, in DDR2, the ODT pin goes high with the WRITE command, enabling termination a predetermined time (e.g., 2nCK) after the WRITE command. The Xilinx document even discusses the problem of ODT being enabled "too late" leading to overshoot, and suggests solutions to enable ODT "one clock cycle before the first rising edge of DQS" (which carries the write data). This unequivocally teaches the concept of coupling ODT prior to write data reception according to a predetermined time after the write command, and the need to decouple it after reception. The DDR3 dynamic ODT (TN-41-04), although technically after the priority date, describes a natural evolution where ODT changes from a nominal value to a write-specific value upon a WRITE command and reverts after the burst, "without having to issue additional MRS commands". This demonstrates the continuous development and understanding of dynamically timed ODT.

Motivation to Combine:

A PHOSITA in memory system design would have been motivated to combine these known elements for several reasons:

• Improved Signal Integrity: The primary motivation for ODT itself is to improve signal integrity by minimizing reflections, overshoot, and crosstalk in high-speed data transfers. As data rates increased (e.g., with DDR2 and DDR3), optimizing ODT became even more critical.
• System Performance and Reliability: By precisely controlling the timing of ODT application and removal, especially during write operations, designers could prevent signal degradation (e.g., overshoot mentioned in Xilinx Answer Record) and improve signaling margins, leading to more reliable data transfer and potentially higher operating frequencies.
• Flexibility and Optimization: The ability to program ODT values via mode registers (EMRS in DDR2) provided flexibility to tune the termination for different system configurations and operating conditions. Combining this programmability with dynamic, command-triggered timing would allow for optimal termination settings for specific transaction types (e.g., write operations) without constant re-configuration or sacrificing performance. The desire to "optimize termination values for different loading conditions" is explicitly stated in the context of dynamic ODT.
• Efficiency: Dynamically switching ODT (e.g., turning it on only when needed for write data reception and off afterwards) would reduce power consumption and improve bus scheduling, as noted in the DDR3 dynamic ODT technical note. The prior art already suggests disabling ODT during idle periods to save power. Extending this to precisely time ODT around the actual data transfer window during a write operation is a logical step.

Therefore, a PHOSITA, faced with the challenges of maintaining signal integrity and optimizing performance in high-speed DRAM systems (like DDR2 and the emerging DDR3), would have found it obvious to combine the known concepts of memory controllers, programmable ODT values set in DRAM registers via commands, and dynamic, command-triggered ODT timing (application before write data and removal after write data) to achieve the benefits of improved signal integrity, reliability, and efficiency.

For example, a PHOSITA combining the DDR2 SDRAM ODT implementation (programmable values via EMRS, ODT pin control by controller for write operations) with the common understanding that ODT should be "turned on just before the data transfer and then shut off immediately after", and further informed by issues of late ODT activation during DDR2 write cycles, would be motivated to develop a memory controller that transmits commands to set the ODT value in a register and then precisely times the ODT assertion and deassertion relative to the write command and subsequent data transfer.