Invalidity dossier
US 7670896
Method and structure for reducing floating body effects in MOSFET devices
Current assignee: GlobalFoundries Inc
Added 9/23/2026, 3:15:13 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 7,670,896 B2
Title: Method and structure for reducing floating body effects in MOSFET devices
Source: https://patents.google.com/patent/US7670896/en (excerpted; consult source for omitted text)
Identifiers and dates (from supplied text): Application US 11/560,412; filed and priority date 2006-11-16; published as US 2008/0116514 A1 on 2008-05-22; granted and published as US 7,670,896 B2 on 2010-03-02. Inventors: Huilong Zhu and Qingqing Liang. Original assignee: International Business Machines Corp.; current assignee listed as GlobalFoundries Inc. Legal status listed as "Expired – Fee Related," with adjusted expiration 2027-12-08. The text also notes later priority filings in CN (2007-09-30) and JP (2007-10-25).
Purpose and plain-language scope: The title states the invention concerns reducing floating body effects in MOSFET devices. The supplied prior-art keywords — source, forming, source region, cavity, layer — and the classifications (e.g., H10D30/6708, "preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region"; H10D62/021, "forming source or drain recesses by etching e.g. recessing by etching and then refilling"; H10D64/256, recessed source/drain electrodes) indicate a fabrication method in which a cavity is formed and a source region is created to address floating body behavior. Beyond these indicators, the excerpt does not include the claims, abstract, or detailed description, so the specific structural and process limitations are not established here.
What the excerpt does not establish: No claim language, abstract, embodiments, or figures are present in the supplied text. The scope, novelty, and validity of the claims cannot be assessed. Assignments listed (IBM; GlobalFoundries U.S. 2 LLC; GlobalFoundries Inc.) are described in the source as reassignments, but no analysis of ownership or legal effect is undertaken here. Per instructions, litigation, validity, and prior-art analysis are excluded. Legal-status and date entries are noted as assumptions in the source, not legal conclusions.
Generated 10/1/2026, 9:51:42 PM
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Litigation summary
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Proceedings on file (0)
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No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
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Obviousness
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Extensions
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Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.