Invalidity dossier

US 7536473

General input/output architecture, protocol and related methods to implement flow control

Current assignee: Intel Corp

Added 9/23/2026, 8:04:52 PM

At a glanceNo PTAB challengesNo litigation on file

Active provider: DeepSeek · deepseek-flash

Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Overview — US7536473B2 (concise, ≤400 words)

Title: General input/output architecture, protocol and related methods to implement flow control.

Patent number / kind: US7536473B2. Application: US10/227,601. Other version: US20030158992A1.

Assignee: Intel Corp (original assignee: Intel Corp). Inventors: Jasmin Ajanovic, David Harriman, Blaise Fanning, David M. Lee.

Dates (from the supplied record): Priority date 2001-08-24; filing date 2002-08-23; US20030158992A1 published 2003-08-21; patent granted/published 2009-05-19. Status shown as Expired – Lifetime, adjusted expiration 2025-03-01.

Purpose (per the source's Definitions): Embodiments "generally relate to the field of general input/output (GIO) bus architectures and, more particularly, to an architecture, protocol and related methods to implement flow control between elements within a GIO bus architecture." The background notes that computing appliances (computers, servers, networking switches and routers, wireless communication devices, etc.) comprise elements such as processors, memory systems, input/output interfaces and peripherals, and that a general purpose input/output (GIO) bus has long been used to let these disparate elements communicate. The PCI bus standard is described as defining a multi-drop, parallel bus architecture interconnecting chips, expansion boards, and processor/memory subsystems in an arbitrated fashion.

Plain-language scope (as far as the supplied excerpt establishes): The patent concerns an architecture, protocol, and methods for controlling the flow of data between elements on a general input/output bus. Google Patents' "prior art keywords" for this record are flow control, buffer, credits, interface, and gio; classifications include G06F13/00 and G06F13/12 (peripheral program control via channel/peripheral processor), G06F13/382–13/385 (universal interface adapter), G06F13/4027, G06F13/405–13/4059 (bus bridges, synchronising, buffers/speed matching), G06F13/42 (bus transfer protocol, handshake, synchronisation), and H04L47/10 and H04L47/30 (flow control/congestion control, including buffer occupancy at either end). A classification such as H04L47/30 suggests buffer-occupancy-based flow control, but the excerpt supplies no claim text, so claim scope is not shown.

Source: https://patents.google.com/patent/[US7536473](/patent/US7536473)/en

What the excerpt does not establish: It provides no claims, full description, drawings, or cited prior art. The classification titles, "prior art keywords," and litigation/continuation entries are database metadata, not findings; legal status and priority are expressly assumptions. No litigation, ownership, validity, or prior-art conclusions are drawn here.

Generated 10/1/2026, 9:41:38 PM

Cases on file (0)

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Litigation summary

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Proceedings on file (0)

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AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.

No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.

PTAB challenges

AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.

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Assignment history

Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.

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Prior art

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Obviousness

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Extensions

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Derivative works

Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.

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