Invalidity dossier
US 7490225
Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number
Current assignee: Sun Microsystems Inc
Added 9/23/2026, 12:34:28 PM
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Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US 7,490,225 B2
Title: Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number
Patent number / application: US 7,490,225 B2; Application US 11/555,258. A prior publication exists as US 2007/0198984 A1.
Inventors: John Gregory Favor; Christopher P. Nelson. Current assignee (as listed): Sun Microsystems Inc.
Key dates (as listed): Priority date 2005-10-31; filing date 2006-10-31; publication date 2009-02-10 (grant). Anticipated expiration 2026-10-31.
Purpose. The patent concerns microprocessors having multiple processing units — specifically a master processor and a coprocessor — and a synchronized register renaming method. A master processor sends an operation (register or memory) to the coprocessor with an identifier (e.g., an index into a scheduler table in the master processor); the coprocessor schedules and executes it and notifies the master upon completion using that identifier. Resources allocated in the coprocessor are associated with and looked up through the identifier.
Plain-language scope. To keep the master from overrunning the coprocessor, the master is allocated a predetermined number of outstanding operations and/or a number of coprocessor resources. The master tracks those outstanding operations/resources and stalls when the count reaches its credited apportionment. The number of resources released per coprocessor cycle for the master's use is limited to a predetermined limit (set to the number of resources the master can allocate in one coprocessor cycle in the described embodiment). The coprocessor may maintain an actual resource allocation map and an external (shadow) map, implemented as bit vectors, so its view matches what the master sees. Related provisional applications (Ser. Nos. 60/731,967; 60/757,240) and non-provisional applications (Ser. Nos. 11/555,263; 11/555,253) are incorporated by reference.
What the excerpt does not establish. It shows classifications and figures but omits the full claims, detailed description, and reference numerals; it does not establish claim scope, prosecution history, validity, ownership transfers, litigation, or prior art beyond the cited related applications. The legal status shown is expressly an assumption, not a legal conclusion.
Generated 10/1/2026, 9:53:32 PM
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Prior art
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