Invalidity dossier

US 6614796

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

Current assignee: Avago Technologies International Sales Pte Ltd

Added 9/23/2026, 4:27:31 PM

At a glanceNo PTAB challengesNo litigation on file

Active provider: DeepSeek · deepseek-flash

Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Overview — US6614796B1

Title: Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

Patent number: US6614796B1
Application number: US09/195,846
Inventors: Alistair D. Black; Kurt Chan
Original assignee: Gadzoox Networks Inc
Current assignee (as listed): Avago Technologies International Sales Pte Ltd
Prior art date (as listed): 1997-01-23
Filing date: 1998-11-19
Publication/grant date: 2003-09-02
Legal status (as listed): Expired – Fee Related; anticipated expiration 2017-01-23

Purpose and plain-language scope

The source text supplies the title and classification data, but the substantive description and claims are omitted from the excerpt. From the title and classifications alone, the patent concerns Fibre Channel arbitrated loop (FC-AL) switching circuitry. Its stated aim is to increase bandwidth without a significant increase in cost, and the circuitry is described as "bufferless." The prior-art keywords indexed by the source — port, loop, node, coupled, switch — indicate a switching architecture in which ports and nodes are coupled to a loop.

Classification places the subject matter under H04L12/4637 ("Interconnected ring systems"), with further classes for bus networks, bus arbitration (H04L12/40084), and packet switching elements adapted for storage area networks (H04L49/356).

The source also lists related later applications claiming priority from this filing and assignment records (Gadzoox to Broadcom in 2003; Broadcom to Avago Technologies General IP in 2017). These are reported as-is; no analysis of them is offered here.

What the excerpt does not establish

Because the description and claims were not included in the supplied text, this overview cannot state the actual claimed invention, the specific bufferless switch architecture, how bandwidth is increased, or what distinguishes the claims from prior art. No litigation, validity, or prior-art conclusion is drawn. Claim scope should be read from the full patent document.

Source: https://patents.google.com/patent/[US6614796](/patent/US6614796)/en

Generated 10/1/2026, 9:50:48 PM

Cases on file (0)

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Litigation summary

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Proceedings on file (0)

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AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.

No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.

PTAB challenges

AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.

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Assignment history

Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.

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Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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Obviousness

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Extensions

Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.

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Derivative works

Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.

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