US 5956597

Patent Overview: US 5,956,597

Title: Method for producing SOI & non-SOI circuits on a single wafer

Patent number: US 5,956,597 A

Application number: US 08/929,730

Inventors: Toshiharu Furukawa; Mark C. Hakey; Steven J. Holmes; David V. Horak; Paul A. Rabidoux

Original assignee: International Business Machines Corp. (The source also lists a current assignee of Google LLC, but per instructions I make no representation as to the accuracy of ownership.)

Key dates (as listed): Priority/filing date 1997-09-15; publication/grant 1999-09-21; anticipated expiration 2017-09-15; status listed as "Expired – Lifetime."

Purpose: The patent addresses fabricating integrated circuits, specifically forming Silicon On Insulator (SOI) devices and non-SOI (bulk CMOS) devices on the same wafer. SOI devices offer lower power consumption, lower parasitic capacitance (faster switching), and greater resistance to ionizing radiation, making them popular for memory support and CPU circuits. However, SOI devices have limitations: charges can accumulate during transistor operation, shifting threshold voltage (V_T); the SOI formation process yields more defective circuits than non-SOI processes (defects arising during formation of the electrically insulating region); and some defect-sensitive applications, such as DRAM, do not work well with SOI. The described SOI formation involves heating the wafer to roughly 650–750 °C, implanting large oxygen quantities below the surface, then heating to approximately 1350 °C to react implanted oxide with silicon to produce SiO₂.

Plain-language scope: According to the supplied text, a "stress-reducing region" formed on a wafer allows standard bulk CMOS (non-SOI) devices and SOI devices to be reliably fabricated on the same wafer; the high-stress interface typically existing between SOI and non-SOI regions is transferred to a region where stress is reduced and relaxed. The text also states a coplanar wafer surface can be maintained where a wafer includes both bulk CMOS and SOI devices, and mentions Shallow Trench Isolation (STI) and Chemical Mechanical Polish (CMP). The excerpt includes only the beginning of FIG. 1's description.

What the excerpt does not establish: It provides no claim language, no complete figure descriptions, no detailed process steps/embodiments, no prior-art references, and no examples. Claim scope, limitations, and dependencies therefore cannot be stated.

Source: https://patents.google.com/patent/US5956597/en