US 5615140

Patent Overview — US5615140A

Title: Fixed-point arithmetic unit
Source: https://patents.google.com/patent/[US5615140](/patent/US5615140)/en

Bibliographic data (as supplied): Inventor Toshihiro Ishikawa; original assignee Matsushita Electric Industrial Co., Ltd. (current assignee listed as Panasonic Holdings Corp); priority date 1994-02-14; filing date 1995-02-07; publication/grant date 1997-03-25; application US08/385,121; status "Expired – Lifetime," with anticipated expiration 2015-02-07.

Purpose: The invention addresses fixed-point arithmetic in digital signal processors (DSPs), e.g., in digital portable telephones, where significant digits are sometimes varied to match required calculation accuracy. It notes prior art JP-A-2-293928 (variable operational word length). The stated problems are superfluous operation: a 16-bit data address register addressing a memory of only 256 words operates 8 unnecessary bits, and similarly a 16-bit program counter addressing a 256-word instruction memory.

Stated objects: To provide an arithmetic unit operable on only the significant bits less than its bit width, reducing power in the arithmetic circuit and its input/output registers and improving calculation speed; and to provide an address generator and program controller that can reduce the maximal-address bit width to match the installed memory.

Plain-language scope (from the excerpted text): An arithmetic unit has arithmetic means, operational-word-length storage storing a significant digit, and control means inhibiting the arithmetic means from operating portions unnecessary for calculating significant bits. Embodiments include an arithmetic and logic circuit with first/second input registers, a third output register, and a register controller causing only significant bits to be stored. The control means may block carry propagation into unnecessary portions (e.g., the most significant bit and above). Related claims described cover an address generator (address register, increment register, adder, installed address width storage) and a program controller (instruction memory, program counter, constant generator, adder).

What the excerpt does not establish: The complete claim set, full specification, drawing contents, and the omitted remainder of the description are not available in the supplied text; claim wording, dependencies, and exact limitations may therefore differ. The excerpt also does not establish any legal conclusions, prosecution history, or validity.