Prior art — US Patent 9972381

Here's an analysis of the most relevant prior art for US patent 9972381, based on the examiner-cited patent documents from its Google Patents page. As the full claims of US9972381 were not provided in the authoritative text, the anticipation analysis for each cited patent will be based on the abstract and description of US9972381, with an explicit acknowledgment of this limitation.

The critical priority date for US9972381 is September 30, 2005. Prior art for purposes of 35 U.S.C. § 102 would generally include any patent or publication publicly available before this date.

Here are the details for each cited patent:

Cited Prior Art Patents

1. US6278632B1

Full Citation: US6278632B1, "Flash memory having multiple banks for improving random access capability and system performance," issued to Masuoka et al. on August 21, 2001.
Publication/Filing Date: Issued: 2001-08-21; Filed: 1999-07-27.
Brief Description: This patent describes a flash memory device with multiple memory banks to improve random access capability and system performance. It aims to reduce average access time by allowing operations to be performed in parallel across different banks. For example, while one bank is busy with a program or erase operation, another bank can be accessed for a read operation.
Potential Anticipation for US9972381: This patent potentially anticipates aspects of US9972381 related to using multiple memory banks for concurrent operations, particularly those described in the abstract and background of US9972381 as "a memory architecture for improving the speed and/or capacity of semiconductor Flash memory devices." US9972381 explicitly discusses memory devices having multiple memory banks (e.g., FIGS. 1A, 1B, 1C, 2A) and performing concurrent operations like read-while-write or read-while-erase (e.g., FIGS. 8A, 8B, 8C). The concept of improving performance through multi-bank architecture for concurrent operations appears to be directly addressed by US6278632B1. Without the specific claims of US9972381, it is difficult to determine exact anticipation, but the core idea of parallel operations across multiple flash memory banks is present.

2. US6742080B1

Full Citation: US6742080B1, "Multi-bank memory architecture for facilitating pipelined operations of different-sized data in an interleaved data transfer environment," issued to Cernea et al. on May 25, 2004.
Publication/Filing Date: Issued: 2004-05-25; Filed: 2003-09-02.
Brief Description: This patent discloses a multi-bank memory architecture, such as in a flash memory system, designed to facilitate pipelined operations. It particularly focuses on handling different-sized data in an interleaved data transfer environment, allowing for more efficient data processing and improved throughput by overlapping operations between memory banks.
Potential Anticipation for US9972381: Similar to US6278632B1, this patent also addresses a multi-bank memory architecture for enhanced performance through pipelined operations. US9972381 mentions that its control module (e.g., 126 in FIG. 1B) can be "configured to perform or execute two operating processes or threads, so that serial data link interface 120 can exchange data with memory banks 122 and 124 in a pipelined fashion." This suggests a direct overlap in the concept of pipelined operations across multiple memory banks to increase efficiency. The "different-sized data" and "interleaved data transfer environment" aspects might represent specific implementations not explicitly detailed in US9972381's general description, but the foundational principle of pipelining in multi-bank memory is comparable.

3. US6850450B2

Full Citation: US6850450B2, "Non-volatile memory device having plural banks to perform program operation," issued to Kageyama et al. on February 1, 2005.
Publication/Filing Date: Issued: 2005-02-01; Filed: 2003-03-27.
Brief Description: This patent describes a non-volatile memory device, such as a flash memory, which includes multiple memory banks. The key feature is the ability to perform a program operation in one bank while another operation (e.g., a read operation or another program operation) is ongoing in a different bank, thus enhancing the overall throughput and reducing the busy time of the memory device.
Potential Anticipation for US9972381: This patent is highly relevant as it specifically focuses on non-volatile memory (like Flash memory in US9972381) with plural banks to perform concurrent program operations. US9972381 details "concurrent program" operations (e.g., FIG. 8B, "page program" command 812 being performed concurrently with a "page read" command 810). The general concept of performing a program operation in one bank while another operation proceeds in a different bank is explicitly covered. The specific mechanisms for achieving this might differ, but the overall functional goal of parallel program operations in a multi-bank non-volatile memory is anticipated.

4. US6919757B2

Full Citation: US6919757B2, "Method and apparatus for concurrent erase and program operations in a flash memory system," issued to Arai et al. on July 19, 2005.
Publication/Filing Date: Issued: 2005-07-19; Filed: 2002-06-25.
Brief Description: This patent provides a flash memory system capable of concurrently performing erase and program operations. It describes how such operations can be managed across different memory blocks or banks to avoid conflicts and maximize efficiency.
Potential Anticipation for US9972381: This patent is also highly relevant, as it directly addresses "concurrent erase and program operations" in a flash memory system. US9972381 lists "program while erase" and "erase while program" among its envisioned concurrent operations (e.g., in the discussion of FIGS. 8A-8C). The abstract of US9972381 mentions "concurrent operations," and the detailed description confirms this functionality. Therefore, the fundamental concept of performing program and erase operations concurrently in a flash memory system is anticipated by US6919757B2.

5. US6987702B2

Full Citation: US6987702B2, "Flash memory system with serial access," issued to Chen et al. on January 17, 2006.
Publication/Filing Date: Issued: 2006-01-17; Filed: 2004-03-24.
Brief Description: This patent describes a flash memory system that utilizes a serial interface for data access. It aims to reduce pin count and improve signal integrity, addressing issues commonly associated with parallel interfaces at high operating frequencies.
Potential Anticipation for US9972381: This patent is extremely relevant because US9972381 prominently features a "serial data link" and "serial interface" as a core aspect of its invention, aiming to overcome the limitations of parallel interfaces (e.g., cross-talk, signal skew, pin count). US9972381 states, "At least one advantage of a serial interface is a low-pin-count device with a standard pin-out...". The abstract of US9972381 explicitly mentions "a serial data link that transfers serial input data to the memory" and "serial data output port." US6987702B2's focus on a "flash memory system with serial access" directly anticipates this fundamental aspect of US9972381. The details of the serial protocol or specific control signals might differ, but the broad concept of a serial interface for flash memory to achieve reduced pin count and improved signal quality is covered.

6. US7020005B2

Full Citation: US7020005B2, "Flash memory with a flexible architecture," issued to Roohparvar on March 28, 2006.
Publication/Filing Date: Issued: 2006-03-28; Filed: 2003-09-02.
Brief Description: This patent discloses a flash memory device with a flexible architecture that allows for various operating modes and configurations. This flexibility might include adaptive block sizes or configurable interfaces to optimize performance for different applications.
Potential Anticipation for US9972381: US9972381 emphasizes "enhanced flexibility for system design" and mentions various configurations like "dual port configuration" (FIG. 1A) and "single port configuration" (FIG. 1B) with a "virtual multiple link" feature. While "flexible architecture" is a broad term, it could encompass the adaptability of US9972381's serial interfaces and multi-bank access. The specific details of how "flexibility" is achieved would be crucial for a precise anticipation analysis. However, the general goal of a flexible memory device architecture to optimize usage aligns with aspects of US9972381.

7. US7072205B2

Full Citation: US7072205B2, "Serial interface flash memory," issued to Kwon et al. on July 4, 2006.
Publication/Filing Date: Issued: 2006-07-04; Filed: 2004-09-24.
Brief Description: This patent describes a flash memory device equipped with a serial interface. It focuses on the implementation and advantages of serial communication for flash memory, potentially covering aspects like command processing, data transfer, and status reporting via a serial link.
Potential Anticipation for US9972381: Similar to US6987702B2, this patent directly describes a "serial interface flash memory," which is a central theme of US9972381. US9972381 details a "fully serializes a single set of serial input and output pins which are SIP (Serial Input Port) and SOP (Serial Output Port) along with two control signals, IPE (Input Port Enable) and OPE (Output Port Enable)." The presence of a serial interface for flash memory to handle commands, addresses, and data is a strong point of overlap.

8. US7218556B2

Full Citation: US7218556B2, "Memory device with output control," issued to Oh et al. on May 15, 2007.
Publication/Filing Date: Issued: 2007-05-15; Filed: 2005-09-30.
Brief Description: This patent describes a memory device with output control, where the output of data can be managed using specific control signals. The abstract mentions a memory, a serial data link, and control circuitry to manage data transfer, including converting parallel data from the memory to serial output data. Notably, the filing date (2005-09-30) is the same as the priority date of US9972381. The inventors for US7218556B2 (Oh, Pyeon, Kim) are also the inventors for US9972381, and the title "Memory with output control" is very similar to "Memory with output control" for US9972381. This patent is likely a direct parent or sibling application, and thus its disclosure would likely be part of the same inventive entity's earlier work. It's listed as "Priority date 2005-09-30" on the US9972381 Google Patents page as well. This is a very strong candidate for internal prior art (i.e., part of the same inventive concept or family), rather than independent prior art.
Potential Anticipation for US9972381: Given the identical priority date and inventors, US7218556B2 is highly likely a direct parent or sibling application to US9972381, possibly from the same provisional application (US Provisional Application No. 60/722,368 filed on Sep. 30, 2005). Therefore, the contents of US7218556B2 are likely to be very similar or foundational to US9972381. If US9972381 claims priority to US7218556B2's underlying application, then US7218556B2 itself cannot anticipate US9972381 under § 102. However, if any claims in US9972381 are not supported by the earlier priority date of US7218556B2 (or its provisional), then US7218556B2's publication date would be prior art for those specific claims. Based on the abstract, the core concepts of serial data links, output control, and control circuitry for data transfer are highly consistent with US9972381.

9. US7254060B2

Full Citation: US7254060B2, "Non-volatile memory device," issued to Lee et al. on August 7, 2007.
Publication/Filing Date: Issued: 2007-08-07; Filed: 2004-03-05.
Brief Description: This patent describes a non-volatile memory device with improved data storage and retrieval capabilities. It may involve specific circuit designs or control mechanisms for efficient operation.
Potential Anticipation for US9972381: This patent, titled broadly as "Non-volatile memory device," could potentially anticipate any general aspects of non-volatile memory devices disclosed in US9972381 that are not specific to the serial interface or multi-bank concurrent operations. Without a more detailed abstract or claim set, it's difficult to pinpoint specific anticipation. However, the overall concept of an improved non-volatile memory device is a common goal shared by both.

10. US7330386B2

Full Citation: US7330386B2, "Serial flash memory and method of operating the same," issued to Park on February 12, 2008.
Publication/Filing Date: Issued: 2008-02-12; Filed: 2005-09-09.
Brief Description: This patent describes a serial flash memory device and a method for its operation. It likely details the architecture and operational sequences for reading, writing, and erasing data through a serial interface in a flash memory.
Potential Anticipation for US9972381: With a filing date of September 9, 2005, this patent predates the priority date of US9972381 (September 30, 2005) and directly addresses "Serial flash memory and method of operating the same." This makes it highly relevant prior art. US9972381's core innovation involves a serial interface for flash memory, including its operational methods. Therefore, US7330386B2 could potentially anticipate many aspects of US9972381's serial communication protocols, command sequences, and data transfer mechanisms, as well as the fundamental architecture of a serial flash memory device.

11. US7379344B2

Full Citation: US7379344B2, "Serial interface flash memory device and method of controlling the same," issued to Kim et al. on May 27, 2008.
Publication/Filing Date: Issued: 2008-05-27; Filed: 2006-03-31.
Brief Description: This patent describes a serial interface flash memory device and methods for controlling it. It likely covers the design of the serial interface, command handling, and how the memory controller interacts with the serial flash device.
Potential Anticipation for US9972381: This patent is another highly relevant piece of prior art, specifically titled "Serial interface flash memory device and method of controlling the same." This directly overlaps with the subject matter of US9972381. Although its filing date (2006-03-31) is after US9972381's priority date, its publication date (2008-05-27) is before the filing of US9972381 as a continuation. However, for anticipation under 35 U.S.C. § 102, the relevant date is generally its earliest effective filing date compared to the earliest effective filing date of US9972381. If US7379344B2's earliest priority date is before US9972381's priority date, it could anticipate. Without specific priority chain information for US7379344B2, we assume its filing date as its earliest date for this analysis. If its effective filing date is indeed 2006-03-31, then it would not anticipate claims of US9972381 that are supported by the Sep 30, 2005 priority date. However, it would be highly relevant for obviousness (35 U.S.C. § 103). The description of US9972381 explicitly covers "control communication between memory devices and controller itself" using SIP, SOP, IPE, OPE signals, which falls squarely within the title of US7379344B2.

12. US7430140B2

Full Citation: US7430140B2, "Multi-bank memory architecture for facilitating pipelined operations of different-sized data in an interleaved data transfer environment," issued to Cernea et al. on September 30, 2008.
Publication/Filing Date: Issued: 2008-09-30; Filed: 2004-05-24.
Brief Description: This patent is a continuation or related patent to US6742080B1, having the same title and inventors. It focuses on a multi-bank memory architecture that enables pipelined operations and handles different-sized data in an interleaved manner for efficient data transfer.
Potential Anticipation for US9972381: As a patent with a filing date of May 24, 2004, it predates the priority date of US9972381. It shares the same core subject matter as US6742080B1, concerning multi-bank memory architecture and pipelined operations. Therefore, it has similar potential for anticipating US9972381's features related to concurrent and pipelined operations across multiple memory banks. The explicit mention of "pipelined fashion" in US9972381 (e.g., control module 126 in FIG. 1B) indicates a direct overlap.

13. US7433230B2

Full Citation: US7433230B2, "Serial flash memory device and method of operating the same," issued to Park et al. on October 7, 2008.
Publication/Filing Date: Issued: 2008-10-07; Filed: 2005-09-19.
Brief Description: This patent describes a serial flash memory device and its operational methods, focusing on the commands and sequences for accessing and managing data within a flash memory through a serial interface.
Potential Anticipation for US9972381: With a filing date of September 19, 2005, this patent predates the priority date of US9972381 (September 30, 2005) and is directly titled "Serial flash memory device and method of operating the same." This makes it highly relevant prior art that could potentially anticipate many aspects of US9972381's serial interface, command processing (e.g., page read, page program, erase commands as shown in FIGS. 3A, 5A, 6A), and overall operation of a serial flash memory.

14. US7515471B2

Full Citation: US7515471B2, "Multiple independent serial link memory," issued to Oh et al. on April 7, 2009.
Publication/Filing Date: Issued: 2009-04-07; Filed: 2006-10-19.
Brief Description: This patent describes a memory device with multiple independent serial data links, where each link can communicate with any memory bank. It emphasizes concurrency and enhanced utilization. US9972381 explicitly states it is a continuation of a chain of applications, including this one ("U.S. application Ser. No. 11/583,354 filed on Oct. 19, 2006, now U.S. Pat. No. 7,515,471"). This patent also claims benefit of U.S. Provisional Application No. 60/722,368 filed on Sep. 30, 2005, the same provisional as US9972381.
Potential Anticipation for US9972381: As US9972381 is a continuation in the same patent family and claims priority to the same provisional application (60/722,368) as US7515471B2, US7515471B2 would not be considered prior art under 35 U.S.C. § 102 for any claims in US9972381 that are fully supported by the common priority date of September 30, 2005. If US9972381 contains new subject matter not disclosed in US7515471B2's underlying application or the common provisional, then the publication date of US7515471B2 (2009-04-07) could potentially be prior art for those specific, later-invented claims. However, given the nature of continuations, it is expected that US7515471B2's disclosure is largely foundational to US9972381. The abstract of US7515471B2 ("Multiple independent serial link memory") directly mirrors the core concepts of US9972381, especially the dual-port and quad-port configurations with independent serial data links (e.g., FIGS. 1A, 1C of US9972381).

15. US7652922B2

Full Citation: US7652922B2, "Multiple independent serial link memory," issued to Oh et al. on January 26, 2010.
Publication/Filing Date: Issued: 2010-01-26; Filed: 2005-12-30.
Brief Description: This patent describes a memory device with multiple independent serial data links and multiple memory banks, allowing for concurrent operations and improved data throughput. It explicitly claims benefit of U.S. Provisional Application No. 60/722,368 filed on Sep. 30, 2005, the same provisional as US9972381. US9972381 states it is a continuation-in-part of US11/324,023 (which issued as US7652922).
Potential Anticipation for US9972381: Similar to US7515471B2, US7652922B2 is a direct parent patent in the same family as US9972381, claiming priority to the same provisional application (60/722,368). Therefore, US7652922B2 generally would not anticipate claims of US9972381 that are supported by the common priority date of September 30, 2005. Its disclosure is likely a direct foundation for US9972381. The title "Multiple independent serial link memory" indicates it broadly covers the fundamental architecture of multiple serial links and independent operation with memory banks, which is a central feature of US9972381.

Summary of Potential Anticipation

Without the specific claims of US9972381, a precise claim-by-claim anticipation analysis is not possible. However, based on the general descriptions and abstracts:

Multi-bank concurrent operations: US6278632B1, US6742080B1, US6850450B2, US6919757B2, and US7430140B2 directly anticipate the concept of using multiple memory banks to perform concurrent or pipelined read, program, or erase operations in flash memory.
Serial Interface for Flash Memory: US6987702B2, US7072205B2, US7330386B2, and US7433230B2 broadly anticipate the use of a serial interface for flash memory devices to reduce pin count and improve data transfer characteristics. These are highly relevant to the core technical problem US9972381 aims to solve.
Parent/Sibling Applications: US7218556B2, US7515471B2, and US7652922B2 are likely part of the same patent family and share a common priority date with US9972381. Therefore, they are generally not "prior art" in the sense of anticipating claims that enjoy the benefit of that shared priority date. However, they are highly relevant for understanding the scope of the invention as it evolved through the continuation lineage. If US9972381 introduced new subject matter not present in the earlier applications and relied solely on its own filing date for those new claims, then these earlier-filed/published family members could potentially anticipate those specific new claims.

The most relevant independent prior art patents that explicitly disclose key features of US9972381 before its priority date include:

US6278632B1 (2001-08-21): Multi-bank flash memory for random access and performance.
US6742080B1 (2004-05-25) and US7430140B2 (2008-09-30, filed 2004-05-24): Multi-bank for pipelined operations.
US6850450B2 (2005-02-01): Multi-bank for concurrent program operations.
US6919757B2 (2005-07-19): Concurrent erase and program in flash memory.
US6987702B2 (2006-01-17, filed 2004-03-24): Flash memory system with serial access.
US7330386B2 (2008-02-12, filed 2005-09-09): Serial flash memory and method of operating.
US7433230B2 (2008-10-07, filed 2005-09-19): Serial flash memory device and method of operating.

These patents collectively show that the concepts of multi-bank flash memory, concurrent operations within multi-bank memories, and serial interfaces for flash memory were known in the art prior to the earliest priority date of US9972381. The novelty of US9972381, if any, would likely lie in the specific combination of these features, the particular control mechanisms (like IPE/OPE signals and echo signals for daisy-chaining), or other specific architectural details that distinguish its claims from these earlier disclosures.