Obviousness

The numbered claims for US9972381 are not provided in the supplied patent text. A comprehensive obviousness analysis under 35 U.S.C. § 103 requires evaluating each claim against prior art. Without the claims, a definitive assessment of obviousness is not possible.

However, based on the patent's abstract and detailed description, the invention relates to semiconductor memory devices, particularly Flash memory, incorporating serial data link interfaces, advanced control mechanisms, concurrent operations, and daisy-chain configurations. The priority date for US9972381 is September 30, 2005.

Assuming representative claims covering the main disclosed features (e.g., a serial data interface for Flash memory, input/output enable signals (IPE/OPE), daisy-chaining with echo signals (IPEQ/OPEQ), target device addressing in a serial chain, and concurrent multi-bank operations via serial links), an obviousness argument would typically identify prior art references disclosing these elements and a motivation to combine them.

To illustrate, a hypothetical obviousness argument could be structured as follows, focusing on combining known concepts in serial memory and Flash technology:

Identified Features of US9972381 from Description:

1. Serial data link interface for semiconductor memory (Flash memory specifically): The patent emphasizes using serial interfaces to reduce pin count and improve signal integrity at high speeds, particularly for Flash memory.
2. Input Port Enable (IPE) and Output Port Enable (OPE) signals: Control signals for enabling/disabling serial data input and output ports (SIP, SOP) respectively.
3. Daisy-chain cascading with echo signals (IPEQ, OPEQ): Serially connecting multiple memory devices, where each device echoes received IPE and OPE signals to the next device (IPEQ, OPEQ).
4. Unique device identifiers and target device addressing (TDA): Each device has a unique ID, and input data streams include a TDA. Devices parse the TDA to determine if they are the target, ignoring data if not, to save processing time.
5. Multi-bank memory with concurrent operations: Memory devices with multiple banks (e.g., Flash banks) that can perform concurrent operations (e.g., read while write) either through multiple serial links or a "virtual multiple link" configuration using a single serial link.
6. Serial-to-parallel and parallel-to-serial conversion: The serial link interface converts serial input data to parallel data for the memory bank and parallel data from the memory bank to serial output data.

Potential Prior Art Combinations for Obviousness:

Given the general knowledge in the field of memory devices and serial communication systems prior to September 30, 2005, a person having ordinary skill in the art (PHOSITA) would have been motivated to combine known elements to achieve the functionality described in US9972381.

Combination 1: Serial Interface for Flash Memory with I/O Control (Features 1, 2, 6)

• Reference A (Disclosing Serial Interface for Memory & Conversion): Many prior art patents and publications before 2005 discussed the benefits of serial interfaces for memory, particularly for reducing pin count and improving performance and signal integrity. For example, some patents describe general serial-to-parallel and parallel-to-serial conversion within memory devices to interface with internal parallel memory arrays.

• Reference B (Disclosing Enable Signals for Data Transfer): It was well-known in digital electronics to use enable signals to control data flow into and out of registers and ports. For instance, serial peripheral interface (SPI) and similar protocols often employed chip select (CS) or enable lines to gate data. Applying distinct input enable (IPE) and output enable (OPE) signals to control dedicated serial input (SIP) and output (SOP) ports for flexible data communication would be a straightforward design choice for a PHOSITA.

• Motivation to Combine: A PHOSITA facing the challenges of increasing Flash memory speed and density while managing pin count and signal integrity (as noted in the background of US9972381) would naturally seek to apply serial interfaces (Reference A) to Flash memory. To provide precise control over when a serial port receives or transmits data, integrating dedicated enable signals (Reference B) for input and output operations would be an obvious design decision, allowing the memory controller more flexibility, as highlighted in US9972381. The conversion between serial and parallel data streams (Reference A) is inherent to interfacing a serial link with a parallel memory core.

Combination 2: Daisy-Chained Serial Memory with Device Addressing and Echo Signals (Features 3, 4)

• Reference C (Disclosing Daisy-Chained Serial Devices): Daisy-chain configurations for serially connecting multiple devices were common in various electronic systems (e.g., SPI bus, JTAG, certain memory modules) prior to 2005. These systems often involved passing data or control signals down a chain.

• Reference D (Disclosing Unique Device Identifiers and Target Addressing): Methods for addressing individual devices in a multi-device serial bus were also well-established. This could involve unique device IDs and a target address field in the data stream, where non-target devices would forward or ignore data.

• Reference E (Disclosing Signal Echoing/Re-transmission in Serial Chains): To ensure signal integrity and proper synchronization over longer daisy chains, repeating or echoing control signals (e.g., clock, enable) to subsequent devices was a known technique.

• Motivation to Combine: When designing a scalable Flash memory system requiring increased capacity, a PHOSITA would consider daisy-chaining (Reference C) as an efficient way to expand memory without dramatically increasing the controller's I/O pins. To effectively manage data flow and commands to specific devices in such a chain, implementing unique device identifiers and target addressing (Reference D) is a necessary and obvious step. Furthermore, to maintain robust communication in a long serial chain, echoing control signals (Reference E) like IPE and OPE (from Combination 1) would be a logical extension to ensure reliable operation of downstream devices. The patent explicitly states "when devices are serially cascaded in a system they may further comprise output control ports that “echo” the received IPE and OPE signals to external devices. This allows the system to have point-to-point connected signal ports (e.g., SIP/SOP, IPE/IPEQ, OPE/OPEQ, SCLKI/SCLKO) to form a daisy-chain cascading scheme". This directly points to a known architectural choice for daisy-chaining to improve signal integrity and control.

Combination 3: Concurrent Multi-Bank Operations via Serial Links (Feature 5)

• Reference F (Disclosing Multi-Bank Flash Memory with Concurrent Operations): It was standard practice in Flash memory design to include multiple memory banks to enable concurrent operations (e.g., reading from one bank while programming another) to improve overall throughput. These operations were typically managed by an internal controller.

• Reference A (from Combination 1 - Serial Interface): Discloses the use of serial interfaces for memory access.

• Motivation to Combine: A PHOSITA seeking to maximize the performance of a serial Flash memory device (Reference A) would naturally combine it with known multi-bank architectures capable of concurrent operations (Reference F). The challenge would then be to expose and manage this concurrency through the serial interface. Whether by employing multiple independent serial links, or by intelligently arbitrating access to multiple banks through a single serial link (a "virtual multiple link" where the link is freed while a bank operation is busy, as described in US9972381), would be an obvious optimization. The patent mentions that the "control module 126 is configured to perform or execute two operating processes or threads, so that serial data link interface 120 can exchange data with memory banks 122 and 124 in a pipelined fashion". This pipelined or concurrent operation across multiple banks to improve utilization was a known objective in memory system design.

Conclusion

While specific claims are absent, the core inventive concepts of US9972381, such as serial interfaces for Flash memory, specialized I/O enable signals, daisy-chaining with echo signals, target device addressing, and concurrent multi-bank operations, represent a combination of elements that were individually known or readily apparent to a PHOSITA in the field of semiconductor memory design prior to September 30, 2005. The motivation to combine these elements would stem from well-recognized industry challenges: the need for higher speed, increased capacity, reduced pin count, and improved overall system performance and flexibility in memory devices, especially for Flash memory in mobile and high-data-rate applications, as explicitly stated in the background of the invention. The patent itself describes these features as improving "device utilization (e.g., bus utilization and core utilization)" and achieving "reduced pin count resulting from the virtual multiple link configuration". These are common engineering goals that would drive a PHOSITA to combine existing techniques.

Therefore, without the precise language of the claims, it is highly probable that claims encompassing these broadly described features would have faced obviousness challenges based on combinations of prior art teaching serial communication, multi-bank memory management, and daisy-chain architectures with addressing schemes.