Prior art — US Patent 9786510

The USPTO provides a Patent Public Search tool to search for patents and patent application publications, which is the appropriate resource for identifying prior art.

Upon reviewing US Patent 9,786,510, the following prior art references are identified from the "Cited By" and "Citations" sections of the patent document itself. Please note that a full anticipation analysis under 35 U.S.C. § 102 would require a detailed claim-by-claim comparison and expert opinion, which is beyond the scope of this response. The descriptions below offer a brief overview of the cited art's relevance to the general subject matter of US9786510.

Cited Prior Art for US9786510:

US20100148234A1
- Full Citation: US20100148234A1, "Subresolution silicon features and methods for forming the same"
- Publication Date: June 17, 2010
- Brief Description: This patent application describes methods for forming subresolution silicon features, which can include fins or similar structures, by using a hard mask layer and etching processes. It focuses on achieving fine feature sizes beyond the lithographic limit.
- Potential Anticipation (General): This could potentially anticipate aspects of claims related to the formation of fin-shaped structures, particularly the initial steps of defining and etching fins in a semiconductor substrate. Given that US9786510 discusses forming first and second fin-shaped structures and various etching processes, general methods for fin formation are highly relevant.
US20080157225A1
- Full Citation: US20080157225A1, "SRAM and logic transistors with variable height multi-gate transistor architecture"
- Publication Date: July 3, 2008
- Brief Description: This patent application discloses semiconductor devices with multi-gate transistor architectures, such as FinFETs, where fins may have variable heights to achieve different threshold voltages for various circuit blocks (e.g., SRAM and logic).
- Potential Anticipation (General): This reference is highly relevant to US9786510's objective of forming fin-shaped structures of "different heights and critical dimensions" in "different areas" to meet "specific electrical demands" like high voltage threshold (HVT) and low voltage threshold (LVT) areas. Claims 5 and 6 of US9786510, which relate to different fin heights protruding from the isolation structure or substrate, could be particularly implicated.
US8373238B2
- Full Citation: US8373238B2, "FinFETs with multiple Fin heights"
- Publication Date: February 12, 2013
- Brief Description: This patent describes FinFET devices having multiple fin heights. It details methods to achieve these varying heights, often involving selective etching processes and different masking steps, to optimize device performance for different circuit requirements.
- Potential Anticipation (General): Similar to US20080157225A1, this patent directly addresses the concept of creating FinFETs with varying fin heights. The methods described could anticipate aspects of US9786510's processes for forming fin-shaped structures of different heights, and thus impact claims related to achieving such variations. Claims 5 and 6 of US9786510 are again particularly relevant.
US20130149826A1
- Full Citation: US20130149826A1, "FinFETs with Multiple Fin Heights"
- Publication Date: June 13, 2013
- Brief Description: This is a patent application related to US8373238B2, disclosing FinFETs with multiple fin heights and methods for their fabrication. It aims to optimize FinFET performance by allowing for different fin heights across a single chip.
- Potential Anticipation (General): As a related application, its relevance and potential anticipation are similar to US8373238B2, focusing on the formation of FinFETs with varying fin heights to meet specific electrical requirements, which is a core aspect of US9786510.
US20120313169A1
- Full Citation: US20120313169A1, "Fin-FET device and method and integrated circuits using such"
- Publication Date: December 13, 2012
- Brief Description: This patent application describes FinFET devices and their fabrication methods, including integrated circuits utilizing such devices. It generally covers the structure and manufacturing of FinFETs.
- Potential Anticipation (General): This reference provides general background on FinFET devices and their manufacturing. Depending on the specific details of its claims, it could broadly anticipate elements of the FinFET structure or basic manufacturing steps described in US9786510.
US8669167B1
- Full Citation: US8669167B1, "Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices"
- Publication Date: March 11, 2014
- Brief Description: This patent focuses on techniques for engineering metal gates in FinFET devices to achieve multiple threshold voltages. While not directly about fin shape, the context is creating different electrical characteristics in FinFETs.
- Potential Anticipation (General): While not directly related to the "ladder-shaped cross-sectional profile" of the fins in US9786510, this patent addresses the broader problem of achieving varied electrical demands in different areas of a chip using FinFETs, which is an explicit goal of US9786510. If the methods described in US9786510 are used in conjunction with metal gate work function engineering, there could be an indirect relevance.
US8669615B1
- Full Citation: US8669615B1, "Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices"
- Publication Date: March 11, 2014
- Brief Description: This patent is a continuation or related to US8669167B1, also discussing metal gate workfunction engineering for multiple threshold voltage FinFETs.
- Potential Anticipation (General): Similar to US8669167B1, its relevance lies in the context of achieving varied electrical characteristics in different areas of a chip using FinFETs, which is a stated advantage of the fin structures created by US9786510.
US20140191323A1
- Full Citation: US20140191323A1, "Method of forming finfet of variable channel width"
- Publication Date: July 10, 2014
- Brief Description: This patent application describes a method for forming FinFETs with variable channel widths. The variation in channel width can influence the electrical characteristics of the transistor.
- Potential Anticipation (General): US9786510 explicitly mentions forming "fin-shaped structures of different heights and critical dimensions (CD)" and that the "width w1 of the top part of each of the first fin-shaped structures... is larger than a width w3 of a top part of each of the second fin-shaped structures". This directly relates to the concept of variable channel width. Therefore, claims like Claim 2, which specifies the width difference, could be impacted.
US20140335673A1
- Full Citation: US20140335673A1, "Methods of manufacturing finfet semiconductor devices using sacrificial gate patterns and selective oxidization of a fin"
- Publication Date: November 13, 2014
- Brief Description: This patent application details methods for manufacturing FinFET devices that involve sacrificial gate patterns and selective oxidation of fins. Selective oxidation can be used to modify fin dimensions or create insulating layers.
- Potential Anticipation (General): US9786510's first embodiment involves a "treatment process Q2" which is "preferably an oxidation process" to form a "modified part 120" on the fin, which is then removed. This has strong similarities to the "selective oxidization of a fin" described in this prior art. Therefore, method claims of US9786510 related to the modification and removal of fin surfaces through oxidation could be anticipated.
US20150145048A1
- Full Citation: US20150145048A1, "Structure and method for forming cmos with nfet and pfet having different channel materials"
- Publication Date: May 28, 2015
- Brief Description: This patent application describes methods for forming CMOS devices where n-type and p-type FinFETs have different channel materials. This addresses optimizing performance for different transistor types.
- Potential Anticipation (General): While the primary focus is on different channel materials, the underlying FinFET structures and their formation processes would be relevant. If the methods described for forming the fins themselves overlap with US9786510, certain claims could be implicated. The filing date of 2013-11-22 is after the priority date of US9786510 (2014-09-09), making this a later-filed application if it relies on its own priority date. However, further analysis would be needed to determine if it could still be prior art under different 35 U.S.C. § 102 provisions (e.g., if it claims priority to an earlier application that predates US9786510). Given the 2015 publication, it is likely cited for its disclosure rather than necessarily anticipating the claims of US9786510 based solely on its publication date.
US20150311085A1
- Full Citation: US20150311085A1, "Field effect transistor (finfet) device with a planar block area to enable varialble fin pitch and width"
- Publication Date: October 29, 2015
- Brief Description: This patent application describes a FinFET device with a planar block area that allows for variable fin pitch and width. This enables flexibility in FinFET layout and performance optimization.
- Potential Anticipation (General): US9786510 discusses variations in fin width and the distances between fins (p1, p2, p3, p5, p6). Claim 1 of US9786510 specifically addresses the difference in distances between adjacent top corners of fins. Therefore, prior art disclosing variable fin pitch and width, like this reference, would be directly relevant to such claims. The filing date of 2014-04-23 is also before the priority date of US9786510 (2014-09-09).