Obviousness

Obviousness under 35 U.S.C. § 103 dictates that a patent claim cannot be obtained if the differences between the claimed invention and the prior art would have been obvious to a person having ordinary skill in the art (PHOSITA) before the effective filing date of the invention. The analysis requires identifying the scope and content of the prior art, distinguishing the claimed invention from the prior art, and determining the level of ordinary skill in the art. A key component of an obviousness rejection is providing a clear articulation of the reasons why the claimed invention would have been obvious, including a motivation to combine prior art references. This motivation can stem from design needs, market pressure, common sense, or a reasonable expectation of success.

US patent 9786510 claims a fin-shaped structure and a method for manufacturing it, particularly focusing on forming fin-shaped structures with ladder-shaped cross-sectional profiles in different areas to achieve varying electrical demands for transistors. The patent emphasizes the ability to form fin-shaped structures of different heights and critical dimensions.

A PHOSITA in the field of FinFET technology at the time of the invention (priority date 2014-09-09) would have been aware of the challenges in scaling semiconductor devices and the advantages of multi-gate MOSFETs like FinFETs for better channel control, reduced short channel effects, and increased current. They would also understand that transistors in different areas (e.g., logic vs. input/output) have different purposes and electrical demands, necessitating tailored structures.

Here are potential combinations of prior art references that could render the claims of US9786510 obvious:

Combination 1: US20080157225A1 (Datta) + US8373238B2 (Taiwan Semiconductor Manufacturing Company, Ltd.) + General knowledge in the art

• US20080157225A1 (Datta): This reference discloses SRAM and logic transistors with variable height multi-gate transistor architecture. This directly addresses the concept of having different fin heights for different types of transistors, which is a core aspect of US9786510, particularly for meeting varying electrical demands (e.g., HVT and LVT areas).
• US8373238B2 (Taiwan Semiconductor Manufacturing Company, Ltd.): This patent explicitly teaches FinFETs with multiple fin heights. It details methods for achieving these different heights.
• Motivation to Combine: A PHOSITA would be motivated to combine the teachings of Datta and US8373238B2 to implement the variable fin heights proposed by Datta using the specific FinFET manufacturing techniques described in US8373238B2. The motivation would be to optimize transistor performance for different circuit areas (e.g., logic vs. I/O) by tailoring fin heights, a known design consideration in FinFET development. The ability to create FinFETs with different heights allows for better control of electrical characteristics such as threshold voltage, which is crucial for integrating different types of devices on a single substrate.

Combination 2: US20140191323A1 (International Business Machines Corporation) + US20140335673A1 ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)) + General knowledge in the art

• US20140191323A1 (International Business Machines Corporation): This reference describes a method of forming FinFETs of variable channel width. Variation in channel width directly relates to variation in critical dimensions (CDs) of the fins.
• US20140335673A1 (Samsung Electronics Co., Ltd.): This patent describes methods of manufacturing FinFET semiconductor devices using sacrificial gate patterns and selective oxidation of a fin. This aligns with the methods described in US9786510 for modifying fin structures. The patent details how to selectively oxidize a fin, which can lead to changes in its dimensions.
• Motivation to Combine: A PHOSITA would be motivated to combine the concept of variable channel width from US20140191323A1 with the selective modification techniques of US20140335673A1. The goal would be to create FinFETs with varied critical dimensions in different regions of a semiconductor device to meet diverse electrical performance requirements. For example, by selectively oxidizing a fin, its effective width and/or height can be altered, leading to different critical dimensions. This is a predictable outcome when seeking to customize FinFET characteristics for specific applications or areas on a chip. The ability to modify fin dimensions selectively allows for the tailoring of transistor properties such as drive current and leakage.

Combination 3: US20150311085A1 (Globalfoundries Inc.) + US20120313169A1 (Globalfoundries Inc.) + General knowledge in the art

• US20150311085A1 (Globalfoundries Inc.): This reference discloses a FinFET device with a planar block area to enable variable fin pitch and width. This directly addresses forming fins with different dimensions (including width, which impacts CD) in different areas.
• US20120313169A1 (Globalfoundries Inc.): This patent teaches FinFET devices and methods, and integrated circuits using such. It represents general knowledge regarding FinFET fabrication.
• Motivation to Combine: A PHOSITA would be motivated to use the methods described in US20120313169A1, which pertain to FinFET fabrication, to implement the variable fin pitch and width structures described in US20150311085A1. The motivation would be to create FinFETs with customized geometries (e.g., width) in different areas on a chip, which is a known approach to achieving desired electrical characteristics for various components (e.g., high-performance logic vs. low-power memory). The combination offers a direct path to the "fin-shaped structures of different heights and critical dimensions" mentioned in US9786510.

It's important to note that the above combinations are based on the information provided in the "Prior Art" section and the claims of US9786510. A complete obviousness analysis would require a deeper dive into the specific details of each cited prior art reference and a more thorough comparison with each claim element of US9786510, as well as a robust argument regarding the motivation to combine and the reasonable expectation of success for a PHOSITA.