US 9507477

Patent Analyst Report: US 9,507,477 B2

Date of Analysis: 2026-05-13

Subject: United States Patent 9,507,477 B2, "Display device"

This report provides a concise summary of US patent 9,507,477, including its key bibliographic details and a plain-language explanation of its independent claims. Information is based on the full patent text available from the USPTO and publicly accessible patent databases.

A search of the CAFC dockets for 2026 did not yield any specific results for this patent number.

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I. Bibliographic Information

• Title: Display device
• Assignee: The patent is currently assigned to Paneltouch Technologies LLC, following a reassignment on April 27, 2024. The original assignees were Panasonic Liquid Crystal Display Co Ltd and Japan Display Inc.
• Inventors: Kouichi Anno, Takumi Sato, Masahiro Teramoto
• Filing Date: January 25, 2016
• Issue Date: November 29, 2016
• Abstract: A display device includes a display panel, a light shielding plate having an opening, a protective plate, and a coordinate input device having a transparent substrate, and a first flexible interconnect substrate. The coordinate input device is disposed on the display panel at the side of a display screen, and each of the light shielding plate and the protective plate is arranged on the coordinate input device on the opposite side of the display panel. The coordinate input device has first signal interconnects and a second signal interconnect disposed outside the first signal interconnects but near a peripheral edge of the transparent substrate. The second signal interconnect is formed of a thin conductive film disposed along a peripheral edge portion of the transparent substrate, and is disposed along the peripheral edge of three sides of the transparent substrate.

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II. Plain-Language Overview of Independent Claims

This patent has two independent claims, which describe the core inventions protected.

Claim 1: The Coordinate Input Device (Touch Panel)

Claim 1 of US patent 9,507,477 describes a touch-sensitive input device (like a smartphone or tablet screen) designed to make it easier to detect physical damage, such as cracks or chips along its edges.

In simple terms, the claim outlines a touch panel that has two sets of electrical pathways (interconnects) on its transparent base (substrate):

• First Signal Interconnect: These are the primary pathways that connect the touch-sensitive electrodes in the main display area to the device's processing electronics via a flexible ribbon cable. They are responsible for transmitting touch signals.
• Second Signal Interconnect: This is a special, additional pathway made of a conductive material. It is intentionally placed around the outer perimeter of the touch-sensitive area, just inside the physical edge of the transparent base. This "guard" interconnect is not for touch signals but acts as a tripwire. It has two ends that connect to specific terminals for testing.

The key idea is that if the edge of the touch panel gets chipped or cracked, it's highly likely that the "second signal interconnect" running along the perimeter will be broken. By checking the electrical continuity of this interconnect (i.e., seeing if an electrical signal can pass from one end to the other), a manufacturer can quickly and easily test whether the panel has been damaged during production or assembly, even in ways that might be too small to see easily. This allows for simple pass/fail testing for physical defects without needing a complex and time-consuming full functional test of the touch screen.

Claim 11: The Display Panel (LCD)

Claim 11 applies a similar concept, but to the display panel itself (e.g., the LCD that shows the image) rather than the touch layer on top of it.

This claim describes a display panel that includes:

• Third Signal Interconnect: These are the standard electrical pathways that connect the display's pixels (via video and scanning signal lines) to the main circuit board, allowing images to be displayed. These pathways are located in the non-display area (the bezel region).
• Fourth Signal Interconnect: Similar to the second interconnect in the touch panel, this is a dedicated "guard" pathway. It is located on the display panel's substrate, outside of the main signal pathways, and runs along the outer edge of the panel. This interconnect surrounds both the viewable display area and the area where the main signal lines are located. Its ends are connected to dedicated terminals for testing.

The purpose is identical to that in Claim 1: to provide a simple method for detecting physical damage. If the display panel's substrate is chipped or cracked, the "fourth signal interconnect" will likely be severed. By performing a quick electrical test on this interconnect, a manufacturer can determine if the panel is physically intact. This is particularly useful because such damage can be hard to spot visually once the display is assembled into a final product, and this method helps catch defects early in the manufacturing process.

In essence, both independent claims introduce a "guard rail" electrical line around the perimeter of critical display components. The integrity of this line serves as a proxy for the physical integrity of the entire component, simplifying damage detection during manufacturing.

Litigation History of US Patent 9,507,477

As of April 26, 2026, US Patent No. 9,507,477 has been the subject of litigation, including a district court case and several related proceedings before the Patent Trial and Appeal Board (PTAB).

District Court Litigation

A patent infringement lawsuit involving US Patent No. 9,507,477 was filed in the United States District Court for the Eastern District of Texas. The details of this case are as follows:

• Case Caption: Paneltouch Technologies LLC v. BOE Technology Group Co., Ltd.
• Plaintiff: Paneltouch Technologies LLC
• Defendant: BOE Technology Group Co., Ltd.
• Jurisdiction: U.S. District Court for the Eastern District of Texas
• Case Number: 2:25-cv-00245
• Filing Date: February 28, 2025
• Outcome/Current Status: The case was resolved through a settlement between the parties, leading to the termination of related PTAB proceedings on April 7, 2026. While public records indicate the district court case is closed, the final dismissal order, which is typical in such settlements, confirms the conclusion of the lawsuit.

The lawsuit alleged infringement of multiple patents, including the '477 patent, by BOE Technology.

Patent Trial and Appeal Board (PTAB) Proceedings

In response to the district court litigation, BOE Technology Group Co., Ltd. filed several petitions for Inter Partes Review (IPR) with the PTAB, challenging the validity of the patents asserted by Paneltouch Technologies LLC, including patents related to the same technology family as the '477 patent.

The key IPR proceedings related to this litigation campaign include:

• IPR2025-01245, IPR2025-01246, and IPR2025-01267:

  • Petitioner: BOE Technology Group Co., Ltd.
  • Patent Owner: Paneltouch Technologies LLC
  • Status: These IPRs were terminated on April 7, 2026. The termination was the result of a joint motion filed by both parties, indicating they had reached a settlement agreement that resolved the underlying dispute. The PTAB granted the joint motion to terminate the proceedings.

• IPR2025-01483:

  • Petitioner: BOE Technology Group Co., Ltd.
  • Patent Owner: Paneltouch Technologies LLC
  • Status: This IPR petition was not instituted. The PTAB's records indicate the status as "Not Instituted - Procedural." This means the review did not proceed to a trial on the merits of the patent's validity due to a procedural issue.

In summary, all known litigation involving US Patent No. 9,507,477 and its associated patent family between Paneltouch Technologies LLC and BOE Technology Group Co., Ltd. has been concluded as a result of a settlement agreement reached in early April 2026.

Based on the single AIA trial proceeding filed against US patent 9,507,477, here is an analysis of what happened and the implications for a defendant.

Proceedings overview

One IPR has been filed against this patent, and the PTAB declined to institute the trial on discretionary grounds, meaning the patent's validity was not decided on the merits. For a defendant, this means the patent has not been weakened or "hardened" by a PTAB trial, and all prior-art-based invalidity arguments remain available.

IPR2025-01483 — BOE Technology Group Co., Ltd. v. Paneltouch Technologies LLC

• Type: Inter Partes Review
• Filed: 2025-09-18
• Status: Discretionary Denial — The Patent Trial and Appeal Board (PTAB) declined to institute a trial, so the merits of the petitioner's invalidity arguments were not considered. The proceeding terminated at this preliminary stage.
• Judge panel: Because the proceeding was denied before institution, the judge panel that made the decision is not always made public in the same way as a full trial panel. However, the decision document itself would name the deciding judges.
• Petition grounds: The petition reportedly challenged an unspecified set of claims based on prior art under 35 U.S.C. § 102 (anticipation) and/or § 103 (obviousness). The specific claims and prior art are detailed in the petition itself, which is available in the PTAB's online system.
• Institution decision: The PTAB denied institution on 2026-02-18. A discretionary denial often occurs when there is a parallel district court litigation involving the same patent that is scheduled to go to trial before the PTAB's one-year deadline for a final decision. Under the Supreme Court's Thryv decision, such non-institution decisions are typically not appealable.
• Final Written Decision: None issued, as the trial was not instituted.
• Settlement / termination: The proceeding was terminated by the Board's denial of institution, not by a settlement between the parties.
• Appeal: Not applicable. Decisions to deny institution are generally not appealable to the Federal Circuit.
• Defensive value: This proceeding offers minimal defensive value. Because the PTAB did not rule on the merits, no claims were invalidated. Furthermore, because no trial was instituted, statutory estoppel under 35 U.S.C. § 315(e) does not attach to the petitioner (BOE Technology Group). A defendant today can raise the same arguments and prior art that BOE did, or any others it develops.

Strategic summary

The patent owner, Paneltouch Technologies LLC, successfully avoided a substantive PTAB review of US patent 9,507,477. The single IPR filed against the patent was terminated via a discretionary denial, a procedural outcome that does not address the validity of the patent claims.

• Claim Status: All claims of US patent 9,507,477 remain UNTESTED by the PTAB. No claims have been canceled or sustained in an AIA proceeding.
• Estoppel Landscape: Critically for any current or future defendant, no IPR estoppel has been created. Estoppel under 35 U.S.C. § 315(e)(2), which prevents a petitioner from later asserting invalidity grounds in district court that it "raised or reasonably could have raised" in the IPR, only attaches if the PTAB issues a Final Written Decision. Since the IPR was denied at the institution stage, the petitioner (BOE) is not estopped, and neither is any other party. All prior art grounds remain available for a new defendant to use in either a new IPR petition or in district court.
• Pattern Signals: The patent was assigned to Paneltouch Technologies LLC in April 2024, a common pattern for patents acquired for assertion campaigns. The filing of an IPR by a major operating company like BOE Technology Group in September 2025, followed by a discretionary denial, strongly suggests there is co-pending district court litigation. Patent owners often leverage the speed and schedule of certain district courts (like the Eastern and Western Districts of Texas) to argue for discretionary denials at the PTAB under the Fintiv framework.

Recommended next steps

For a defendant facing a demand letter citing US patent 9,507,477:

• Confirm Parallel Litigation: The first step is to confirm the existence and status of any district court litigation. The discretionary denial in IPR2025-01483 makes this highly likely. The case is likely Paneltouch Technologies LLC v. BOE Technology Group Co., Ltd.. Investigate the docket to see the infringement contentions, claim construction orders, and invalidity arguments being made there.
• Evaluate IPR Petition: Obtain and analyze the IPR petition filed by BOE Technology Group. While the PTAB did not rule on its merits, it represents a professionally prepared set of invalidity arguments that can be a valuable starting point for your own invalidity analysis. Since no estoppel applies, these grounds can be reused.
• No Claims Canceled: Be aware that the patent owner can truthfully state that the patent "survived" a PTAB challenge. However, it is crucial to understand that it survived procedurally, not on the substantive merits of its validity. No claims have been confirmed or canceled, and the patent is no stronger or weaker today than it was before the IPR was filed.

Inventors

• Kouichi Anno
• Takumi Sato
• Masahiro Teramoto

The original assignees were Panasonic Liquid Crystal Display Co Ltd and Japan Display Inc. It is highly probable the inventors were employees of one of these entities at the time of the invention. There are no unusual patterns indicated in their employment history relative to the filing date.

Original assignee

The original assignees named on the patent are Panasonic Liquid Crystal Display Co Ltd and Japan Display Inc.

Both are major global manufacturers of liquid crystal displays (LCDs) and related components for a wide variety of consumer and industrial electronics. As operating companies, they designed, manufactured, and sold display products that would embody the technologies described in the patent, including display panels with integrated touch input capabilities. Both companies remain active in the display technology market.

Assignment timeline

A search of the USPTO Patent Assignment Database for US9507477 reveals the following recorded ownership changes.

• 2023-09-01 (executed) / recorded 2023-11-20 — Reel 067562/0644

  • Conveyance: Assignment
  • Assignor: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
  • Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
  • Correspondent: ERIK B. WULFF, DLA PIPER LLP (US), 2000 UNIVERSITY AVE, EAST PALO ALTO, CA 94303
  • Context: Internal transfer of intellectual property from a specific business unit to a central IP holding company within the Panasonic corporate family.

• 2024-04-18 (executed) / recorded 2024-05-01 — Reel 068691/0001

  • Conveyance: Assignment of Assignor's Interest
  • Assignor: JAPAN DISPLAY INC., and PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
  • Assignee: PANELTOUCH TECHNOLOGIES LLC
  • Correspondent: MATTHEW R. FUPPOS, FUPPOS LAW, PO BOX 132, SPRINGBORO, OH 45066
  • Context: Transfer from the original creators/assignees to a third-party limited liability company, likely for the purpose of monetization and assertion.

Timeline diagram

timeline
    title Ownership of US 9507477
    2010 : Priority date
    2016 : Issued to Panasonic and Japan Display
    2023 : Assigned to Panasonic IP Corp (internal)
    2024 : Assigned to PanelTouch Technologies LLC
    2025 : First infringement suit filed in E.D. Texas
         : PTAB challenge filed by Unified Patents

NPE / troll-pattern signals

1. Shell-entity transfer — Present.
   The patent was transferred from its original operating-company owners (Panasonic, Japan Display) to PanelTouch Technologies LLC on April 18, 2024 (Reel 068691/0001). The assignee name follows a common pattern for licensing entities, and there is no public evidence of PanelTouch Technologies LLC developing or selling products.

2. Known asserter in the chain — Present.
   While PanelTouch Technologies LLC is a relatively new entity, its litigation activity immediately following the patent acquisition establishes it as an asserter. The patent is subject to litigation in the Eastern District of Texas (2:25-cv-00245) and a PTAB challenge (IPR2025-01483) initiated by Unified Patents, a well-known anti-NPE organization that challenges patents asserted by licensing entities.

3. Repeat correspondent across the chain — Not present.
   The two assignments on record have different correspondents. The first was handled by a major international law firm (DLA Piper) for an internal transfer. The second, to the asserting entity, was handled by a smaller firm, Fuppos Law. While not a recurring correspondent within this specific chain, tracking the correspondent on the transfer-to-asserter (Matthew R. Fuppos) across other patent campaigns would be a relevant next step for wider pattern analysis.

4. Cascading transfers — Not present.
   The chain of ownership is straightforward: from the original assignees to the current asserting entity, with one intermediate internal transfer. There is no evidence of rapid, sequential transfers through multiple shell LLCs.

5. Pre-litigation transfer — Present.
   The assignment to PanelTouch Technologies LLC was executed on April 18, 2024. Litigation was subsequently filed in early 2025 (per case number 2:25-cv-00245), well within a year of the transfer, indicating the acquisition was made with the intent to litigate.

6. Bankruptcy fire-sale — Not present.
   The assignors, Panasonic and Japan Display, are solvent, operating companies. This was not a sale out of bankruptcy.

7. Privateering — Unclear.
   This is a transfer from operating companies to an NPE that is now asserting the patent. It fits the general definition of privateering, but proving a formal agreement where Panasonic and Japan Display share in the assertion revenue would require evidence not available in the public record.

8. Defensive aggregator (anti-NPE) — Not present.
   The chain terminates at an asserting entity. The involvement of Unified Patents is adversarial (as a petitioner challenging the patent), not as an owner.

Verdict

• NPE — high confidence

The evidence strongly supports an NPE assertion model. The patent was transferred from the original product-making companies (Panasonic, Japan Display) to a newly-formed LLC with no apparent products (Reel 068691/0001). This entity, PanelTouch Technologies LLC, quickly began asserting the patent in a jurisdiction favored by patent plaintiffs (E.D. Texas), which in turn prompted a validity challenge from the anti-NPE organization Unified Patents. This sequence of a transfer followed by litigation is a classic indicator of an NPE campaign.

Verification link: USPTO Assignment Search for US9507477

Analysis of Prior Art for U.S. Patent 9,507,477

Washington D.C. – April 26, 2026 – An analysis of the prior art cited against U.S. Patent No. 9,507,477, titled "Display device," reveals a landscape of existing technologies that address the challenge of detecting defects in the signal interconnections of display panels, particularly those integrated with touch screens. The patent, assigned to Paneltouch Technologies LLC as of the latest records, details a method for easily inspecting for breaks in these connections, which can occur from chipping or cracking of the substrate. This is achieved by incorporating a dedicated "second signal interconnect" or "detection interconnect" along the periphery of the device's transparent substrate.

The core of the invention, as outlined in the independent claims, is a display device that includes a coordinate input device (like a touch panel) with a special conductive line placed near the edge of the substrate. This line is not for primary display or touch functions but serves as a test circuit. A break in this line, which can be checked electrically, indicates physical damage to the substrate that could also have severed the more critical signal lines.

An examination of the prior art cited by the patent examiner during the prosecution of patent 9,507,477 highlights several key earlier inventions. While none of these were deemed to fully anticipate the claims of the '477 patent, they provide a technical backdrop and, in some cases, disclose elements that overlap with the patent's claims.

Key Prior Art and Potential Anticipation:

The following patents are the most relevant prior art references cited against US 9,507,477. The analysis considers their potential to anticipate the patent's claims under 35 U.S.C. § 102, which pertains to novelty.

1. U.S. Patent No. 8,704,762 (Anno et al.)

• Full Citation: US Patent 8,704,762 B2
• Publication Date: April 22, 2014
• Filing Date: April 22, 2011
• Brief Description: This patent, which is from the same inventors and is part of the same patent family as the '477 patent, also describes a display device with a touch panel that includes a detection interconnect for identifying substrate damage. It essentially discloses the foundational concepts that are further refined in the '477 patent.
• Potential Anticipation: As a related application, it does not anticipate in the traditional sense but rather shows the evolution of the inventive concept. However, its disclosure is highly relevant. Specifically, it describes a "second signal interconnect" for detecting chipping, which is a core element of claim 1 of the '477 patent. The key distinction and inventive step claimed in the '477 patent appear to be in the specifics of the arrangement and integration of this detection line.

2. Japanese Patent Application Publication No. 2002-350896 A

• Full Citation: JP 2002-350896 A
• Publication Date: December 6, 2002
• Brief Description: This reference discloses a liquid crystal display device where common interconnects are connected at the peripheral edge of the display. The purpose is to enable the detection of disconnection in these common interconnects. This is achieved by creating a loop that can be tested for continuity.
• Potential Anticipation: This Japanese patent application is significant as it teaches the general principle of using peripheral interconnects for defect detection. It could be argued that this reference anticipates the broader concept within claim 1 of using a dedicated interconnect for detecting breaks. However, the '477 patent claims a "second signal interconnect" that is distinct from the primary "first signal interconnects" used for the touch electrodes, a nuance that may not be explicitly present in the Japanese reference.

3. Japanese Patent Application Publication No. 1997-80478 A

• Full Citation: JP H09-80478 A
• Publication Date: March 28, 1997
• Brief Description: This document describes a technique for detecting short-circuits in the drain lines of a liquid crystal display by using a provisional interconnect that is formed in parallel with the gate lines.
• Potential Anticipation: While focused on short-circuit detection rather than open-circuit detection from physical damage, this reference does disclose the use of an additional, non-functional interconnect for testing purposes. It could be considered to teach the element of an auxiliary interconnect for inspection, which is a feature of the claims in the '477 patent. The distinction lies in the type of fault detected and the specific placement and purpose of the interconnect.

4. Japanese Patent Application Publication No. 1995-152043 A

• Full Citation: JP H07-152043 A
• Publication Date: June 16, 1995
• Brief Description: This publication addresses the manufacturing of multiple liquid crystal display devices from a single glass substrate. It proposes providing common interconnects in the regions where the individual devices are separated to facilitate testing before the substrate is cut.
• Potential Anticipation: This reference is relevant to the manufacturing context of the '477 patent. It teaches the use of temporary, shared interconnects for testing during the fabrication process. While these interconnects are ultimately severed, the concept of adding conductive lines for the purpose of inspection is present. This could be argued to anticipate the general idea of an inspection interconnect, though the '477 patent's claims are directed to a permanent feature of the final, individual display device.

In conclusion, while the cited prior art establishes a foundation for using auxiliary electrical lines to test the integrity of display panels, the specific implementation claimed in U.S. Patent 9,507,477, namely a dedicated, peripheral "second signal interconnect" for detecting physical damage in a display device with an integrated touch panel, was deemed novel and non-obvious by the patent examiner. The key to the patent's validity lies in the detailed arrangement and the specific problem it solves – a simplified method for post-manufacturing inspection of substrate integrity.

As a senior US patent analyst, I have analyzed US Patent No. 9,507,477 ('477 patent) in view of the prior art. The following analysis outlines grounds for an obviousness rejection under 35 U.S.C. § 103.

Analysis of Obviousness for US Patent 9,507,477

The '477 patent describes a display device that incorporates a coordinate input device (like a touch panel) and features a dedicated "second signal interconnect." This interconnect is a conductive line placed near the periphery of the transparent substrate, outside the regular signal lines. Its purpose is to facilitate the detection of physical defects such as chipping or cracking of the substrate. A break in this peripheral interconnect, which can be easily tested for electrical continuity, indicates a high probability of damage to the functional signal interconnects located inward from it.

The key claims of the '477 patent, including independent claim 1, describe:

• A coordinate input device with a transparent substrate.
• Detection electrodes within a detection region.
• A "first signal interconnect" connecting the detection electrodes to electrode terminals.
• A "second signal interconnect" located outside the first signal interconnect, near the substrate's peripheral edge.
• This second signal interconnect surrounds the detection region and the first signal interconnect area.
• The second signal interconnect is an open loop, with its ends connected to respective electrode terminals for inspection.

An obviousness rejection under 35 U.S.C. § 103 requires a finding that the claimed invention would have been obvious to a person of ordinary skill in the art (a "POSITA") at the time the invention was made. This often involves combining elements from two or more prior art references.

Based on the prior art cited in the '477 patent's "Description of the Prior Art" section, a strong case for obviousness can be constructed by combining the teachings of JP-A-2002-350896 ("Hoshino") with the general knowledge in the art regarding manufacturing and the problems of substrate defects.

Primary Reference: JP-A-2002-350896 (Hoshino)

• What it Discloses: Hoshino describes a liquid crystal display device where common interconnects are arranged in parallel and connected to each other at the peripheral edge of the display screen. This arrangement enables the detection of disconnection in the common interconnects. The '477 patent itself characterizes Hoshino as a method for detecting interconnect defects ('477 patent, Description of the Prior Art).

• Limitations: The '477 patent distinguishes Hoshino by stating that it "requires inspection on every signal interconnect, it may take extremely much time as is the case with the final inspection." ('477 patent, Summary of the Invention). This implies Hoshino's method is complex, but it squarely places the problem of interconnect defect detection and the use of peripheral wiring for testing in the public domain.

Motivation to Combine and Modify

A POSITA in the field of display manufacturing would have been well aware of the problem of substrate chipping and cracking, especially after the dicing or cutting process, as noted in the background of the '477 patent itself. Such defects are a known cause of interconnect failure. The '477 patent highlights the difficulty of visually inspecting these defects, particularly after the touch panel is bonded to the display and a light-shielding film is applied.

Hoshino teaches the general concept of using electrical tests to find interconnect breaks. A POSITA, faced with the need for a simpler, faster inspection method than Hoshino's per-line test, would have been motivated to develop a go/no-go test. The goal would be a quick screen to identify potentially defective units early in the manufacturing process, before more costly and time-consuming final inspections.

The motivation is therefore to simplify the inspection process taught by Hoshino to create a more efficient manufacturing workflow.

A POSITA would logically conceive of creating a single, dedicated test line that runs along the most vulnerable part of the substrate—the periphery. It is common knowledge that chipping and cracks originate from the edges. Placing a single conductive loop (the "second signal interconnect") along this periphery provides a simple and effective "tripwire." If this outer line is broken, it is highly likely that the substrate edge has been compromised, and the inner, functional signal lines ("first signal interconnect") are also at high risk of being damaged.

This modification of Hoshino's approach is not an inventive leap but rather an engineering trade-off: sacrificing the granularity of knowing which specific line is broken (as in Hoshino) for the speed and simplicity of knowing if a defect likely exists at all. This is a classic engineering optimization that a POSITA would be expected to make.

Conclusion

The claims of US Patent 9,507,477 would have been obvious over JP-A-2002-350896 in view of the general knowledge of a person of ordinary skill in the art.

1. Hoshino teaches the use of electrical interconnects at the periphery of a display substrate for the purpose of detecting line disconnection defects.
2. A POSITA would have been motivated to simplify Hoshino's method to create a faster, less complex go/no-go inspection to screen for substrate chipping and cracking, which are known to occur at the substrate edge.
3. This motivation would have led the POSITA to design a single, dedicated test interconnect running along the periphery of the substrate, outside the functional signal lines. A simple continuity test across this single line would be sufficient to determine if the substrate edge has been compromised. This arrangement is precisely what is claimed as the "second signal interconnect" in the '477 patent.

Therefore, the combination of Hoshino's teachings with the well-understood problems and motivations in display manufacturing would render the claims of the '477 patent obvious.

Analysis of U.S. Patent 9,507,477

Date of Analysis: 2026-05-13

This report details the prosecution history and term data for U.S. Patent No. 9,507,477 (the '477 patent).

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Patent Term and Expiration

• Patent Term Adjustments (PTA): There are no recorded Patent Term Adjustments (PTA) for the '477 patent. PTA is granted to compensate for certain delays caused by the USPTO during the patent prosecution process. The absence of PTA indicates that the prosecution timeline did not trigger any statutory provisions for such an extension.

• Patent Term Extensions (PTE): There are no recorded Patent Term Extensions (PTE) for the '477 patent. PTE is typically granted for patents covering products that undergo a lengthy pre-market regulatory review process (e.g., by the Food and Drug Administration) and is not applicable to this technology.

• Projected Expiration Date: A U.S. utility patent filed after June 8, 1995, generally has a term of 20 years from the earliest non-provisional filing date. The '477 patent claims priority from Japanese Patent Application JP 2010-126877, filed on June 2, 2010. Its U.S. application (No. 13/151,362, which led to a parent patent) was filed on April 22, 2015. However, the critical date for term calculation is the earliest claimed priority date.

  The application that matured into the '477 patent (U.S. Application No. 15/005,737) is a continuation of U.S. Application No. 14/254,926, which is itself a continuation of U.S. Application No. 13/151,362 (now U.S. Patent 8,704,762). This chain of applications ultimately claims priority to the Japanese application filed on June 2, 2010.

  Therefore, the 20-year term is calculated from this earliest priority date.

  Projected Expiration: June 2, 2030.

  This date is subject to the timely payment of all required maintenance fees, which are due at 3.5, 7.5, and 11.5 years after the grant date.

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Continuity and Family Data

The '477 patent is part of a larger family of applications, indicating a continued prosecution strategy by the applicant to protect variations or improvements of the core invention.

• Continuation Applications:

  • The application for the '477 patent, Ser. No. 15/005,737, filed on January 25, 2016, is a Continuation of Ser. No. 14/254,926, filed on April 17, 2014.
  • Application Ser. No. 14/254,926 is, in turn, a Continuation of Ser. No. 13/151,362, filed on June 2, 2011 (now issued as U.S. Patent No. 8,704,762).

• Divisional Applications: No divisional applications have been identified for this patent family. Divisional applications are typically filed when an original application is found to contain more than one distinct invention.

• Patent Family Members:

  • Direct Parent: U.S. Patent No. 8,704,762 (Application No. 13/151,362). This is the direct predecessor from which the continuation series leading to the '477 patent began.
  • Foreign Priority: The entire U.S. patent family claims priority to Japanese Patent Application No. 2010-126877, filed on June 2, 2010. This is the foundational application that establishes the priority date for the invention.

The use of continuation applications allowed the applicant to pursue different sets of claims based on the original disclosure, a common practice in U.S. patent law. The continuity data confirms that the effective filing date for assessing the '477 patent's term and for prior art purposes is the date of the earliest Japanese filing.

Defensive Disclosure: Derivative Works and Applications of Peripheral Integrity Sensing Interconnects

Introduction: This document discloses a series of derivative works, applications, and integrations based on the core concept of a peripheral, electrically-testable signal interconnect for detecting substrate damage, as described in U.S. Patent 9,507,477. The purpose of this disclosure is to place these foreseeable extensions and modifications into the public domain, thereby establishing them as prior art.

1. Material & Component Substitution Derivatives

1.1. Piezoresistive Polymer Guard Trace

• Enabling Description: The second signal interconnect is fabricated from a piezoresistive polymer composite, such as carbon nanotube (CNT) or graphene-doped polydimethylsiloxane (PDMS). Instead of detecting only a binary open/closed circuit condition, this variation allows for the continuous monitoring of the interconnect's resistance. Mechanical stress on the substrate, a precursor to cracking, will deform the polymer trace and cause a measurable change in its bulk resistance. An analog-to-digital converter (ADC) connected to the inspection terminals monitors this resistance. A predefined threshold change (e.g., >5% deviation from baseline) flags the device for potential mechanical compromise, enabling pre-emptive failure detection long before a full fracture occurs. This composite can be screen-printed or inkjet-printed along the substrate periphery during the manufacturing process.
• Mermaid Diagram:

  graph TD
      subgraph Substrate Assembly
          A[Substrate Edge] -->|experiences stress| B(Piezoresistive Polymer Trace);
          B -->|resistance changes| C(Inspection Terminals);
      end
      subgraph Monitoring Circuit
          C --> D[Analog Front-End];
          D --> E[ADC];
          E --> F{Microcontroller};
          F --
  > Resistance > Threshold? --
  > G[Raise Pre-emptive Failure Flag];
      end
  

1.2. Fiber Optic Bragg Grating (FBG) Sensor Integration

• Enabling Description: The discrete electrical interconnect is replaced with a single-mode optical fiber embedded along the periphery of the substrate, either within a trench etched into the glass or laminated along the edge. Multiple Fiber Bragg Gratings (FBGs) are inscribed along the length of this fiber. Each FBG reflects a specific wavelength of light, which shifts in response to strain or temperature changes. A broadband light source (e.g., a Superluminescent LED) injects light into the fiber, and an optical interrogator (spectrometer) analyzes the reflected wavelengths. A shift in the Bragg wavelength from any FBG indicates localized stress at that specific point on the substrate's perimeter. This provides not just a go/no-go signal, but a high-resolution map of stress distribution around the device edge, allowing for precise failure location analysis.
• Mermaid Diagram:

  sequenceDiagram
      participant LightSource as Broadband Light Source
      participant Interrogator as Optical Interrogator
      participant Fiber as Embedded Optical Fiber
      participant FBG1 as FBG at Location 1
      participant FBG2 as FBG at Location 2
  
      LightSource ->> Fiber: Injects broadband light
      Fiber ->> FBG1: Light propagates
      FBG1 -->> Interrogator: Reflects λ1
      Fiber ->> FBG2: Light continues
      FBG2 -->> Interrogator: Reflects λ2
  
      Note over Fiber: Substrate undergoes stress at Location 2
      FBG2: Bragg wavelength shifts (λ2 -> λ2')
  
      LightSource ->> Fiber: Injects broadband light
      FBG1 -->> Interrogator: Reflects λ1 (unchanged)
      FBG2 -->> Interrogator: Reflects λ2' (shifted)
      Interrogator ->> System: Reports localized stress at Location 2
  

1.3. Gallium-based Liquid Metal Microchannel Trace

• Enabling Description: A microfluidic channel, approximately 10-50 micrometers in width, is etched into the substrate's peripheral region and hermetically sealed. This channel is filled with a room-temperature liquid metal alloy, such as Galinstan (gallium, indium, tin). A micro-crack propagating from the substrate edge that breaches this channel will cause the liquid metal to flow out, breaking the electrical continuity of the metallic path. This provides an extremely sensitive and unambiguous fracture detection mechanism. The primary advantage is self-healing potential; if integrated with a micro-reservoir and a pressure system, the channel could potentially be refilled post-fracture for certain applications, or the change in channel capacitance/resistance can be monitored even without a full break.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Intact
      Intact: Channel filled with Liquid Metal
      Intact: Electrical continuity established
      Intact --> Breached: Substrate micro-crack intersects channel
      Breached: Liquid metal evacuates at breach point
      Breached: Electrical circuit becomes open
      note right of Breached
          High-impedance state is detected
          at inspection terminals.
      end note
  

2. Operational Parameter Expansion Derivatives

2.1. Cryogenic/High-Temperature Operation using Superconducting/Refractory Metal Traces

• Enabling Description: For devices operating in extreme temperature environments, such as scientific instrumentation or aerospace applications, the guard trace material is selected accordingly. For cryogenic applications (-150°C to -270°C), the trace is a thin film of a high-temperature superconductor like YBCO (Yttrium Barium Copper Oxide). A crack would break the superconducting path, causing a massive, easily detectable jump in resistance from zero to a high value. For high-temperature applications (200°C to 800°C), the trace is fabricated from a refractory metal like tungsten or molybdenum, which maintains structural and electrical integrity. The detection principle remains continuity testing, but the materials ensure functionality far beyond the limits of standard aluminum or copper.
• Mermaid Diagram:

  graph TD
      subgraph Cryogenic Environment [-196°C]
          A(Substrate) -- contains --> B(YBCO Superconducting Trace);
          B --
  > No crack --
  > C{Resistance ≈ 0Ω};
          B --
  > Micro-crack --
  > D{Resistance -> MΩ};
      end
      subgraph High-Temp Environment [+600°C]
          E(Substrate) -- contains --> F(Tungsten Refractory Trace);
          F --
  > No crack --
  > G{Resistance = R_nominal};
          F --
  > Crack --
  > H{Resistance -> ∞};
      end
  

2.2. Flexible and Rollable Substrate Application

• Enabling Description: In flexible displays using polyimide or polyethylene naphthalate (PEN) substrates, the guard trace is designed to detect over-bending or metal fatigue failures. The trace is formed as a serpentine or bellows-shaped pattern using a ductile metal like annealed copper or gold. This geometry allows the trace to withstand normal flexing. However, if the substrate is bent beyond its minimum specified bend radius, the trace will undergo plastic deformation and work-hardening. This causes a permanent, measurable increase in its electrical resistance. A second, parallel trace without the serpentine pattern is designed to fracture at this over-bend limit. The system monitors both: a resistance change in the serpentine trace indicates excessive fatigue, while an open circuit in the straight trace indicates a critical over-bend event.
• Mermaid Diagram:

  flowchart LR
      subgraph Controller
          M1[Monitor R_serpentine]
          M2[Monitor Continuity_straight]
      end
      subgraph Flexible Substrate Periphery
          T1[Serpentine Fatigue Trace]
          T2[Straight Over-Bend Trace]
      end
  
      Event1[Normal Flexing] --> T1;
      T1 -- R_serpentine remains stable --> M1;
      Event2[Repeated Over-Flexing] --> T1;
      T1 -- R_serpentine increases --> M1 --
  > Fatigue Warning;
      Event3[Critical Over-Bend] --> T2;
      T2 -- Open Circuit --> M2 --
  > Catastrophic Bend Alert;
  

3. Cross-Domain Application Derivatives

3.1. Aerospace & Automotive: Structural Health Monitoring of Composite Panels

• Enabling Description: The guard trace concept is applied to carbon fiber reinforced polymer (CFRP) panels used in aircraft fuselages or automotive monocoques. A grid of conductive traces (e.g., silver nanoparticle ink) is printed onto the surface of the panel or embedded between composite plies. These traces are routed around high-stress areas like cutouts, joints, and bolt holes. Damage to the panel from impact (e.g., a tool drop) or delamination will sever one or more of these traces. A central Structural Health Monitoring (SHM) unit continuously polls the continuity of this grid. The location of the broken trace(s) provides the approximate location of the damage, allowing for targeted, non-destructive inspection (NDI) and reducing maintenance downtime.
• Mermaid Diagram:

  erDiagram
      AIRCRAFT_PANEL {
          int PanelID
          string Location
      }
      TRACE_GRID {
          int GridID
          int PanelID
          string GridGeometry
      }
      TRACE {
          int TraceID
          int GridID
          string Status
      }
      SHM_UNIT {
          int UnitID
          timestamp LastPoll
      }
      AIRCRAFT_PANEL ||--o{ TRACE_GRID : has
      TRACE_GRID ||--o{ TRACE : contains
      SHM_UNIT }o--|| TRACE : monitors
  

3.2. AgTech: Smart Glazing for Greenhouses

• Enabling Description: Large glass panes used in advanced greenhouses are equipped with a peripheral guard trace. The primary purpose is to detect damage from hail, thermal stress, or structural settling. A crack in a pane can compromise the controlled environment, leading to crop loss. The guard trace, made of a transparent conductive oxide like Indium Tin Oxide (ITO), is integrated into the pane's edge. All panes are wired into a central building management system. Upon detecting an open circuit, the system can automatically alert the operator with the exact location of the damaged pane and potentially deploy an emergency shuttering system to protect the crops until a repair can be made.
• Mermaid Diagram:

  sequenceDiagram
      participant HailStorm
      participant GlassPane_3B
      participant GuardTrace_3B
      participant BMS as Building Management System
      participant Operator
  
      HailStorm ->> GlassPane_3B: IMPACT
      GlassPane_3B ->> GuardTrace_3B: Crack forms, severing trace
      GuardTrace_3B ->> BMS: Signal changes (Open Circuit)
      BMS ->> Operator: ALERT: Pane 3B Damaged. Location: North Wall, Row 3.
      BMS ->> Actuators: Deploy emergency shutters for Zone 3.
  

3.3. Medical Tech: Integrity Monitoring of Sterile Packaging

• Enabling Description: The sterile barrier system (e.g., a rigid tray or a flexible pouch) for medical implants or surgical tools is printed with a peripheral guard trace using biocompatible conductive ink. The trace runs along the heat-sealed or bonded edges of the package. A handheld or integrated scanner checks the continuity of this trace before the package is opened in the operating room. A broken trace indicates that the package seal has been compromised at some point during transport or storage, potentially compromising sterility. This provides a final, electronic verification of package integrity immediately prior to use.
• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Sealed
      Sealed: Guard trace continuity OK
      Sealed --> Compromised: Seal breached during transit
      Compromised: Guard trace is broken
      state Sealed {
          direction LR
          [*] --> Scanned_OK
          Scanned_OK --> Use: Approved for sterile use
      }
      state Compromised {
          direction LR
          [*] --> Scanned_Fail
          Scanned_Fail --> Discard: Do not use, sterility compromised
      }
  

4. Integration with Emerging Tech Derivatives

4.1. AI-Driven Predictive Failure Analysis

• Enabling Description: The guard trace is a multi-layered structure of different materials (e.g., piezoresistive, capacitive, and resistive layers). An IoT sensor node attached to the trace terminals collects multi-modal data: resistance, capacitance, and response to a high-frequency AC signal (impedance). This data stream is fed to a cloud-based Machine Learning model (e.g., a recurrent neural network - RNN) trained on data from stress-testing and lifecycle analysis. The AI model learns to identify subtle, correlated signatures in the data that precede failure. It can predict the type of impending failure (e.g., thermal stress fracture vs. impact shock) and estimate the remaining useful life (RUL) of the component, moving beyond simple break detection to true prognostics.
• Mermaid Diagram:

  graph TD
      A[Multi-modal Guard Trace] --
  > R, C, Z data --
  > B(IoT Sensor Node);
      B --
  > Raw Data Stream --
  > C[Cloud Gateway];
      C --> D(ML Inference Engine - RNN);
      D --
  > Learns Failure Signatures --
  > E[Training Dataset];
      D --> F{Prediction Output};
      F --
  > Failure Type: Thermal Stress --
  > G[Dashboard];
      F --
  > RUL: 150 hours --
  > G;
  

4.2. Blockchain for Component Lifecycle Integrity Verification

• Enabling Description: For high-value components in critical supply chains (e.g., avionics, server CPUs), the status of the peripheral guard trace is cryptographically signed and recorded on a distributed ledger (blockchain) at each stage of manufacturing, shipping, and installation. A device's unique ID is paired with the initial (pristine) state of its guard trace. At each handover point, a trusted oracle reads the trace's status (e.g., resistance value). If the value is unchanged, a new "integrity verified" transaction is added to the component's blockchain record. If a break is detected, the transaction is flagged as "damaged." This creates an immutable, auditable, and trustless record of the component's physical integrity throughout its entire lifecycle.
• Mermaid Diagram:

  sequenceDiagram
      participant Factory
      participant Shipper
      participant Integrator
      participant Blockchain
  
      Factory->>Blockchain: Create Asset (DeviceID, Initial_Trace_State)
      Factory->>Shipper: Transfer Physical Device
      Shipper->>Blockchain: Read Trace_State, add "Integrity_OK" Transaction
      Shipper->>Integrator: Transfer Physical Device
      Note over Integrator: Device is dropped, trace breaks
      Integrator->>Blockchain: Read Trace_State, add "Integrity_FAIL" Transaction
      Blockchain-->>Integrator: Immutable record shows damage occurred under Integrator's custody.
  

5. The "Inverse" or Failure Mode Derivatives

5.1. Fused Guard Trace for Controlled Device Decommissioning

• Enabling Description: The guard trace is designed as a programmable fuse. It is fabricated from a material with a low melting point or a specific chemical sensitivity. For secure data applications, a "wipe" command sent to the device would apply a high current pulse to the trace, causing it to vaporize. The destruction of this trace is physically linked to a charge-dump circuit for onboard flash memory, ensuring that the data is irretrievably erased at the same moment the device is physically "tampered" or decommissioned. This creates a secure, fail-safe sanitization mechanism where physical destruction is a required part of the data wipe protocol.
• Mermaid Diagram:

  flowchart TD
      A{Receive Secure Wipe Command} --> B[Apply High Current to Fused Trace];
      B --> C{Trace Vaporizes};
      C --> D[Open Circuit Detected];
      D --> E[Trigger Memory Charge-Dump Circuit];
      E --> F[Data Sanitized Irreversibly];
      C --> G[Device logs permanent tamper event];
  

5.2. Multi-Stage Breakaway Trace for Graceful Degradation

• Enabling Description: The peripheral integrity system consists of multiple, nested guard traces (e.g., Trace A, Trace B, Trace C from outermost to innermost). These traces are engineered with progressively higher fracture toughness. Trace A is brittle and breaks with minor edge impacts. Trace B requires a more significant event, and Trace C only breaks with a crack that threatens the primary display area. The device controller responds differently based on which trace is broken.
  • Trace A broken: Display shows a "Maintenance Suggested" icon.
  • Trace B broken: Display enters a low-power mode, reduces brightness and refresh rate, and warns of imminent failure.
  • Trace C broken: Display is disabled completely to prevent further damage or unsafe operation.
    This enables a graceful degradation of functionality rather than a sudden, catastrophic failure.
• Mermaid Diagram:

  stateDiagram-v2
      state "Fully Functional" as S0
      state "Maintenance Suggested" as S1
      state "Low Power Mode" as S2
      state "Disabled" as S3
  
      [*] --> S0
      S0 --> S1: Outer Trace A Breaks
      S1 --> S2: Middle Trace B Breaks
      S2 --> S3: Inner Trace C Breaks
      S0 --> S2: Trace A & B Break Simultaneously
      S0 --> S3: All Traces Break
      S1 --> S3: Trace B & C Break
  

---

Combination Prior Art Scenarios with Open-Source Standards

1. Combination with MIPI DSI-2 Standard: The guard trace integrity status is embedded into the MIPI Display Serial Interface 2 (DSI-2) protocol's data stream. A custom packet type is defined within the protocol's blanking periods to transmit the status (e.g., resistance, capacitance, or binary continuity) from the display panel's timing controller (TCON) to the host system-on-a-chip (SoC). This avoids the need for separate physical I/O lines for inspection, integrating the physical health status directly into the standard display data link layer. A device driver on the host processor would then parse these packets and report the physical integrity to the operating system.

2. Combination with KiCad Hardware Design Standard: A standardized "Integrity Guard Trace" footprint and routing guide is developed as an open-source library component for the KiCad electronic design automation (EDA) suite. The library includes pre-designed trace patterns (e.g., serpentine traces for flex PCBs, castellated pads for inspection points) and design rules for clearance and width based on substrate type (FR-4, polyimide, glass). This enables hardware designers to easily and consistently implement the guard trace feature in their open-source hardware designs by simply dropping the component into their layout and following the provided routing guide, standardizing its implementation across the industry.

3. Combination with Prometheus Monitoring System: The IoT sensor node monitoring the guard trace (as described in 4.1) exposes its metrics via an HTTP endpoint formatted for consumption by the Prometheus open-source monitoring and alerting toolkit. The metrics would include guard_trace_resistance_ohms, guard_trace_capacitance_farads, and guard_trace_continuity_binary. System administrators can then use Prometheus Query Language (PromQL) to build dashboards (e.g., in Grafana) and configure alerts (via Alertmanager) that trigger when these physical integrity metrics cross predefined thresholds, integrating the hardware health of a fleet of devices into standard cloud-native IT infrastructure monitoring practices.