Obviousness

As a senior US patent analyst, I have analyzed US Patent No. 9,507,477 ('477 patent) in view of the prior art. The following analysis outlines grounds for an obviousness rejection under 35 U.S.C. § 103.

Analysis of Obviousness for US Patent 9,507,477

The '477 patent describes a display device that incorporates a coordinate input device (like a touch panel) and features a dedicated "second signal interconnect." This interconnect is a conductive line placed near the periphery of the transparent substrate, outside the regular signal lines. Its purpose is to facilitate the detection of physical defects such as chipping or cracking of the substrate. A break in this peripheral interconnect, which can be easily tested for electrical continuity, indicates a high probability of damage to the functional signal interconnects located inward from it.

The key claims of the '477 patent, including independent claim 1, describe:

• A coordinate input device with a transparent substrate.
• Detection electrodes within a detection region.
• A "first signal interconnect" connecting the detection electrodes to electrode terminals.
• A "second signal interconnect" located outside the first signal interconnect, near the substrate's peripheral edge.
• This second signal interconnect surrounds the detection region and the first signal interconnect area.
• The second signal interconnect is an open loop, with its ends connected to respective electrode terminals for inspection.

An obviousness rejection under 35 U.S.C. § 103 requires a finding that the claimed invention would have been obvious to a person of ordinary skill in the art (a "POSITA") at the time the invention was made. This often involves combining elements from two or more prior art references.

Based on the prior art cited in the '477 patent's "Description of the Prior Art" section, a strong case for obviousness can be constructed by combining the teachings of JP-A-2002-350896 ("Hoshino") with the general knowledge in the art regarding manufacturing and the problems of substrate defects.

Primary Reference: JP-A-2002-350896 (Hoshino)

• What it Discloses: Hoshino describes a liquid crystal display device where common interconnects are arranged in parallel and connected to each other at the peripheral edge of the display screen. This arrangement enables the detection of disconnection in the common interconnects. The '477 patent itself characterizes Hoshino as a method for detecting interconnect defects ('477 patent, Description of the Prior Art).

• Limitations: The '477 patent distinguishes Hoshino by stating that it "requires inspection on every signal interconnect, it may take extremely much time as is the case with the final inspection." ('477 patent, Summary of the Invention). This implies Hoshino's method is complex, but it squarely places the problem of interconnect defect detection and the use of peripheral wiring for testing in the public domain.

Motivation to Combine and Modify

A POSITA in the field of display manufacturing would have been well aware of the problem of substrate chipping and cracking, especially after the dicing or cutting process, as noted in the background of the '477 patent itself. Such defects are a known cause of interconnect failure. The '477 patent highlights the difficulty of visually inspecting these defects, particularly after the touch panel is bonded to the display and a light-shielding film is applied.

Hoshino teaches the general concept of using electrical tests to find interconnect breaks. A POSITA, faced with the need for a simpler, faster inspection method than Hoshino's per-line test, would have been motivated to develop a go/no-go test. The goal would be a quick screen to identify potentially defective units early in the manufacturing process, before more costly and time-consuming final inspections.

The motivation is therefore to simplify the inspection process taught by Hoshino to create a more efficient manufacturing workflow.

A POSITA would logically conceive of creating a single, dedicated test line that runs along the most vulnerable part of the substrate—the periphery. It is common knowledge that chipping and cracks originate from the edges. Placing a single conductive loop (the "second signal interconnect") along this periphery provides a simple and effective "tripwire." If this outer line is broken, it is highly likely that the substrate edge has been compromised, and the inner, functional signal lines ("first signal interconnect") are also at high risk of being damaged.

This modification of Hoshino's approach is not an inventive leap but rather an engineering trade-off: sacrificing the granularity of knowing which specific line is broken (as in Hoshino) for the speed and simplicity of knowing if a defect likely exists at all. This is a classic engineering optimization that a POSITA would be expected to make.

Conclusion

The claims of US Patent 9,507,477 would have been obvious over JP-A-2002-350896 in view of the general knowledge of a person of ordinary skill in the art.

1. Hoshino teaches the use of electrical interconnects at the periphery of a display substrate for the purpose of detecting line disconnection defects.
2. A POSITA would have been motivated to simplify Hoshino's method to create a faster, less complex go/no-go inspection to screen for substrate chipping and cracking, which are known to occur at the substrate edge.
3. This motivation would have led the POSITA to design a single, dedicated test interconnect running along the periphery of the substrate, outside the functional signal lines. A simple continuity test across this single line would be sufficient to determine if the substrate edge has been compromised. This arrangement is precisely what is claimed as the "second signal interconnect" in the '477 patent.

Therefore, the combination of Hoshino's teachings with the well-understood problems and motivations in display manufacturing would render the claims of the '477 patent obvious.