Obviousness

To analyze the obviousness of U.S. Patent 9,423,424 under 35 U.S.C. § 103, we identify combinations of prior art references that would render the claims obvious and explain the motivation a person having ordinary skill in the art (PHOSITA) would have had to combine them. The analysis focuses on Claim 1, the sole independent claim of the patent.

Claim 1 Breakdown:
Claim 1 describes a probe module comprising:

1. An upper guide plate with through holes.
2. A lower guide plate with through holes, spaced beneath the upper guide plate.
3. A plurality of probes slidably inserted through the holes of both plates, with tips for contacting a device under test (DUT), and being elastically deformable between the plates.
4. A current-diverting circuit trace disposed on the first surface of the plate body of the lower guide plate.
5. At least two probes electrically connected with the current-diverting circuit trace of the lower guide plate.
6. The lower guide plate further comprising conducting layers each provided at a periphery wall of one of its through holes and electrically connected with the current-diverting circuit trace.

Identified Prior Art and Its Relevance:

The background section of US9423424B2 explicitly details the state of the art and its shortcomings, providing a basis for an obviousness analysis.

1. Conventional Probe Module (FIG. 1 of US9423424B2): This reference depicts a conventional probe module 10 comprising an upper guide plate 11, a lower guide plate 12, and a plurality of probes 13. The probes 13 are inserted through guide holes in both plates and are designed to deform elastically, providing a stable contact force and buffering effect when contacting a DUT. The patent explicitly states that this conventional module suffers from the problem where "the slim probe tends to burn out due to instantaneous overcurrent."

   This conventional module already teaches elements 1, 2, 3 (upper guide plate, lower guide plate, and probes that slide and deform between them).

2. U.S. Pat. No. 4,622,514 and U.S. Pat. No. 7,417,447: These patents are cited in US9423424B2's background as examples of probe modules with guide plates that also "may have the above-mentioned problem, i.e. the slim probe tends to burn out due to instantaneous overcurrent." While specific structural details are not provided in US9423424B2's text, their mention reinforces the prevalence of probe modules facing this overcurrent issue.

Differences Between Claim 1 and the Prior Art:

The key differences between Claim 1 and the conventional probe modules lie in the specific mechanism for current diversion:

• The presence of a current-diverting circuit trace on a guide plate.
• Conducting layers within the through holes of the guide plate, electrically coupling the probes to this circuit trace.

Obviousness Combination and Motivation:

A person having ordinary skill in the art (PHOSITA) in semiconductor probe card design would be familiar with the structure and function of conventional probe modules, such as that shown in FIG. 1 of US9423424B2. The problem of "slim probe" burnout due to "unexpected excessive instantaneous current" is explicitly acknowledged as a deficiency of this prior art. This clearly establishes a long-felt but unsolved need and a strong motivation for a PHOSITA to find a solution.

Combination 1: Conventional Probe Module (e.g., FIG. 1 of US9423424B2) + General Knowledge of Overcurrent Protection and Printed Circuit Board (PCB) Manufacturing Techniques.

• Primary Reference: The "conventional probe module 10" (FIG. 1) provides the basic structure of a probe module with upper and lower guide plates and probes.
• Problem Identified: The explicit recognition that these conventional probes "may easily burn out due to an unexpected excessive instantaneous current running therethrough" serves as the primary motivation for a PHOSITA to modify the design.
• Motivation to Combine: Faced with the known problem of probe burnout, a PHOSITA would be motivated to incorporate a mechanism to protect the probes from excessive current. The concept of diverting excessive current through an alternative, lower-resistance path is a fundamental principle in electrical engineering and is widely applied in various electrical circuits for overcurrent protection.
• Known Electrical Engineering & PCB Techniques:
  • Current-diverting circuit trace: The idea of creating conductive paths (circuit traces) on a substrate to route or divert electrical current is a basic practice in printed circuit board (PCB) design. A PHOSITA would recognize that a conductive trace on the surface of a guide plate could serve as such a current-diverting path.
  • Conducting layers in through holes: The patent itself provides a crucial insight, stating that "a plated through hole that is commonly used in printed circuit board can be substituted for the conducting hole structure produced by the through hole 36 and the conducting layer 40." This indicates that the concept of a conductive lining within a through hole to establish an electrical connection is well-known in the art of PCB manufacturing. Therefore, incorporating a conductive layer (e.g., a plated through hole) on the periphery wall of the guide plate's through holes to ensure electrical contact with the probes and the current-diverting circuit trace would be an obvious design choice for a PHOSITA.
  • Electrical Connection: Connecting the probes to these conductive layers, and then connecting these layers to the circuit trace, would be a straightforward application of known electrical connection techniques.

Conclusion:

A PHOSITA, understanding the inherent vulnerability of slim probes in conventional probe modules to instantaneous overcurrent (as explicitly taught by the patent's background), would seek to implement a solution using known electrical engineering principles. The combination of the conventional probe module structure with the well-understood concepts of current diversion using conductive traces on a substrate (like a PCB) and conductive "plated through holes" to make electrical contact, would render the subject matter of Claim 1 obvious. The motivation is directly provided by the recognized problem of probe burnout and the readily available solutions within the broader electrical and PCB manufacturing arts.