Prior art — US Patent 9201834

To identify the most relevant prior art for US patent 9201834, I will search the USPTO database for the patent and then analyze its cited references. The USPTO provides tools like Patent Public Search for this purpose, where prior art includes patents, printed publications, public use, sales, or other publicly available information before the effective filing date of the claimed invention. Patent examiners consider both prior art they discover and prior art submitted by applicants via Information Disclosure Statements (IDS).

I will now proceed with finding the patent on the USPTO database to extract the cited prior art.

Most Relevant Prior Art for US Patent 9201834

Upon reviewing the patent document US9201834B2, the following prior art references are cited. These references were likely considered by the patent examiner during the prosecution of US9201834.

The following are the "U.S. Patent Documents" cited in US9201834:

US 6,243,300 B1
- Inventors: Merritt; Douglas A.
- Publication Date: June 5, 2001
- Brief Description: This patent describes a semiconductor memory device with multiple memory arrays and a data transfer bus. It focuses on efficiently transferring data between the memory arrays and an external device using a wide internal bus.
- Potential Anticipation for US9201834 Claims: This patent could potentially anticipate elements of Claim 1 and Claim 2 of US9201834, particularly concerning the "type of memory cell array group" comprising multiple memory ICs, and the concept of a "first transmission bus" with a wider bus width than the I/O data bus of individual memory ICs for transmitting parallel data. The programmable aspects of US9201834's buses would likely be the differentiating factor.
US 6,556,478 B2
- Inventors: Tanaka; Koji
- Publication Date: April 29, 2003
- Brief Description: This patent details a semiconductor memory device and system with a high-speed internal bus structure and a controller for managing data transfer, including features for adjusting data rates.
- Potential Anticipation for US9201834 Claims: Similar to US 6,243,300 B1, this reference might anticipate the basic structure of memory arrays, a logic unit, and a transmission bus as described in Claim 1 of US9201834. The key distinguishing feature for US9201834 would be the programmable nature of the data rates and signal swings on its transmission buses.
US 7,203,778 B2
- Inventors: Kirihata; Toshiaki et al.
- Publication Date: April 10, 2007
- Brief Description: This patent describes a semiconductor memory device that can operate at various data rates and voltage swings, allowing for flexible operation modes.
- Potential Anticipation for US9201834 Claims: This reference is highly relevant to Claim 1 of US9201834, especially regarding the "programmable transmitting or receiving data rate" and "programmable transmitting or receiving signal swing" of the first and second transmission buses. The scope of "programmable" in US9201834's claims and how it differs from the flexible operation modes in US 7,203,778 B2 would be critical in assessing anticipation.
US 7,370,166 B2
- Inventors: Lee; Kye Hyun et al.
- Publication Date: May 6, 2008
- Brief Description: This patent describes a memory module with stacked memory devices and an interposer, focusing on improving signal integrity and reducing noise in high-speed memory systems.
- Potential Anticipation for US9201834 Claims: This patent could be relevant to the structural aspects mentioned in the detailed description of US9201834, particularly those related to stacking memory ICs and using interposers (e.g., as described in FIGS. 4-6 and associated text). While not directly addressing the programmable bus features of Claim 1, it provides context for the physical implementation of high-speed memory modules.
US 7,921,228 B2
- Inventors: Oku; Yuji et al.
- Publication Date: April 5, 2011
- Brief Description: This patent discusses a stacked semiconductor device with through-silicon vias (TSVs) for interconnections between stacked chips, aiming to reduce package size and improve performance.
- Potential Anticipation for US9201834 Claims: This patent is particularly relevant to Claim 5 of US9201834, which specifies the presence of "at least one through silicon via (TSV) exists within a non-active circuit region surrounding or partially surrounding an active circuit region of each of the memory cell array ICs." The general concept of using TSVs in stacked memory is covered, but the specific placement "within a non-active circuit region" and the stated benefits (e.g., EMI shielding, heat dissipation, noise isolation as discussed in the detailed description of US9201834) would need to be carefully compared.
US 8,245,091 B2
- Inventors: Kim; Hong Seok et al.
- Publication Date: August 14, 2012
- Brief Description: This patent describes a semiconductor memory device and system with reconfigurable input/output (I/O) interfaces, allowing for flexible configuration of data width and operating modes.
- Potential Anticipation for US9201834 Claims: This patent is highly relevant to Claim 1 and Claim 3 of US9201834 due to its focus on reconfigurable I/O interfaces and flexible configuration of data width. The programmable bus width (Claim 3) and programmable data rate/signal swing (Claim 1) in US9201834 would need to demonstrate novel distinctions from the reconfigurable aspects of US 8,245,091 B2 to overcome potential anticipation.
US 2004/0009653 A1
- Inventors: Kumamoto; Yoshihiro
- Publication Date: January 15, 2004
- Brief Description: This application describes a semiconductor device with a reconfigurable data bus width and control signals to support different memory configurations.
- Potential Anticipation for US9201834 Claims: This publication is relevant to Claim 1 and Claim 3, especially concerning the "first programmable bus width" and "first programmable data width" of the first transmission bus. The reconfigurable data bus width described could potentially anticipate the programmable bus width aspects of US9201834.
US 2008/0022066 A1
- Inventors: Lin; Yen-Chih et al.
- Publication Date: January 24, 2008
- Brief Description: This application details a memory system with multiple memory devices and a controller that can adjust operating parameters, including data rates and signal swings, for efficient operation.
- Potential Anticipation for US9201834 Claims: This reference is highly relevant to Claim 1 due to its discussion of adjusting operating parameters such as data rates and signal swings. The specific definition and implementation of "programmable" in US9201834 for both transmitting and receiving would be key to differentiating it from this prior art.
US 2009/0070542 A1
- Inventors: Lin; Yen-Chih et al.
- Publication Date: March 12, 2009
- Brief Description: This application describes a memory device with a flexible interface that can be configured for different bus widths and data transfer modes.
- Potential Anticipation for US9201834 Claims: Similar to US 2004/0009653 A1 and US 2008/0022066 A1, this publication is relevant to Claim 1 and Claim 3, as it describes a flexible interface configurable for various bus widths and data transfer modes, potentially anticipating the programmable bus width, data width, and address width of US9201834's transmission buses.
US 2011/0088019 A1
- Inventors: Li; Qi et al.
- Publication Date: April 14, 2011
- Brief Description: This application discloses methods and apparatus for configuring a memory controller to optimize performance based on memory characteristics and system requirements.
- Potential Anticipation for US9201834 Claims: This reference could be relevant to the underlying concept of optimizing memory performance through configuration, which underpins the "programmable" features of US9201834's transmission buses in Claim 1. However, the specific inventive steps in US9201834 related to the reconfigurable high-speed memory chip module itself and its two distinct programmable buses would be the focus of differentiation.